CN1574290A - 制造半导体元件的方法 - Google Patents
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Abstract
本发明提供一种制造半导体元件的方法，有效地防止了由于自然氧化膜所引起的接触电阻的增加。该方法包括：(1)制备一半导体衬底，其上形成了一具有结区的下部结构；(2)形成一层间介电膜于上述半导体衬底的整个表面上；(3)通过蚀刻层间介电膜而形成暴露出结区的接触孔；(4)顺序地进行干式清洗和湿式清洗由接触孔所露出的半导体衬底的表面；(5)在一还原性气体气氛下对已清洗的接触表面进行预处理，以去除形成于接触表面上的自然氧化膜；(6)追加原位掺入掺杂剂至结区的表面，以便补偿在预处理后的接触表面上的掺杂剂损失；以及(7)原位沉积一导电膜于接触孔及层间介电膜上。
Description
技术领域
本发明涉及一种制造半导体元件的方法，特别是有关于可防止由于自然氧化膜所引起接触电阻(contact resistance)增加的半导体元件的制造方法。
背景技术
如众所周知，除了半导体技术的进步以外，高速操作与高度集成化的半导体元件的发展也在积极地进行中。因此，要求图形(pattern)的精细对准与高度集成化。依照此一倾向，多种工艺技术也已开发并用来获得优良的元件性能。
特别是，为了增进半导体元件的操作效率，新的接触工艺技术业已开发。在此接触工艺技术中，当介于上和下部图形(pattern)之间的接触不稳定，或者接触电阻增加时，虽然图形(pattern)的微细化可以达成，但是半导体元件的可靠度却缺乏，且难以执行高速动作。
以下，简要说明一种传统的接触工艺。
图1A至图1C是断面图，说明一传统的制造半导体元件的方法。
请参看图1A，制备一硅衬底1，在硅衬底1上形成了具有结区(junctionregion)2的预定的下部结构。一层间介电膜3被沉积在硅衬底1的整个表面上，以覆盖下部结构。一蚀刻掩模，例如，一光致抗蚀剂图形4利用公知的工艺形成于层间介电膜3上。该光致抗蚀剂图形4定义了一接触形成区。
请参见图1B，层间介电膜3藉由使用光致抗蚀剂图形4被蚀刻。因此，形成了一露出结区2的接触孔5。去除作为蚀刻掩模的光致抗蚀剂图形4。
请参见图1C，一导电膜，例如，一金属膜被沉积在层间介电膜3上，以埋入接触孔5。金属膜被构图以形成一与硅衬底1的结区2相接触的金属布线6。
当形成金属布线6时，一中间插入物质(intermediate plug material)，亦即，一多晶硅膜7可被插入金属布线6与结区2之间，其情形如图2所示。在图2中，参考标记8代表一氧化物膜。
传统地，在制造半导体元件时，在接触蚀刻期间所生成的蚀刻残留物及衬底表面的自然氧化膜应该予以去除。为了修复蚀刻所造成的损伤，在接触孔形成以后，使用NF3/O2、SF6/O2、CF4/O2、或Ar/O2的等离子干式清洗与湿式清洗工艺被依序进行，然后，沉积一金属膜。
然而，在形成接触导电膜期间，由于在被清洗的衬底表面暴露于空气之后，完成在溅射(sputtering)装置中沉积金属膜或在化学气相沉积装置中沉积多晶硅膜，如图3所示，无可避免地会在接触表面上形成自然氧化膜10于是，金属布线6与衬底1的结区2之间的实际欧姆接触(ohmic contact)就无法达成，因此增加了接触电阻。这导致半导体元件品质的下降。
为了解决上述问题，传统上是在沉积金属膜之前，以氩等离子体进行物理溅射，作为原位(in-situ)预处理。而且，为了使自然氧化膜的形成最小化，通过多晶硅膜沉积设备，衬底被装入一衬底装入部中，在下述条件下，即：衬底装入部被单独关闭，并且通过高纯度氮的流动，氧的浓度降低到小于100ppm；一设于衬底装入部与一高温沉积管之间的门开启，而衬底则被装入高温沉积管之中。
然而，此步骤只可使自然氧化膜的影响最小化，而不能提供一清洁的接触表面，结果，因为接触面的不良，使接触电阻增加。
发明内容
本发明即是为了解决在现有技术中发生的上述问题，而本发明的一目的是提供一种制造半导体元件的方法，其防止了由于自然氧化膜所导致接触电阻的增加。
为了达成上述的目的，本发明提供一种半导体元件的制造方法，其包括下列步骤：(1)制备一半导体衬底，其上形成了一具有结区的下部结构；(2)形成一层间介电膜于半导体衬底的整个表面上；(3)通过蚀刻层间介电膜而形成暴露出结区的接触孔；(4)顺序地干式清洗和湿式清洗由接触孔所露出的半导体衬底的表面；(5)在还原性气体的气氛下对已清洗的接触表面进行预处理，以去除形成于接触表面上的自然氧化膜；(6)追加原位掺入掺杂剂至结区的表面，使得在预处理期间所造成的掺杂剂损失得以补偿并且在结区表面上的掺杂剂浓度增加；以及(7)原位(in-situ)沉积一导电膜于接触孔及层间介电膜上。
优选地，还原性气体为氢气或氨气。而且，更优选地是，步骤(5)是利用一低温等离子工艺或一高温热处理来进行的。最优选地是，低温等离子工艺是在下列条件下进行的：氢气的流速为1～1000sccm，压强为1～300Torr且温度为室温至600℃。并且，高温热处理是在下列条件下进行的：氢气的流速为1～5slm，压强为1～300Torr，且温度为700～1000℃。
而且，所述步骤(6)包括下列步骤：将包含损失掺杂剂的气体分子供应至设备中，并且进行低温等离子工艺或高温热处理。
依照本发明，在清洗接触孔后，溅射或化学气相沉积设备提供诸如氢气的还原性气体至接触表面，以去除在接触表面上所形成的自然氧化膜。而且，通过追加原位掺杂(additional in-situ doping)步骤，增加了在结区表面上的掺杂剂浓度。此设备原位沉积一接触导电膜于接触表面中，因此，提供了一去除了自然氧化膜的清洁接触表面。于是，有效防止了由于自然氧化膜所引起的接触电阻的增加。
附图说明
下面参照附图详细描述优选具体实施例，本发明的上述和其它目的、特征与优点即可得到明确地了解。
图1A至图1C为截面图，解释一种传统制造半导体元件的方法；
图2是截面图，解释另一种传统制造半导体元件的方法；
图3是截面图，解释传统制造半导体元件的方法所发生的问题；以及
图4A至图4D是截面图，说明根据本发明实施例制造半导体元件的方法。
具体实施方式
以下参考附图说明本发明的优选实施例。在下面的描述和附图中，相同的参考标记用于表示相同或相似的部件，因此省略了对于相同或相似部件的描述。
图4A至图4D是截面图，说明根据本发明实施例制造半导体元件的方法。
请参看图4A，制备了一半导体衬底41，其上形成了一具有结区42的预定下部结构。在结区42中，半导体的导电率是依照掺杂剂的种类、掺杂浓度与掺杂深度而调整。
请参看图4B，一层间介电膜43沉积于硅衬底41的整个表面上，以覆盖具有结区42的下部结构。层间介电膜43是使用一已知的工艺被蚀刻，以形成将结区42露出的接触孔45。
为了修复诸如蚀刻残留物对于衬底接触表面所造成的蚀刻损伤以及硅晶格(lattice)缺陷，进行使用NF3/O2、SF6/O2、CF4/O2或Ar/O2的等离子干式清洗，然后，进行包括二氧化硅膜蚀刻溶液的湿式清洗。
在硅接触(silicon contact)的情况下，等离子干式清洗去除了由接触孔干式蚀刻所积累的物理性损伤。在碳系蚀刻残留物被氧化并被去除之后，残留的氧化物膜乃通过使用氟系化学溶液的湿式清洗被去除。结果，得到清洁的接触表面。
请参看图4C，在没有时间迟延的条件下，所述衬底形成物被装入溅射设备或化学气相沉积设备中。而此溅射设备沉积一接触导电膜，亦即，金属膜。化学气相沉积设备则沉积多晶硅膜。在将衬底形成物装入溅射设备或化学气相沉积设备的过程中，一自然氧化膜产生于接触表面上。因此，在本发明的实施例中，为了去除产生于接触表面上的自然氧化膜，在衬底形成物被装入溅射设备或化学气相沉积设备中之后，在还原性气体的气氛下预处理该接触表面。优选地，在本发明的实施例中，此还原性气体包括氢气或氨气。
所述预处理包括一低温等离子工艺，其在下列条件下进行：氢气以1～1000sccm的速度流动，压强为1～300Torr，温度在室温至600℃的范围内。所述预处理包括一高温热处理，其在下列条件下进行：氢气以1～5slm的速度流动，压强为1～300Torr，且温度在700～1000℃的范围内。此时，由于氢的强还原特性，衬底表面(即，结区42)的掺杂剂与氢结合而形成一氢化物化合物，而此氢化物化合物以气体的形态被释放。于是，形成于接触表面上的自然氧化膜乃被去除以获得一清洁的接触表面。但是，在一磷(P)掺杂结区的情况下，氢也可以与磷(P)结合并以PH3气体的形态释放出来。
当结区42的掺杂剂与氢结合且此氢化合物被释放出来时，所述结区42的导电率变差，且其接触电阻增加。因此，在本发明中，在进行上述的氢预处理后，一包含相应掺杂剂的物质原位地供应至设备中，并且进行低温等离子工艺或高温热处理以补偿结区42中的掺杂剂损失。在磷(P)掺杂结区的情况下，PH3气体以10～1000sccm的速度流动，和在下列条件下产生等离子体：压强为1～300Torr，温度在室温～600℃的范围内；或者，PH3气体以1～5slm的速度流动，在下列条件下进行热分解：压强为1～300Torr，温度为700～1000℃。于是磷(P)被追加掺入接触表面中。
请参看图4D，在进行接触表面的预处理后，在衬底形成物上原位沉积一金属膜，以将接触孔45覆盖。所述金属膜被构图以形成一与结区42接触的金属布线46。然后，顺序进行公知的后续工艺，以获得根据本发明的半导体元件。
藉由在金属布线46与结区42之间插入一中间插入物质，例如多晶硅膜，可以实现金属布线46与结区42之间的接触。插入物质是通过一回蚀刻(etchback)工艺或化学机械抛光(CMP，Chemical Mechanical Polishing)工艺形成的。通过沉积与蚀刻氧化物膜而形成接触孔。然后，形成一与中间插入物质相接触的金属布线46。
依照本发明，由于利用相同的设备，以原位(in-situ)的方式，顺序进行下列操作：使用还原性气体例如氢气的预处理，用来补偿损失的掺杂剂的追加掺杂，以及接触导电膜的沉积；因此形成的金属布线具有理想的欧姆接触表面(ohmic contact surface)。因此，在利用依照本发明的方法所制造的半导体元件中，自然氧化膜从接触表面完全被去除，引起接触电阻降低。
依照本发明，在接触孔被清洗以后，溅射或化学气相沉积装置供应例如氢气的还原性气体至一接触表面，以去除形成于接触表面上的自然氧化膜。而此装置原位沉积一接触导电膜至接触表面中，以提供一已去除所述自然氧化膜的清洁接触表面。于是，其有效地防止了由于自然氧化膜所引起的接触电阻的增加。由于本发明在补偿原位预处理期间损失的掺杂剂之后沉积接触导电膜，其防止了元件性能变差。因此，由于本发明形成了理想的欧姆接触，其提高了元件的性能与制造合格率。
以上所述乃是本发明的优选实施例，用于示例，本领域内的技术人员可以理解，在不脱离由所附权利要求保护的本发明的范围和精神的条件下，可以作出各种变化、增加和替换。
Claims (6)
1.一种制造半导体元件的方法，包括下列步骤：
(1)制备一半导体衬底，其上形成了一具有结区的下部结构；
(2)形成一层间介电膜于上述半导体衬底的整个表面上；
(3)通过蚀刻该层间介电膜而形成暴露出该结区的接触孔；
(4)顺序地干式清洗和湿式清洗由该接触孔所露出的该半导体衬底的表面；
(5)在还原性气体的气氛下对已清洗的接触表面进行预处理以去除形成于该接触表面上的自然氧化膜；
(6)追加原位掺入掺杂剂至该结区的表面，使得在预处理后的接触表面上的掺杂剂损失得以补偿；以及
(7)原位沉积一导电膜于上述接触孔及层间介电膜上。
2.如权利要求1所述的方法，其中还原性气体包括氢气或氨气。
3.如权利要求1所述的方法，其中步骤(5)是利用一低温等离子工艺或一高温热处理来进行的。
4.如权利要求3所述的方法，其中低温等离子工艺是在下列条件下进行的：氢气以1～1000sccm的速度流动，压强为1～300Torr，温度为室温～600℃。
5.如权利要求3所述的方法，其中所述高温热处理是在下列条件下进行的：氢气以1～5slm的速度流动，压强为1～300Torr，温度为700～1000℃。
6.如权利要求1所述的方法，其中所述步骤(6)包括下列操作：供应包含损失掺杂剂的物质至设备中，并进行低温等离子工艺或高温热处理。
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102315161A (zh) * | 2010-07-07 | 2012-01-11 | 海力士半导体有限公司 | 具有侧结的半导体器件的制造方法 |
| CN101593678B (zh) * | 2008-05-30 | 2012-05-16 | 中芯国际集成电路制造(北京)有限公司 | 掺杂区形成方法 |
| CN101969048B (zh) * | 2009-07-27 | 2012-07-25 | 中芯国际集成电路制造(上海)有限公司 | 存储器件的制作方法 |
| CN101724896B (zh) * | 2009-11-26 | 2012-08-08 | 上海宏力半导体制造有限公司 | 一种非选择性生长锗硅外延的方法 |
| CN104091762A (zh) * | 2014-07-16 | 2014-10-08 | 上海先进半导体制造股份有限公司 | 双极型晶体管的制备方法 |
| CN108538780A (zh) * | 2018-04-18 | 2018-09-14 | 睿力集成电路有限公司 | 位线/存储节点接触栓塞和多晶硅接触薄膜的制造方法 |
| CN110911265A (zh) * | 2018-09-17 | 2020-03-24 | 长鑫存储技术有限公司 | 在氮化钛生成工艺中去除氧化硅的方法 |
| CN111446156A (zh) * | 2020-04-03 | 2020-07-24 | 合肥晶合集成电路有限公司 | 半导体结构的形成方法及半导体结构 |
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| CN103346126A (zh) * | 2013-06-26 | 2013-10-09 | 上海宏力半导体制造有限公司 | 闪存存储单元的形成方法 |
| US20150093889A1 (en) * | 2013-10-02 | 2015-04-02 | Intermolecular | Methods for removing a native oxide layer from germanium susbtrates in the fabrication of integrated circuits |
| US11088147B2 (en) | 2019-06-26 | 2021-08-10 | Micron Technology, Inc. | Apparatus with doped surfaces, and related methods with in situ doping |
| CN114063320B (zh) * | 2020-07-31 | 2024-09-17 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
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| JPH0618236B2 (ja) | 1987-07-01 | 1994-03-09 | 富士電機株式会社 | 半導体素子の製造方法 |
| JPH0669152A (ja) * | 1992-08-20 | 1994-03-11 | Matsushita Electron Corp | 半導体装置およびその製造方法 |
| JP2978748B2 (ja) | 1995-11-22 | 1999-11-15 | 日本電気株式会社 | 半導体装置の製造方法 |
| JP4663038B2 (ja) * | 1997-05-28 | 2011-03-30 | 三菱電機株式会社 | コンタクトホールの形成方法 |
| JPH11204455A (ja) * | 1998-01-13 | 1999-07-30 | Sony Corp | 半導体装置の製造方法 |
| US6242331B1 (en) * | 1999-12-20 | 2001-06-05 | Taiwan Semiconductor Manufacturing Company | Method to reduce device contact resistance using a hydrogen peroxide treatment |
| JP2003115462A (ja) * | 2001-10-05 | 2003-04-18 | Kawasaki Microelectronics Kk | コンタクト構造の形成方法 |
| KR100451504B1 (ko) * | 2001-10-08 | 2004-10-06 | 주식회사 하이닉스반도체 | 반도체소자의 플러그 형성방법 |
| KR100431295B1 (ko) * | 2001-10-12 | 2004-05-12 | 주식회사 하이닉스반도체 | 반도체소자의 플러그 형성방법 |
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2003
- 2003-05-21 KR KR10-2003-0032210A patent/KR100518228B1/ko not_active IP Right Cessation
- 2003-11-07 TW TW092131157A patent/TWI234203B/zh not_active IP Right Cessation
- 2003-11-07 US US10/704,231 patent/US6979633B2/en not_active Expired - Fee Related
- 2003-11-12 JP JP2003383104A patent/JP4508607B2/ja not_active Expired - Fee Related
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| CN101969048B (zh) * | 2009-07-27 | 2012-07-25 | 中芯国际集成电路制造(上海)有限公司 | 存储器件的制作方法 |
| CN101724896B (zh) * | 2009-11-26 | 2012-08-08 | 上海宏力半导体制造有限公司 | 一种非选择性生长锗硅外延的方法 |
| CN102315161A (zh) * | 2010-07-07 | 2012-01-11 | 海力士半导体有限公司 | 具有侧结的半导体器件的制造方法 |
| CN102315161B (zh) * | 2010-07-07 | 2015-03-25 | 海力士半导体有限公司 | 具有侧结的半导体器件的制造方法 |
| CN104091762A (zh) * | 2014-07-16 | 2014-10-08 | 上海先进半导体制造股份有限公司 | 双极型晶体管的制备方法 |
| CN108538780A (zh) * | 2018-04-18 | 2018-09-14 | 睿力集成电路有限公司 | 位线/存储节点接触栓塞和多晶硅接触薄膜的制造方法 |
| CN110911265A (zh) * | 2018-09-17 | 2020-03-24 | 长鑫存储技术有限公司 | 在氮化钛生成工艺中去除氧化硅的方法 |
| CN111446156A (zh) * | 2020-04-03 | 2020-07-24 | 合肥晶合集成电路有限公司 | 半导体结构的形成方法及半导体结构 |
Also Published As
| Publication number | Publication date |
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| JP2004349676A (ja) | 2004-12-09 |
| CN1282999C (zh) | 2006-11-01 |
| KR100518228B1 (ko) | 2005-10-04 |
| KR20040100015A (ko) | 2004-12-02 |
| JP4508607B2 (ja) | 2010-07-21 |
| US20040235282A1 (en) | 2004-11-25 |
| US6979633B2 (en) | 2005-12-27 |
| TWI234203B (en) | 2005-06-11 |
| TW200426942A (en) | 2004-12-01 |
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