CN100341136C - 内联机结构的形成方法及铜制程整合方法 - Google Patents

内联机结构的形成方法及铜制程整合方法 Download PDF

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CN100341136C
CN100341136C CNB2004100571377A CN200410057137A CN100341136C CN 100341136 C CN100341136 C CN 100341136C CN B2004100571377 A CNB2004100571377 A CN B2004100571377A CN 200410057137 A CN200410057137 A CN 200410057137A CN 100341136 C CN100341136 C CN 100341136C
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supercritical fluid
dielectric layer
opening
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CN1645592A (zh
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曾伟雄
庄平
涂宏荣
王静亚
林俞良
罗冠腾
周梅生
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明揭示一种半导体装置中蚀刻后续清洁制程(post-etchingcleaning process)与沉积制程的整合方法。首先，提供一基底，其中具有一镶嵌结构，其藉由蚀刻一介电层并利用为于其上方的一光阻掩膜作为蚀刻掩膜而形成。接着，藉由一超临界流体实施一清洁制程，以去除光阻掩膜以及蚀刻后续产生的副产品。最后，利用该超临界流体作为一反应媒介，以临场(in-situ)填入一内联机层于镶嵌结构内。上述清洁制程与后续内联机层的制作是于一制程设备的单一或不同的反应室中进行。

Description

内联机结构的形成方法及铜制程整合方法
技术领域
本发明是有关于一种半导体制程，特别是有关于一种在一具有单一个或多数个反应室的半导体制程设备中整合蚀刻后续清洁制程(post-etchingcleaning process)与沉积制程。
背景技术
在集成电路或是微电子装置的制造中，多层导线结构是使用于集成电路中的单一或多个装置的内联机(interconnect)区。传统上是采用双镶嵌(dualdamascene)制程形成上述内联机结构。
双镶嵌制程一开始是先于一硅晶片上沉积一介电层，例如一低介电常数(k)材料层，以作为一金属层间介电(intermetal dielectric，IMD)层。随后实施微影及蚀刻制程以在IMD层中形成一沟槽或接触窗开口或是由这些开口所成的双镶嵌开口。最后，在开口中沉积一金属层，例如铜层或铝层，以完成内联机结构的制作。
传统上，藉由蚀刻制程在IMD层中形成开口之后，反应室中的晶片会实施一清洁制程以去除光阻掩膜及蚀刻后续产生的副产品(post-etchingby-products)，例如聚合物或是其它化学残留物。之后，将晶片从反应室移出以等候后续进行沉积制程或是金属化制程。在等候期间(称做制程等待时间(queue time，Q-time))，晶片是暴露于大气中，导致原生(native)氧化物形成硅晶片表面或是不必要的氧化物形成于晶片的下层金属层表面而不利于后续的制程。为了去除上述氧化物，是于进行沉积制程之前，额外实施一电浆清洁制程，但却因此而损及低介电常数材料层的表面。再者，低介电常数材料层在等候进行沉积制程时，容易与蚀刻后续产生的副产品相互作用或是吸收到水气而导致介电特性退化。
另外，光阻掩膜的去除通常采用电浆去除法。然而，电浆会损害低介电常数材料层，同样会导致介电特性退化。再者，电浆去除法并无法完全去除光阻掩膜，因为聚合物会形成于光阻掩膜的侧壁，而不利于后续制程的进行。
美国专利第6,184,132号是揭示一种半导体装置中硅化钴的整合制程，其利用临场(in-situ)电浆清洁制程以在进行钴沉积之前去除形成于硅基底上的原生氧化物。然而，如以上所述，于清洁期间，电浆容易损害基底表面。另外，美国专利第6,395,642号是揭示一种改良的铜制程整合方法，其是整合进行铜电镀之前的铜晶种层制作与电浆清洁制程。藉由此方法，铜氧化物可有效地除去，以增加铜内联机的品质。然而，于去除光阻掩膜与金属沉积步骤之间仍存在制程等候时间(Q-time)。
因此，有必要寻求新的方法来解决因上述制程等候时间所引发的问题，以维持介电层的介电特性。
发明内容
有鉴于此，本发明的目的在于提供一种藉由整合蚀刻后续清洁制程与沉积制程来避免具有低介电常数(lowk)材料层形成其上的一基底于金属沉积前暴露于大气中的方法，藉以克服制程等待时间(queue time)所引发的问题并增加产能。
本发明的另一目的在于提供一种利用超临界流体(supercriticalfluid)技术来进行蚀刻后续清洁制程及随后的沉积制程的方法，以取代传统电浆技术，进而有效地去除蚀刻后续产生的副产品(post-etchingby-products)并防止低介电常数材料层的损害。
本发明的又另一目的在于提供一种具有一内联机结构的半导体装置，其中内联机结构的形成是采用超临界流体作为清洁制程的清洁剂并作为沉积制程的反应媒介。
根据上述的目的，本发明提供一种内联机结构的形成方法。首先，提供一基底，其上覆盖有一介电层，该介电层具有由位于其上方的一掩膜图案层所定义出的至少一开口。之后，藉由一超临界流体实施一清洁制程，以去除该掩膜图案层以及形成于介电层表面及开口内表面的蚀刻副产品。最后，藉由超临界流体作为反应媒介以临场填入一导电层于开口内，而完成内联机结构。此处，清洁制程的实施及临场填充开口是于一制程设备的一制程反应室或是具有多个反应室的制程设备的不同制程反应室中进行。
上述介电层可为一低介电常数材料层且掩膜图案层可为一光阻图案层。
再者，使用于清洁制程的超临界流体可为超临界二氧化碳，且其更包括一化学清除剂溶解其中，其包括HF、NMP、CH3COOH、MeOH、BLO、H2SO4、HNO3、H3PO4、或TFAA。
再者，导电层是利用一有机金属错合物作为沉积前驱物并利用超临界二氧化碳作为反应媒介而形成的，其中有机金属错合物包括Cu(hfac)(2-butyne)。
根据上述的另一目的，本发明提供一种铜制程整合方法。首先，提供一基底，其上覆盖有一介电层，介电层具有由位于其上方的一掩膜图案层所定义出的一镶嵌开口。接着，藉由一超临界流体实施一清洁制程，以去除掩膜图案层以及形成于介电层表面及镶嵌开口内表面的蚀刻副产品。最后，利用超临界流体作为一反应媒介，以临场填入一铜层于该镶嵌开口内。此处，清洁制程的实施及临场填充开口是于一制程设备的一制程反应室或是具有多个反应室的制程设备的不同制程反应室中进行。
上述介电层可为一低介电常数材料层且掩膜图案层可为一光阻图案层。
再者，使用于清洁制程的超临界流体可为超临界二氧化碳，且其更包括一化学清除剂溶解其中，其包括HF、NMP、CH3COOH、MeOH、BLO、H2SO4、HNO3、H3PO4、或TFAA。
再者，铜层是利用Cu(hfac)(2-butyne)作为沉积前驱物。
又根据上述的另一目的，本发明提供一种半导体装置。此半导体装置包括一基底、一低介电常数材料层、及一内联机结构。低介电常数材料层是设置于基底上方，其具有至少一镶嵌开口位于被一超临界流体所清洁过的一区域中。内联机结构是设置于镶嵌开口内，且其是于实施清洁制程之后，利用超临界流体作为一反应媒介且利用一有机金属错合物作为一沉积前驱物而临场形成的。此处，对镶嵌开口所实施的清洁制程及内联机结构的制作是于一制程设备的一制程反应室或是具有多个反应室的制程设备的不同制程反应室中进行。
再者，使用于清洁制程的超临界流体可为超临界二氧化碳，且其更包括一化学清除剂溶解其中，其包括HF、NMP、CH3COOH、MeOH、BLO、H2SO4、HNO3、H3PO4、或TFAA。
再者，有机金属错合物包括Cu(hfac)(2-butyne)。
附图说明
图1a到图1d是绘示出根据本发明实施例的双镶嵌制程中内联机结构形成方法的剖面示意图。
符号说明：
100～基底；102～介电层；104～掩膜图案层；104a～聚合物层；108～镶嵌开口；110～清洁制程；112～导电层；112a～内联机结构；200～半导体装置。
具体实施方式
为让本发明的上述目的、特征和优点能更明显易懂，下文特举较佳实施例，并配合所附图式，作详细说明如下：
图1a到图1d是绘示出根据本发明实施例的双镶嵌制程中形成内联机结构的方法。首先，请参照图1a，提供一基底100，例如一硅基底或其它半导体基底。此基底100可包含不同的组件，例如晶体管、电阻器、及其它现有的半导体组件。此基底100亦可包含其它绝缘层或金属内联机层。此处，为了简化图式，仅绘示出一平整的基底。
接着，在基底100上方形成一介电层102。再本实施例中，介电层102是作为一内层层间介电(ILD)层或是金属层间介电(IMD)层。举例而言，介电层102可为二氧化硅、磷硅玻璃(PSG)、硼磷硅玻璃(BPSG)、或是其它如掺杂氟的硅玻璃(FSG)的低介电常数(k)材料层。再者，介电层102可藉由现有沉积技术形成，例如电浆辅助化学气相沉积(PECVD)、低压化学气相沉积(LPCVD)、常压化学气相沉积(APCVD)、高密度电浆化学气相沉积(HDPCVD)、或是其它适当的CVD。另外，在沉积介电层102之前，一蚀刻终止层(未绘示)，例如一氮化硅层，可藉由LPCVD并利用SiCl2H2及NH3作为反应源，选择性地沉积于基底100上。再者，一抗反射层(未绘示)，可选择性地沉积于介电层102上方。此处，抗反射层可为氮氧化硅(SiON)，其可藉由CVD并利用SiH4、O2、及N2作为制程气体形成。
之后，在介电层102上方涂覆一掩膜层(未绘示)，例如光阻，接着实施微影制程以形成一掩膜图案层104，其具有至少一开口106以露出部分的介电层102，作为定义镶嵌结构之用。
接下来，请参照图1b，利用掩膜图案层104作为一蚀刻掩膜，以进行传统蚀刻制程，例如反应离子蚀刻(RIE)，蚀刻介电层102以在其中形成一镶嵌开口108。镶嵌开口108可为一沟槽、接触窗开口、或其它开口。
接着，进行本发明的一连串的关键步骤。首先藉由超临界流体，例如超临界二氧化碳(CO2)，实施一清洁制程110以去除掩膜图案层104以及形成于介电层102表面及镶嵌开口108内表面的蚀刻后续产生的副产品。亦即，上述清洁制程110包含了掩膜层剥除制程以及传统的清洁制程。
气体处于超临界态是称做超临界流体。亦即，当环境的压力及温度达到临界态时，气体就会进入超临界态。举例而言，CO2的临界温度约在31℃，且CO2的临界压力约在72.6atm。在本实施例中，清洁制程110的制程温度在31到400℃的范围且制程压力在72到400atm的范围。典型地，超临界流体的密度与液相大体相同时。其扩散性质与黏性相似于气相。因此，可将化学清除剂溶解于超临界流体之中。此超临界流体是用于掩膜层剥除制程及清洁制程，以去除掩膜图案层104及蚀刻后续产生的副产品，例如形成于掩膜图案层104侧壁的聚合物104a或是形成于介电层102表面及镶嵌开口108内表面的化学残留物(未绘示)。在本实施例中，化学清除剂包括HF、NMP(N-methyl-2-pyrrolidone)、CH3COOH、MeOH、BLO(butrolactone)、H2SO4、HNO3、H3PO4、或TFAA(trifluoroacetic acid)。
接下来，请参照图1c，在介电层102上方临场(in-situ)形成一导电层112，例如铜、铝、或其它现有的内联机材料，并填入镶嵌开口108。在本实施例中，为了避免清洁过的基底100暴露于大气中时，形成氧化物或任何化学残留物或与介电层102发生不必要的化学反应，是藉由超临界流体技术来临场形成导电层112，且其可轻易地与先前的清洁制程整合。举例而言，在一反应室进行一清洁制程之后，接着在不与外界接触的情形之下，利用一有机金属错合物作为沉积前驱物及利用超临界二氧化碳作为反应媒介来进行沉积制程。亦即，清洁制程与沉积制程可依序于一制程设备的一反应室中进行或于一具有多数个反应室的制程设备的不同反应室中进行。在本实施例中，举例而言，用于内联机制作的有机金属错合物包括Cu(hfac)(2-butyne)，其中hfac为hexafluoroacethyl acetonate的缩写，dibm为diisobutyrylmethanato的缩写。另外，典型地，一扩散阻障层(未绘示)，例如氮化钛、氮化钽、氮化钨、或其它类似的材料，于沉积导电层112之前，形成于介电层102表面及镶嵌开口108内表面。再者，扩散阻障层可藉由上述超临界流体技术及利用其它适当的有基金属错合物作为沉积前驱物而临场形成。
最后，请参照图1d，藉由回蚀刻制程或是研磨制程，例如化学机械研磨(CMP)，将介电层102上方多余的导电层112去除，以在镶嵌开口108内留下一部分的导电层112a作为内联机并完成内联机结构的制作。
图1d亦绘示出本发明实施例的半导体装置200的剖面示意图。半导体装置200包括一基底100、一介电层102、及一内联机结构112a。介电层102，例如一低介电常数材料层，是设置于基底100上方，且其具有至少一镶嵌开口108位于被一超临界流体，例如超临界二氧化碳，所清洁过的一区域中，其中超临界流体内溶解有作为清除剂的HF、NMP、CH3COOH、MeOH、BLO、H2SO4、HNO3、H3PO4、或TFAA。此处，镶嵌开口108可为一沟槽或接触窗开口。内联机结构112a是设置于镶嵌开口108中，其是于清洁制程之后，利用超临界流体作为反应媒介且利用有机金属错合物，例如Cu(hfac)(2-butyne)，作为沉积前驱物以临场形成。再者，清洁制程与内联机结构112a的制作是于一制程设备的一反应室中进行或于一具有多数个反应室的制程设备的不同反应室中进行。
根据本发明的方法，金属化制程中的清洁步骤与后续沉积步骤是于不与外界接触的情形下依序进行。亦即，可避免清洁过的基底暴露于大气之中，藉以防止氧化物或是化学残留物的形成以及不必要的反应或是水气吸收的发生。因此，半导体装置的可靠度及产生可因排除制程等候时间的问题而增加。再者，相较于相关技术，由于采用超临界流体技术来进行蚀刻后续清洁制程，所以可有效地去除蚀刻后续产生的副产品而不损害到低介电常数材料，藉以增加组件的品质。再者，可藉由超临界流体作为清洁剂并以其作为沉积制程的反应媒介而将蚀刻后续清洁制程轻易地整合于沉积制程，进而简化制程、减少制程设备的所需空间、及降低制造成本。
虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明，任何熟习此技艺者，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当视所附的权利要求范围所界定者为准。

Claims (6)

1.一种内联机结构的形成方法，包括下列步骤：
提供一基底，其上覆盖有一介电层，该介电层具有由位于其上方的一掩膜图案层所定义出的至少一开口；
藉由一超临界流体实施一清洁制程，以去除该掩膜图案层以及形成于该介电层表面及该开口内表面的蚀刻副产品；以及
临场填入一导电层于该开口内，以完成该内联机结构，该导电层是利用一有机金属错合物作为沉积前驱物并利用超临界二氧化碳作为反应媒介而形成的。
2.根据权利要求1所述的内联机结构的形成方法，其中该超临界流体更包括一化学清除剂溶解其中，其包括HF、NMP、CH3COOH、MeOH、BLO、H2SO4、HNO3、H3PO4、或TFAA。
3.根据权利要求1所述的内联机结构的形成方法，其中该有机金属错合物包括Cu(hfac)(2-butyne)。
4.一种铜制程整合方法，包括下列步骤：
提供一基底，其上覆盖有一介电层，该介电层具有由位于其上方的一掩膜图案层所定义出的一镶嵌开口；
藉由一超临界流体实施一清洁制程，以去除该掩膜图案层以及形成于该介电层表面及该镶嵌开口内表面的蚀刻副产品；以及
利用该超临界流体作为一反应媒介，以临场填入一铜层于该镶嵌开口内。
5.根据权利要求4所述的铜制程整合方法，其中该超临界流体更包括一化学清除剂溶解其中，其包括HF、NMP、CH3COOH、MeOH、BLO、H2SO4、HNO3、H3PO4、或TFAA。
6.根据权利要求4所述的铜制程整合方法，其中该铜层是利用Cu(hfac)(2-butyne)作为沉积前驱物。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6464779B1 (en) * 2001-01-19 2002-10-15 Novellus Systems, Inc. Copper atomic layer chemical vapor desposition
CN1425194A (zh) * 2000-04-25 2003-06-18 东京毅力科创株式会社 沉积金属薄膜的方法和包括超临界干燥/清洁组件的金属沉积组合工具
WO2003087936A1 (en) * 2002-04-12 2003-10-23 Supercritical Systems Inc. Method of treatment of porous dielectric films to reduce damage during cleaning

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US6184132B1 (en) * 1999-08-03 2001-02-06 International Business Machines Corporation Integrated cobalt silicide process for semiconductor devices
US20050227187A1 (en) * 2002-03-04 2005-10-13 Supercritical Systems Inc. Ionic fluid in supercritical fluid for semiconductor processing

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1425194A (zh) * 2000-04-25 2003-06-18 东京毅力科创株式会社 沉积金属薄膜的方法和包括超临界干燥/清洁组件的金属沉积组合工具
US6464779B1 (en) * 2001-01-19 2002-10-15 Novellus Systems, Inc. Copper atomic layer chemical vapor desposition
WO2003087936A1 (en) * 2002-04-12 2003-10-23 Supercritical Systems Inc. Method of treatment of porous dielectric films to reduce damage during cleaning

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
超临界流体技术研究进展 肖建平，范崇政，化学进展，第13卷第2期 2001 *

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