TWI285939B - Semiconductor device and method for forming interconnect structure and integrated copper process - Google Patents
Semiconductor device and method for forming interconnect structure and integrated copper process Download PDFInfo
- Publication number
- TWI285939B TWI285939B TW093121286A TW93121286A TWI285939B TW I285939 B TWI285939 B TW I285939B TW 093121286 A TW093121286 A TW 093121286A TW 93121286 A TW93121286 A TW 93121286A TW I285939 B TWI285939 B TW I285939B
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- Prior art keywords
- layer
- opening
- semiconductor device
- supercritical
- forming
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 122
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000010949 copper Substances 0.000 title claims description 29
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims description 15
- 229910052802 copper Inorganic materials 0.000 title claims description 15
- 238000004140 cleaning Methods 0.000 claims abstract description 37
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- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 9
- 239000001569 carbon dioxide Substances 0.000 claims description 8
- 229910002092 carbon dioxide Inorganic materials 0.000 claims description 8
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- XNMQEEKYCVKGBD-UHFFFAOYSA-N 2-butyne Chemical compound CC#CC XNMQEEKYCVKGBD-UHFFFAOYSA-N 0.000 claims description 6
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- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 229910052797 bismuth Inorganic materials 0.000 description 2
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- 150000004696 coordination complex Chemical class 0.000 description 1
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- 229910052905 tridymite Inorganic materials 0.000 description 1
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- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- G—PHYSICS
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- G—PHYSICS
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- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
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- G03F7/422—Stripping or agents therefor using liquids only
- G03F7/425—Stripping or agents therefor using liquids only containing mineral alkaline compounds; containing organic basic compounds, e.g. quaternary ammonium compounds; containing heterocyclic basic compounds containing nitrogen
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
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- G03F7/42—Stripping or agents therefor
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- G03F7/426—Stripping or agents therefor using liquids only containing organic halogen compounds; containing organic sulfonic acids or salts thereof; containing sulfoxides
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Cleaning Or Drying Semiconductors (AREA)
Description
1285939 九、發明說明: 【發明所屬之技術領域】 本發明係有關於一種半導體製程,特別是有關於一種在一具有單一個 或多數個反應室之半導體製程設備中整合餘刻後續清潔製程(p0St-etching cleaning process)與沉積製程。 【先前技術】 在積體電路或是微電子裝置的製造中,多層導線結構係使用於積體電 路中的單一或多個裝置的内連線(interconnect)區。傳統上係採用雙鑲嵌 (dualdamascene)製程形成上述内連線結構。 雙鑲嵌製程一開始係先於一矽晶圓上沉積一介電層,例如一低介電常 數(k)材料層’以作為一金屬層間介電dielectric, IMD.)層。 隨後實施郷及侧製㈣在IMD層巾形成-雜錢觸冑開σ或是由該 等開口所成之雙職開口。最後,在開口中沉積一金屬層,例如銅層或銘 層,以完成内連線結構之製作。 傳統上,藉由_製程在IMD層中形成開口之後,反應室巾的晶圓會 實施-«餘財除光料幕及侧後生之副產品(pQst_etchJg by—s) ’例《合物歧其魏賴㈣。讀,將晶反應室移 出以等候後續進行沉積製程献金屬化製程。在等候_ (稱做製程等待 聘間(q麵time,Q-time)),晶圓係暴露於大氣中,導致原生(native)氧 化物形成抑表面或是不必要的氧化物形成於晶_下層金屬層表面而 =利於後翻製程。為了去除上化物,聽進行_製程之前,額外 實施-電漿赫餘,但卻因絲損及低介電f數材簡之表面者, 低介電常數材料輕等.候進行沉積製程時,容易與 副 相互作用或是吸收到水氣而導致介電特性退化。 生的剜產 另外’光阻罩幕之去除通常制電漿去除L魏會損害低介 1285939 電常數材料f,同樣會導致介電特性退化。再者,《去除法並無法完全 去除光阻罩幕’目騎合物會形成於光阻罩幕之讎,於後續 之進行〇 . 、王 美國f利弟6,184,132號係揭示-種半導體裝置中魏狀整合製程, 其利用=(m_Sltu)電漿清潔製觀麵行航積之前去_成於秒基底 上的原生氧化物。然而,如以上所述,於清潔期間,電漿容易損害基底表 面另外美國專利第6,395,642號係揭示一種改良的銅製程整合方法,其 係整合進行銅電艘之前的銅晶種層製作與電漿清潔製程。藉由此方法,銅 =物可有效地除去,以增加_連線的品質。然而,於去除光阻罩幕盘 金屬沉積步驟之間仍存在製程等候時間(Q-time)。 ” 胃因此,有必要尋求新的方法來解決因上述製程等候時間所引發的問 通,以維持介電層的介電特性。 【發明内容】 本㈣之目的在於提供_賴域合齡_清潔製程與 此積衣絲避免钟低介電f數(1GW k)材料層 基 沉積前暴露於大氣中之方法,藉以克 .驗钱 的問題並增加魏。 4所引發 2之另-目的秘提供—種彻超臨界流體(〒獅臓 技術來進雜職續清«餘_的_餘之方法,辑代傳統電货 ,術,進而有效地嫌__生之副產品(_痛啤 並防止低介電常數材料層之損害。 甘本發明之又另-目的在於提供—種具有_内連、躲構之半導體裝置, 積製程之反應媒介。,机體作為清潔製程之清潔劑並作為沉 根據上叙目的,本發_—_連、_之形射法。首先,提 1285939 供一基底,其上覆蓋有一介電層,該介電層具有由位於其上方的一罩幕圖 案層所定義出的至少一開口。之後,藉由一超臨界流體實施一清潔製程, 以去除該罩幕圖案層以及形成於介電層表面及開口内表面的蝕刻副產品。 最後,藉由超臨界流體作為反應媒介以臨場填入一導電層於開口内,而完 成内連線結構。此處,清潔製程之實施及臨場填充開口係於一製程設備的 一製程反應室或是具有多個反應室之製程設備的不同製程反應室中進行。 上述η電層可為一低介電常數材料層且罩幕圖案層可為一光阻圖案 層。 再者,使用於清潔製程之超臨界流體可為超臨界二氧化碳,且其更包 括一化學清除劑溶解其申,其包括HF、ΝΜΡ、CHsCOOH、MeOH、BLO、 H2S04、HN〇3、H3P〇4、或 TFAA。 〃再者,導電層係利用一有機金屬錯合物作為沉積前驅物並利用超臨界 二氧化碳作為反應媒介而形成之,其中有機金屬錯合物包括
Cu(hfac)(2-bu㈣)、Cu(hfac)2、或 Cu(dibm^^^ 根據上述之另一目的,本發明提供一種銅製程整合方法。首先,提供· 一基底,其上覆蓋有一介電層,介電層具有由位於其上方的一罩幕圖案層 所定義出的一鑲嵌開口。接著,藉.由一超臨界流體實施一清潔製程,以去 除罩幕圖案層以及形成於介電層表面及鑲嵌開口内表面的蝕刻副產品。最 後,利用超臨界流體作為一反應媒介,以臨場填入一銅層於該鑲嵌開口内。 此處’ ’胃 >糸製程之貫施及臨場填充開口係於一製程設備的一製程反應室咬 是具有多個反應室之製程設備的不同製程反應室中進行。 上述介電層可為一低介電常數材料層且罩幕圖案層可為一光阻圖案 層。 再者,使用於清潔製程之超臨界流體可為超臨界二氧化碳,且其更包 括一化學清除劑溶解其中,其包括HP、、CH3C〇〇h、、%〇、 H2S04、ΗΝ〇3、Η3Ρ〇4、或 TFAA。 1285939 再者,銅層係利用Cu(麻χ2七雖e)、Cu(hfac)2、或⑽㈣作為沉 積前驅物。 又根據上狀另-目的’本發明提供—種轉雜置。辭導體裝置 包括-基底…低介電常數材料層、及—内連線結構。低介電常數材料層 係設置於基底上方’其具有至少—鑲嵌開口錄被―超臨界流體所清潔過 的-區域中。内連線結構係設置於鑲嵌開口内q其係於實施清潔製程之 j,利簡臨界流體作為—反麟介且__錢金屬錯合物作為一沉積 前驅物而臨場形成之。此處,對鑲細σ所實施之清程及内連線結構 之裝作係於-製程設備的-製程反應室或是具有多個反應室之製程設備的 不同製程反應室中進行。 再者,使用於清潔製程之超臨界流體可為超臨界二氧化石炭,且其更包 括一化學清除劑溶解其中,其包括HF、_>、CH3C〇〇H、Me〇H、bl〇、 H2S〇4、HN〇3、h3P〇4、或丁FAA。 再者,有齡屬錯合物包括 Cu(hfae)(2_butyne)、Cu_c〇2、& c^dibm:)。 為讓本發明之上述目的、特徵和優點能更明㈣懂,下域舉較佳實 施例,並配合所附圖式,作詳細說明如下: 【實施方式】 第la到Id係繪示出根據本發明實施例之雙鑲嵌製程中形成内連線結 構之方法。首先,凊參知、第1&圖,提供一基底100,例如一石夕基底或其他 半V體基底。此基底1〇〇可包含不同的元件,例如電晶體、電阻器、及其 他習知的半導體元件。此基底動亦可包含其他絕緣層或金屬内連線層。 此處’為了簡化圖式,僅繪示出一平整的基底。 接者,在基底100上方形成一介電層1〇2。再本實施例中,介電層1〇2 係作為-内層層間介電(ILD)層或是金屬層間介電(IMD)層。舉例而言, ;丨電層102可為二氧化石夕、磷矽玻璃(pSG)、硼磷矽玻璃(BpSG)、或是 1285939 其他如摻雜氟之矽玻璃(FSG)之低介電常數(k)材料層。再者,介電層 102可藉由習知沉積技術形成之,例如電漿輔助化學氣相沉積(pECVD)、 低壓化學氣相沉積(LPCVD)、常壓化學氣相沉積(ApcVD)、高密度電漿 化學氣相沉積(HDPCVD)、或是其他適當的CVD。另外,在沉積介電層 1〇2之前,一蝕刻終止層(未繪示),例如一氮化矽層,可藉由LpcVD並 利用SiC^H2及NH3作為反應源,選擇性地沉積於基底1〇〇上。再者,一抗 反射層(未繪示),可選擇性地沉積於介電層1〇2上方。此處,抗反射層可 為氮氧化矽(SiON),其可藉由CVD並利用SiH4、02、及N2作為製程氣 體形成之。 之後,在介電層102上方塗覆一罩幕層(未繪示),例如光阻,接著實 靶微影製程以形成一罩幕圖案層104,其具有至少一開口 106以露出部分的 介電層102,作為定義鑲嵌結構之用。 接下來,請參照第lb圖,利用罩幕圖案層104作為一蝕刻罩幕,以進 行傳統飯刻製程,例如反應離子蝕刻(RTE),蝕刻介電層102以在其中形 成鑲敢開口 108。鑲嵌開口 108可為一溝槽、接觸窗開口、或其他開口。 接著,進行本發明之一連串的關鍵步驟。首先藉由超臨界流體,例如 超臨界二氧化碳(C〇2),實施一清潔製程110以去除罩幕圖案層1〇4以及 形成於介電層1〇2表面及鑲嵌開口 108内表面的蝕刻後續產生的副產品。 亦即,上述清潔製程110包含了罩幕層剝除製程以及傳統的清潔製程。 氣體處於超臨界態係稱做超臨界流體。亦即,當環境的壓力及溫度達 到臨界態時,氣體就會進入超臨界態。舉例而言,C〇2的臨界溫度約在31 c ’且c〇2的臨界壓力約在726atm。在本實施例中,清潔製程11〇的製程 /J^度在31到400 C的範圍且製程壓力在72到400atm的範圍^典型地,超 臨界流體的密度與液相大體相同時。其擴散性質與黏性相似於氣相。因此, 可將化學清除劑溶解於超臨界流體之中。此超臨界流體係用於罩幕層剝除 ,程及α办‘程’以去除罩奉圖案層1〇4及姓刻後續產生的副產品,例如 1285939 形成於罩幕圖案層1〇4側壁的聚合物HHa或是形成於介電層搬表面及镶 嵌開口 108内表面的化學殘留物(未繪示)。在本實施例中,化學清除劑包 括 HF、NMP ( N-methyl冬pyrrolidone )、CH3C〇〇h、Me〇H、BL〇 (butrolactone) ^ H2S04 > HN03 ^ H3P04 ^TFAA (trifluoroacetic acid) 〇 接下來,请參照第lc圖,在介電層102上方臨場形成一導 電層112,例如銅、鋁、或其他習知的内連線材料,並填入鐵嵌開口 1〇8。 在本實施例中,為了避免清潔過的基底100暴露於大氣中時,形成氧化物 或任何化學殘留物或與介電層1〇2發生不必要的化學反應,係藉由超臨界 流體技術來臨場形祕電層112,且其可輕祕與絲的清潔製程整合。舉 例而g,在_反應室進行-清雜程之後,接著在不與外界細的情形之 下,利用一有機金屬錯合物作為沉積前驅物及利用超臨界二氧化碳作為反 應媒介來進行沉積餘。亦即,清雜減沉積餘可依序於—製程設備 的-反應室中進行或於-具有多數個反應室之製程設備的不同反應室中進 行。在本實施射,舉_言,用於内連線製作財機金屬錯合物包括 eu(hf__butyne)、Cu_)2、或 Cu(di㈣ acetonate 之縮舄 ’ dibm 為 diisobutyrylmethanato <縮寫。另外,典型地,一 擴散阻障層(树示),例如氮化鈦、氮她、氮化鎢、或其他類似的材料, 於沉積導電層112之前,形成於介電層搬表面及鑲散開口娜内表面。 再者’擴散轉層可躺上述超臨界流體技術及彻其他適當的有基金屬 錯合物作為沉積前驅物而臨場形成之。 最後,請參照第1(1圖,藉由回飯刻製程或是研 學 研磨_),將侧上方多翻糊m去除,以錢嵌;千口= 内留厂部分的導電層112a作為内連線並完成内連線結構之製作。 第Id圖亦繪示出本發明實施例之半導體裝置2〇〇之剖面示意圖。半導 體裝置200包括-基底1〇〇、_介電層搬、及一内連線結構此。介電層 1〇2 ’例如一低介電常數材料層,係設置於基底謂上方,且其具有至少一 1285939 鑲嵌開口⑽位於被-超轉流體,例如超臨界二氧化碳,所清潔過的一 區域中’其中超臨界机肢内溶解有作為清除劑的
MeOH、BLO、H2S04、_〇3、聊4、或 TFAA。此處,驗開 口⑽可 為-溝槽或接觸Μ 口。俩線結構112_設置於職開口 1Ό8中,其係 於清泳餘之後’糊超臨界趙作為反應媒介且利财機金屬錯合物, _ Cu_>(>butyne)' Cu(hfac)2、或Cu(dibm),作為沉積前驅物以臨場 形成之。再者,清潔製程與内連線結構心之製作係於一製程設備的一反 應室中進减於-具有錄個反魅之製程設備的不同反應室中進行。 根據本發明之方法,金屬化製程中的清潔步驟與後續沉積步驟係於不 與外界接觸的情形下依序進行。亦即,可聽清潔·基絲露於大氣之 中’藉以防止氧化物或是化學殘留物之形成以及不必要的反應或是水氣吸 收之發生。目此,轉體裝置的可靠度及產生可因麟製程等候時間的問 題而增加。再者,相較於相關技術,由於採用超臨界流體技術來進行蝕刻 後績清潔製程,所以可有效地去除侧後續產生的副產品而不損害到低介 電常數材料,藉以增加元件的品質。再者,可藉由超臨界流體作為清潔劑 並以其作為沉積製程之反應媒介而將蝕刻後續清潔製程輕易地整合於沉積 製程’進而簡化製程、減少製程設備之所需空間、及降低製造成本。 雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任 何力習此項技藝者,在不脫離本發明之精神和範圍内,當可作更動與潤飾, 因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 11 1285939 【圖式簡單說明】 第la到Id圖係繪示出根據本發明實施例之雙鑲嵌製程中内連線結構 形成方法之剖面示意圖。 102〜介電層; 104a〜聚合物層; 110〜清潔製程; 112a〜内連線結構;
【主要元件符號說明】 100〜基底; 104〜罩幕圖案層; 108〜鑲嵌開口; 112〜導電層; 200〜半導體裝置。 12
Claims (1)
1285939 十、申請專利範圍: 1·-種内連線結構之形成方法,包括下列轉: 提供-基底’其上覆蓋有—介電層,該介電層具有由位於其上方的一 罩幕圖案層所定義出的至少一開口; ^由-超臨界频魏-清雜程,财除鮮幕_如及形成於 該"電層表©及該開口内表面的侧副產品;以及 臨場填入-導電層於該開叫,以完成該内連線結構。 / 2.”請專利範圍f丨項所述之内連線結構之形成方法,其中該介電層 係一低介電常數材料層。 曰 3.如申請專利範圍第丨項所述之内連線結構之形成方法,其中該開口包 括一溝槽或一接觸窗開口。 4·如申请專她®第1項所述之魄線結構之形成方法,其巾鮮幕圖 案層係一光阻圖案層。 5·如申請專繼圍第1項所叙__構之形成方法,其巾該超臨界 流體係超臨界二氧化碳。 士 6·如申請專利範圍第i項所述之内連線結構之形成方法,其中該超臨界 机體更包括化學清劑溶解其中,其包括册、應^、阳⑺册、Me〇H、 BLO、H2S04、HN〇3、h3P〇4、或 TFAA。 / 7·如申請專利範圍第i項所述之内連線結構之形成方法,其中該導電層 · 係利用-有機金屬錯合物作為哺前麟並侧超臨界二氧化徘為反應 媒介而形成之。 8·如申請專利範圍第7項所述之内連線結構之形成方法,其中該有機金 屬錯合物包括 Cu(hfac)(2-butyne:)、C_ac〇2、或(:u_m)。 ,9·如申清專利範圍第1項所述之内連線結構之形成方法,其中實施該清 潔製程及臨場填充祕 1σ之步驟係於-製程設備的_反應室中進行。 ι〇·如申請專利範圍第1項所述之内連線結構之形成方法,其中實施該 13 1285939 清潔製程及臨場填充該開σ之步驟係於— 不同反應室中進行。 ^數個反應室之製程設備的 u·一種銅製程整合方法,包括下列步驟·· 提供一基底,其上覆蓋有一介電層, 罩幕圖案層所定義出的一鑲嵌開口; ^電層具有由位於其上方的- 藉由-超臨界流體實施—清潔製程, 該介電層表峨侧口咖祕_=^陶卿成於 ^利用該__為—細介 12.如申請專利範圍第u項所述之銅 低介電常數材料層。 ㈣5方法’其中該介電層係- 13·如申請專利範圍第11項所述之鋼製β 括一溝槽或-接觸窗開口。 旬“整合方法,其中該鑲嵌開口包 係概龄U _述之崎雜合找,其中料幕圖案層 係超項—整合方法,其~趙 16.如申料利細帛u摘狀轉雜 βΓ;:γγ w t—-' - ^ cH;c〇〇:":r BLO、H2S04、ΗΝ03、h3P〇4、或 TFAA。 擊糊第11項所述之鋼製程整合方法,其中該銅層係利用 CuChf^-bntyne) . Cu(hfac)2 ^ Cu(diblnKt4^#^^^ 〇 程及圍第11項所述之鋼製程整合方法,其中實施該清潔製 私及㈣軸_層之步驟係於—製程設制_反應室中進行 範圍第^項所述之銅製程整合方法,其中實施該清潔製 私及岭軸該銅層之步義於—具有多數個反魅之製程設備的不同反 14 1285939 應室中進行。 2〇·—種半導體裝置,包括: 一基底; 一低介電常數材料層,設置於該基底上方,其具有至少一鑲嵌開口 於被一超臨界流體所清潔過的一區域中;以及 一内連線結構,設置於該鑲嵌開口内,且其係於實施清潔製程之後 利用該超臨界流體作為一反應媒介且利用一有機金屬錯合物作為一沉 驅物而臨場形成之。 21·如申請專利範圍第20項所述之半導體裝置,其中該鑲嵌開口包括一 溝槽或一接觸窗開口。 22.如申請專利範圍第20項所述之半導體裝置,其中該超臨界流體係超 fer界二氧化碳。 “ 23·如申請專利範圍第2〇項所述之半導體裝置,其中用於該清潔製程之 該超臨界流體更包括一化學清除劑溶解其中,其包括HP、=、 CH3COOH、MeOH、BLO、H2S04、HN〇3、H3P04、或 TFAA。 24·如申請專利範圍第2〇項所述之半導體裝置,其中該有機金屬錯合物 包括 Cu(hfac)(2_butyne)、Cu(hfac)2、或 Cu(dibm)。 =·如t請專利顧第%猶述之半導體裝置,射預清親驗開口 及臨場形成該内連線結構係於一製程設備的一反應室中進行。 ^6·如申清專利範圍第20項所述之半導體裝置,其中預清潔該鑲嵌開口 及臨場形成_連騎構餘—具有錄個反應室之製程設備的不同反應 室中進行。 15
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