CN1395288A - 在去光阻制程中避免低介电常数介电层劣化的方法 - Google Patents
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Abstract
一种在去光阻制程中避免低介电常数介电层劣化的方法,是先于半导体晶片的基底表面形成低介电常数介电层,接着对该低介电常数介电层进行一表面处理,于该低介电常数介电层表面形成钝化层;随后于半导体晶片表面上形成图案化的光阻层,并利用该光阻层作为硬屏蔽来对低介电常数介电层进行一蚀刻制程;最后再去除图案化的光阻层。其中钝化层是用来避免低该介电常数介电层于该去光阻制程中发生介电特性劣化的现象。利用含氮等离子的前处理,于低介电常数介电层表面形成钝化层,进而抑制该低介电常数介电层于去光阻制程中受损而形成Si-OH键,有效避免因Si-OH键吸附水气导致低介电常数介电层发生介电特性劣化的现象。
Description
技术领域
本发明是提供一种在去光阻制程中避免低介电常数介电层劣化的方法,即是一种避免低介电常数介电层于去光阻制程中发生介电特性劣化的方法。
背景技术
随着半导体元件的尺寸不断缩小,以及积体电路密度不断的提高,伴随而来的金属导线间所产生的RC时间延迟(RC time delay)业已严重地影响到积体电路的运作效能,大大降低了积体电路的工作速度,尤其当制程线宽(line width)降到0.25微米,甚至0.13微米以下的半导体制程时,RC时间延迟所造成的影响将更为明显。
由于在金属内连线间所产生的RC时间延迟是由金属导线的电阻值(R)与金属导线间的介电层的寄生电容(C)的相乘积,故减少RC时间延迟的方法可利用电阻值较低的金属做为金属导线,或者是降低金属导线间介电层的寄生电容。在降低电阻方面,使用纯铜作为导线材料的铜连结线技术(copperinterconnect technology)以取代传统的铝铜合金[Al∶Cu(0.5%)]为主要材料的多重金属化制程(multilevel metallization process)已成为势在必行的趋势。因为铜本身具有较低的电阻率(1.67μΩ-cm),加上可承载较高的电流密度而不致产生有铝铜合金的电致迁移(electro migration)之虞,因此可以减少金属导线间的寄生电容,以及金属导线的连结层数。其主要缺陷在于:
但是单单以铜连结线技术仍然无法将金属导线间所产生的RC时间延迟大幅降减低,而且铜连结线技术亦有一些制程上的问题尚待解决,所以利用降低金属导线间介电层的寄生电容来减少RC时间延迟的方法便日益重要。
此外,由于介电层的寄生电容与介电层的介电常数(dielectric constant)相关,因此介电层的介电常数越低,形成于介电层中的寄生电容也就相对的越低。而传统的二氧化硅(介电常数为3.9)已渐渐无法满足目前0.13微米以下的半导体制程的需求,是以一些新的低介电常数材料,例如聚酰亚胺(polyimide,PI)、FPI、FLARETM、PAE-2、PAE-3、或LOSP等已被陆续提出。其主要缺陷在于:
然而,这些低介电常数材料虽具有较低的介电常数值(介于2.6-3.2之间),但是这些一般主成分为碳氢氧的低介电材料,无论在蚀刻及与其它材料的附着力,或是其本身的各项性质都与传统的二氧化硅有明显差异,而且其大部份有附着性不佳以及热稳定性不足等缺点,因此目前尚无法妥善地整合于一般IC常用的制程。
也因为如此,一些以二氧化硅为基础然后于材料内再掺入一些碳氢等元素的低介电常数介电层,例如HSQ(hydrogen silsesquioxane)(K=2.8)、MSQ(methyl silsesquioxane)(K=2.7)、HOSP(K=2.5)、H-PSSQ(hydriopolysilsesquioxane)、M-PSSQ(methyl polysilsesquioxane)、P-PSSQ(phenyl polysilsesquioxane)或多孔性凝胶(porous sol-gel)(K<2)等材料,便由于其性质与传统二氧化硅相去不远,因此对目前传统的半导体制程有着较高的整合能力,而为日后所看好。其主要缺陷在于:
但是在对这些以二氧化硅为基本结构的低介电常数材料(HSQ、MSQ、HOSP、porous sol-gel等)构成的介电层进行图案转移时,不论在蚀刻介电层或进行去光阻制程中均会对介电层造成伤害。因为去光阻制程通常是同时使用干式氧等离子灰化(ashing)制程与湿式去光阻液来去除光阻,故使得介电层表面的键结容易被氧等离子打断,而与氧离子以及硷性的去光阻液反应,使受损介电层表面形成Si-OH键而吸附水气。由于水的高介电常数值(K=78),介电层吸附水气后将导致介电层的介电常数上升,丧失原本低介电常数特性。此外,吸附的水气亦会使介电层的漏电流上升,使介电层绝缘性变差,甚至会有毒害介层洞(poison via)的情形产生,严重影响产品的可靠度。
发明内容
本发明的主要目的在于提供一种在去光阻制程中避免低介电常数介电层劣化的方法,通过于半导体的基底表面形成低介电常数(low k)介电层;接着对该低介电常数介电层进行表面处理,于该低介电常数介电层表面形成钝化层;随后于该半导体晶片表面上形成图案化的光阻层,并利用该光阻层作为硬屏蔽(hard mask)来对该低介电常数介电层进行蚀刻制程;最后去除低介电常数介电层表面的光阻层,克服现有技术的弊端,达到避免低介电常数介电层劣化的目的。
本发明的目的是这样实现的:一种在去光阻制程中避免低介电常数介电层劣化的方法,其特征是:它包括如下步骤:
(1)低介电常数介电层是形成于基底表面,对该低介电常数介电层进行表面处理,于该低介电常数介电层表面形成钝化层;
(2)于该基底上形成图案化的光阻层;
(3)利用该光阻层作为硬屏蔽,对该低介电常数介电层进行蚀刻制程;
(4)进行去光阻制程。
该基底选自硅晶片。该低介电常数介电层选自hydrogensilsesquioxane、methyl silsesquioxane、hydrio polysilsesquioxane、methyl polysilsesquioxane、phenyl polysilsesquioxane、HOSP或多孔性凝胶。该低介电常数介电层是选自化学气相沉积法或旋涂方式形成于该基底上。该表面处理为等离子处理。该等离子处理是进行于含氮的气氛环境下,于该低介电常数介电层表面形成该钝化层。该含氮的气氛环境选自包含有氧化亚氮、一氧化氮或氨气。该等离子处理的无线电波频率为100-300瓦,该等离子处理的真空度是保持在10-3-10-6Torr之间,且该等离子处理的时间小于20分钟,该基底的温度是低于250℃。该去光阻制程是选自湿式去光阻制程,该钝化层是避免该低介电常数介电层于该湿式去光阻制程中形成Si-OH键,而吸附水气,导致该低介电常数介电层的介电常数及漏电流上升而劣化该低介电常数介电层的介电特性。
本发明还提供另一种在去光阻制程中避免低介电常数介电层劣化的方法,其特征是:它包括如下步骤:
(1)低介电常数介电层是形成于基底表面,对该低介电常数介电层进行表面处理,于该低介电常数介电层表面形成钝化层;
(2)于该基底上形成图案化的光阻层;
(3)利用该光阻层作为硬屏蔽,对该低介电常数介电层进行蚀刻制程;
(4)进行湿式去光阻制程;其中该钝化层是用来抑制该低介电常数介电层于该湿式去光阻制程中形成Si-OH键而吸附水气,进而避免该低介电常数介电层发生介电特性劣化的现象。
该基底是选自硅晶片。该低介电常数介电层选自hydrogensilsesquioxane、methyl silsesquioxane、hydrio polysilsesquioxane、methyl polysilsesquioxane、phenyl polysilsesquioxane、HOSP或多孔性凝胶。该低介电常数介电层是选自化学气相沉积法或旋涂方式形成于该基底上。该表面处理选自等离子处理。该等离子处理是进行于含氮的气氛环境下,于该低介电常数介电层表面形成该钝化层。该含氮的气氛环境选自包含有氧化亚氮、一氧化氮或氨气。该等离子处理的无线电波频率为100-300瓦,该等离子处理的真空度是保持在10-3-10-6Torr之间,该等离子处理的时间小于20分钟,该基底的温度是低于250℃。
本发明的创造点是利用含氮等离子的前处理,以于低介电常数介电层表面形成钝化层,进而抑制该低介电常数(low k)介电层于去光阻制程中受损而形成Si-OH键,故能有效避免因Si-OH键吸附水气导致低介电常数(low k)介电层发生介电特性劣化的现象。
下面结合较佳实施例和附图进一步说明。
附图说明
图1-图5为本发明在低介电常数介电层上进行蚀刻制程的方法示意图。
图6为HSQ介电层在不同氨等离子处理时间下所得到的红外线光谱图。
图7为HSQ介电层中使用不同氨等离子处理时间对介电常数的影响示意图。
图8为HSQ介电层中在不同氨等离子处理时间下电场对元件漏电流的关系示意图。
具体实施方式
参阅图1-图5所示,本发明于低介电常数介电层上进行蚀刻制程的方法包括如下步骤。
如图1所示,半导体晶片10上包含有一硅基底12,一利用化学气相沉积法(chemical vapor deposition,CVD)或旋涂方式(spin-on)而形成于硅基底12表面的低介电常数(low k)介电层14。其中,低介电常数介电层14是由HSQ(hydrogen silsesquioxane)、MSQ(methyl silsesquioxane)、H-PSSQ(hydriopolysilsesquioxane)、M-PSSQ(methyl polysilsesquioxane)、P-PSSQ(phenyl polysilsesquioxane)、HOSP等以二氧化硅为基本结构的介电材料所构成。
接着如图2所示,对半导体晶片10上的低介电常数介电层14进行一表面处理,亦即利用无线电频率(radio frequency,RF)为100-300瓦,使用氧化亚氮(nitrous oxide,N2O)、一氧化氮(nitric oxide,NO)或氨气(ammonia,NH3)等含氮等离子,在硅基底12温度为150-250℃,且反应室压力为10-3torr的制程条件下,对低介电常数介电层14进行5-15分钟的含氮等离子处理16,以使低介电常数介电层14表面形成一钝化层18。其中,通入含氮等离子前反应室的压力是保持在10-6Torr。
由于低介电常数介电层14含有硅和氧原子,因此低介电常数介电层14表面会与该含氮等离子进行反应,形成氮化硅(SiN)或氮氧化硅(SiON)的钝化层18,以有效防止低介电常数介电层14吸附水气,而且形成于低介电常数介电层14表面的钝化层18更可用来作为一抑制铜扩散的阻障层。此外,由于钝化层18仅形成于低介电常数介电层14表面,且其厚度很薄,故不会影响低介电常数介电层14的介电常数。
随后,如图3-图4所示,于半导体晶片10表面涂布一光阻层20,并利用一微影制程以于光阻层20中定义一蚀刻图案。然后利用图案化的光阻层20作为硬屏蔽(hard mask),对低介电常数介电层14与钝化层18进行一蚀刻制程,以转移该蚀刻图案到低介电常数介电层14之上,如图4所示。
如图5所示,最后,进行一去光阻制程,先利用一氧等离子灰化(ashing)制程对光阻层20进行反应性蚀刻,使氧等离子与光阻层20中的碳和氢元素完全反应,形成气态的二氧化碳与水蒸气而剥除光阻,接着再将半导体晶片10置放于一湿式去光阻液(wet stripper)中,如羟胺(NH2OH)或乙醇胺(HOC2H4NH2)等硷性溶液中,以去除残留在钝化层18表面的光阻层20,如图5所示,以完成整个低介电常数介电层14的蚀刻制程。其中,由于低介电常数(low k)介电层14表面形成有钝化层18,因此低介电常数介电层14便不易于该去光阻制程中受损而形成大量吸附水气的Si-OH键,进而导致该低介电常数(low k)介电层14的介电常数以及漏电流上升,故有效避免该低介电常数(low k)介电层发生介电特性劣化的现象。
参阅图6所示,为HSQ介电层在不同氨等离子处理时间下所得到的红外线光谱(infrared spectroscopy)图。其中,曲线A、B分别代表未经本发明方法处理的HSQ介电层经去光阻制程前、后的红外线光谱。曲线C、D、E则分别为HSQ介电层在经去光阻制程前先分别利用本发明方法而进行3、6、9分钟的氨等离子处理所得的红外线光谱。其中,吸收峰1与吸收峰2分别代表Si-H与Si-OH键的吸收峰,其吸收位置分别为2200-2300cm-1以及3000-3500em-1处。
比较曲线A、B可知,HSQ介电层在经过去光阻制程后,原本位于HSQ介电层中的Si-H键的吸收峰1消失,且原本不存在的Si-OH键的吸收峰2出现,证明去光阻制程将造成HSQ介电层表面结构受损。而先经氨等离子处理过的曲线C、D、E的吸收峰1仍然存在且吸收峰2并未产生,显示氨等离子的事先处理能成功防止Si-H键被打断,并避免形成Si-OH键。
此外,Si-H键的吸收峰1的吸收度明显随着氨等离子的处理时间增加而下降,故进行等离子处理时间建议控制于20分钟之内,以避免因处理时间过长而使介电层上Si-H官能基受损,并使介电层中包含过多的氮原子而增加其介电常数值。
参阅图7-图8所示,分别为氨等离子处理时间对HSQ介电层的介电常数和漏电流密度的影响。
由图7中可知,HSQ介电层进行氨等离子处理(3、6、9分钟)的介电常数较未经氨等离子处理(0分钟)的介电常数为低,且在氨等离子处理进行超过3分钟后,即可维持在3左右,显示增加等离子处理的时间并不影响介电常数。
而图8中亦显示相同结果,方块■、正三角形▲、倒三角形分别代表在经过3、6、9分钟的氨等离子前处理再进行去光阻制程的HSQ介电层中电场与漏电流密度的关系曲线,而圆型●则代表未经等离子处理即进行去光阻制程的HSQ介电层中电场与漏电流的关系曲线。
由图8中明显可知:先经氨等离子处理的介电层的漏电流,明显较未经处理的介电层的漏电流大幅降低2-3个数量级(order),且进行氨等离子处理时间超过3分钟后,增加氨等离子处理时间并不显著影响漏电流的大小。故在本发明的最佳实施例中,进行氨等离子处理的时间约为3分钟。
综合上述说明,为了避免去光阻制程对低介电常数介电层所造成的伤害,本发明在蚀刻制程之前,便先将低介电常数介电层经含氮等离子处理,使低介电常数介电层表面形成一钝化层,接着再进行去光阻制程,以减少之后氧等离子与去光阻液对低介电常数介电层的反应机会,进而避免低介电常数介电层于此制程步骤中受到伤害。因此,本发明的方法可有效防止低介电常数介电层中形成Si-OH键(如图6所示),以解决传统制程所导致的介电常数与漏电流增加(如图7与图8所示)的问题。
本发明的方法相较于传统蚀刻低介电常数介电层的制作方法,本发明先利用一含氮等离子来处理低介电常数介电层表面,以抑制低介电常数介电层于后续的去光阻制程中受到损害而生成Si-OH键,进而解决传统制程所导致的介电常数与漏电流增加的缺陷,提升半导体晶片的优良率。
以上所述为本发明的较佳实施例,凡依本发明所做的均等变化与修饰,皆应属于本发明的保护范围之内。
Claims (17)
1、一种在去光阻制程中避免低介电常数介电层劣化的方法,其特征是:它包括如下步骤:
(1)低介电常数介电层是形成于基底表面,对该低介电常数介电层进行表面处理,于该低介电常数介电层表面形成钝化层;
(2)于该基底上形成图案化的光阻层;
(3)利用该光阻层作为硬屏蔽,对该低介电常数介电层进行蚀刻制程;
(4)进行去光阻制程。
2、根据权利要求1所述的方法,其特征是:该基底选自硅晶片。
3、根据权利要求1所述的方法,其特征是:该低介电常数介电层选自hydrogen silsesquioxane、methyl silsesquioxane、hydriopolysilsesquioxane、methyl polysilsesquioxane、phenylpolysilsesquioxane、HOSP或多孔性凝胶。
4、根据权利要求3所述的方法,其特征是:该低介电常数介电层是选自化学气相沉积法或旋涂方式形成于该基底上。
5、根据权利要求1所述的方法,其特征是:该表面处理为等离子处理。
6、根据权利要求5所述的方法,其特征是:该等离子处理是进行于含氮的气氛环境下,于该低介电常数介电层表面形成该钝化层。
7、根据权利要求6所述的方法,其特征是:该含氮的气氛环境选自包含有氧化亚氮、一氧化氮或氨气。
8、根据权利要求5所述的方法,其特征是:该等离子处理的无线电波频率为100-300瓦,该等离子处理的真空度是保持在10-3-10-6Torr之间,且该等离子处理的时间小于20分钟,该基底的温度是低于250℃。
9、根据权利要求1所述的方法,其特征是:该去光阻制程是选自湿式去光阻制程,该钝化层是避免该低介电常数介电层于该湿式去光阻制程中形成Si-OH键,而吸附水气,导致该低介电常数介电层的介电常数及漏电流上升而劣化该低介电常数介电层的介电特性。
10、一种在去光阻制程中避免低介电常数介电层劣化的方法,其特征是:它包括如下步骤:
(1)低介电常数介电层是形成于基底表面,对该低介电常数介电层进行表面处理,于该低介电常数介电层表面形成钝化层;
(2)于该基底上形成图案化的光阻层;
(3)利用该光阻层作为硬屏蔽,对该低介电常数介电层进行蚀刻制程;
(4)进行湿式去光阻制程;其中该钝化层是用来抑制该低介电常数介电层于该湿式去光阻制程中形成Si-OH键而吸附水气,进而避免该低介电常数介电层发生介电特性劣化的现象。
11、根据权利要求10所述的方法,其特征是:该基底是选自硅晶片。
12、根据权利要求10所述的方法,其特征是:该低介电常数介电层选自hydrogen silsesquioxane、methyl silsesquioxane、hydriopolysilsesquioxane、methyl polysilsesquioxane、phenylpolysilsesquioxane、HOSP或多孔性凝胶。
13、根据权利要求12所述的方法,其特征是:该低介电常数介电层是选自化学气相沉积法或旋涂方式形成于该基底上。
14、根据权利要求10所述的方法,其特征是:该表面处理选自等离子处理。
15、根据权利要求14所述的方法,其特征是:该等离子处理是进行于含氮的气氛环境下,于该低介电常数介电层表面形成该钝化层。
16、根据权利要求15所述的方法,其特征是:该含氮的气氛环境选自包含有氧化亚氮、一氧化氮或氨气。
17、根据权利要求14所述的方法,其特征是:该等离子处理的无线电波频率为100-300瓦,该等离子处理的真空度是保持在10-3-10-6Torr之间,该等离子处理的时间小于20分钟,该基底的温度是低于250℃。
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WO2020006945A1 (zh) * | 2018-07-02 | 2020-01-09 | 深圳市华星光电半导体显示技术有限公司 | 背沟道蚀刻型tft基板的制作方法及背沟道蚀刻型tft基板 |
CN109119427B (zh) * | 2018-07-02 | 2020-07-28 | 深圳市华星光电半导体显示技术有限公司 | 背沟道蚀刻型tft基板的制作方法及背沟道蚀刻型tft基板 |
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