CN101063065A - 半导体晶片的清洗溶液及内连线结构的形成方法 - Google Patents
半导体晶片的清洗溶液及内连线结构的形成方法 Download PDFInfo
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- CN101063065A CN101063065A CNA200710005732XA CN200710005732A CN101063065A CN 101063065 A CN101063065 A CN 101063065A CN A200710005732X A CNA200710005732X A CN A200710005732XA CN 200710005732 A CN200710005732 A CN 200710005732A CN 101063065 A CN101063065 A CN 101063065A
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- dielectric layer
- opening
- dielectric constant
- acid
- low dielectric
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Images
Classifications
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- C—CHEMISTRY; METALLURGY
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- C11D—DETERGENT COMPOSITIONS; USE OF SINGLE SUBSTANCES AS DETERGENTS; SOAP OR SOAP-MAKING; RESIN SOAPS; RECOVERY OF GLYCEROL
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- C11D2111/22—
Abstract
本发明提供一种半导体晶片的清洗溶液及集成电路的内连线结构的形成方法,上述半导体晶片的清洗溶液,包括:有机溶剂;金属试剂;置换剂;以及水。
Description
技术领域
本发明涉及一种集成电路,特别是涉及一种具有多孔性低介电常数材料的内连线构造的形成制造方法。
背景技术
一般而言,高密度集成电路,例如超大型集成电路(VLSI)会形成多重金属内连线,以作为三维空间(3D)导线结构。多重金属内连线的目的在于紧密地将包埋的元件连接在一起。随着各层的积集度的提升,金属内连线之间的寄生电容会随之增加,从而导致电阻电容延迟(RC延迟)与串音(cross talk)。为了降低寄生电容以及提升金属内连线之间的导电速度,通常使用低介电常数材料(low k dielectric)以形成层间介电层(inter-layer dielectric;ILD)以及金属间介电层(inter-meal dielectric;IMD)。
经常用来形成低介电常数相关结构之一的结构为金属硬掩模(metal hardmask;MHM)结构,其中金属硬掩模是用来保护低介电常数介电层,使免于受到化学机械研磨(chemical mechanical polishing;CMP)的损害。一般而言,在低介电常数介电层上形成覆盖层(cap layer)或底部抗反射涂布层,之后形成金属硬掩模层。接下来,可使用光致抗蚀剂作为掩模以图案化上述金属硬掩模层以及上述覆盖层,再将此图案转移到下方的低介电常数介电层以形成内连线。此内连线的制造方法通常包括在低介电常数介电层形成开口,再将导电材料填入此开口中,然后进行化学机械研磨法以平坦化导电材料的表面,之后,移除金属硬掩模。
在低介电常数介电层形成开口的步骤会产生特定的副产物,例如为有机与无机副产物,此副产物对于后续的步骤以及最终的集成电路会有不良的影响。以往,需要进行多个清洗步骤以移除这些副产物,然而,多个清洗步骤通常较为复杂且包括干式清洗及湿式清洗两者。因此,需要一种较为简化的清洗方法。
发明内容
根据上述目的,本发明提供一种半导体晶片的清洗溶液,其包括有机溶剂;金属试剂;置换剂;以及水。
本发明还提供一种半导体晶片的清洗方法,包括将该半导体晶片浸入清洗溶液,该清洗溶液包括:有机溶剂;金属试剂;置换剂;以及水。
本发明又提供一种集成电路的内连线结构的形成方法,包括:形成低介电常数介电层在基底上;形成金属硬掩模在该低介电常数介电层上;图案化该金属硬掩模以在该金属硬掩模中形成第一开口,其中经由该第一开口露出该低介电常数介电层;经由该第一开口蚀刻该低介电常数介电层以在该低介电常数介电层之中形成第二开口;通过将该基底与该基底上方的结构浸入清洗溶液,以进行清洗步骤,其中该清洗溶液包括:有机溶剂;金属试剂;置换剂;以及水;形成阻障层在该第二开口之中;以及填入导电材料在该第二开口。
上述清洗溶液可利用单一步骤去除在形成内连线结构过程中所产生的有机及无机副产物。
附图说明
图1至图9为本发明较佳实施例的各制造阶段中集成电路内连线结构的剖面图。
【主要部件符号说明】
10~介电层;
12~金属导线;
14~蚀刻停止层;
20~低介电常数介电层;
22~覆盖层;
24~金属硬掩模层;
26~反射涂布层;
28、36~光致抗蚀剂;
30、32、38、40~开口;
34~底部抗反射涂布层;
42~沟漕开口;
44~介层孔开口;
46、48、50~副产物层;
52~阻障层;
54~介层孔导通物;以及
56~金属导线。
具体实施方式
图1至图9为本发明较佳实施例的各制造阶段中集成电路内连线结构的剖面图。其中本发明的实施例中,相同的符号代表相同的元件。
请参考图1,形成金属导线12在介电层10中,此金属导线12较佳包含铜或铜合金。较佳者,可视需要形成扩散阻障层(图未显示)在金属导线12与介电层10之间。接着,形成蚀刻停止层14在金属导线12与介电层10之上。蚀刻停止层14较佳包含氮化硅、氧化硅、碳化硅、氮氧硅化物及/或其他常用的材料。
图2显示蚀刻停止层14上方的低介电常数介电层20的形成。低介电常数介电层20的介电常数(k值)较佳小于3.5,更佳为小于2.5,因此有时也称为超低的介电常数层。低介电常数介电层20较佳包含掺碳氧化硅、掺氟氧化硅或类似的材料。低介电常数介电层20的沉积方法包括旋转涂布法、化学气相沉积法(CVD)、等离子体加强型化学气相沉积法(PECVD)、低压化学气相沉积法(LPCVD)或其他类似的沉积技术。
接着,形成覆盖层22在低介电常数介电层20上,此覆盖层22较佳为不含氮,更佳者为包含例如碳或氧的材料。再者,覆盖层22也可以在后续即将形成的金属硬掩模图案化时作为底部抗反射涂布层(BARC)。因此,覆盖层22又称为不含氮的抗反射涂布层(NFARC)22。覆盖层22的形成方法包括化学气相沉积法或物理气相沉积法,然而,例如原子层沉积法等其他方法也可以使用。
之后,形成金属硬掩模层24在覆盖层22上,此金属硬掩模层24较佳由例如钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)、铝(Al)或类似的金属所形成,也可以使用例如氧化硅、碳化硅、氮化硅或氮氧硅化物等非金属材料构成非金属硬掩模结构来取代上述金属硬掩模层24。
请参照图3,形成抗反射涂布层26在金属硬掩模层24上方。由于抗反射涂布层26是形成在后续即将形成的光致抗蚀剂28的下方,所以抗反射涂布层26也称为底部抗反射涂布层(BARC)。在另一实施例中,可以在后续即将形成的光致抗蚀剂28的上方形成顶部抗反射涂布层(TARC)。底部抗反射涂布层26会吸收光并且提供最大的(ultimate)临界尺寸的控制。底部抗反射涂布层26可以利用旋转涂布法技术或在气相反应器中沉积而形成。
然后,形成并图案化光致抗蚀剂28,使开口30形成在光致抗蚀剂28之中以暴露出下方的底部抗反射涂布层26。接下来,通过穿过开口30而蚀刻底部抗反射涂布层26与金属硬掩模层24以形成穿过金属硬掩模层24的开口32,如图4所示。接着,移除光致抗蚀剂28与底部的抗反射涂布层26。在接下来的双镶嵌制造中,开口32是用来定义金属导线用的沟槽图案。
请参照图5,形成底部抗反射涂布层34与光致抗蚀剂36。接着,图案化光致抗蚀剂36而形成开口38,此光致抗蚀剂36定义出即将形成的介层孔的图案。
接下来,如图6所示,进行介层孔局部蚀刻(via partial etch)。以光致抗蚀剂36作为掩模,移除光致抗蚀剂36下方的各层,其包括底部抗反射涂布层34、覆盖层22以及低介电常数介电层20,而在低介电常数介电层20中形成开口40。控制蚀刻方法以使得开口40具有想要的深度,此深度小于低介电常数介电层20的厚度。最好使用干蚀刻进行介层孔局部蚀刻。在此较佳实施例中,使用等离子体蚀刻。接着,进行灰化方法移除光致抗蚀剂36,而产生如图7所示的构造。
图8显示沟漕开口42与介层孔开口44的形成,其中使用的蚀刻较佳为干蚀刻。在此较佳实施例中,使用等离子体蚀刻,而具体的蚀刻气体较佳为包含四氟甲烷(CF4)、八氟环丁烷(C4F8)或其余类似的气体。此蚀刻方法侵蚀底部的抗反射涂布层26、覆盖层22以及低介电常数介电层20。如本领域技术人员所知,结合适当的化学物质与处理控制条件,在可控制的速度下形成沟漕开口42与介层孔开口44。在此蚀刻过程中,开口40往下延伸至蚀刻穿过低介电常数介电层20,而形成介层孔开口44,同时,以金属硬掩模层24作为新的掩模,蚀刻没有被金属硬掩模层24保护的低介电常数介电层20的部分。由于金属硬掩模层24定义作为金属导线的漕沟图案,因而形成沟漕开口42。在小心的控制蚀刻处理下,当介层孔开口44达到低介电常数介电层20底部时,沟漕开口42会达到想要的深度。接着进行衬层(liner)移除步骤,由介层孔开口44中移除露出的蚀刻停止层14。
在介层孔局部蚀刻、蚀刻沟漕开口42与介层孔开口44以及衬层移除的步骤时,会形成副产物。一般而言,这些副产物包含有机副产物以及无机副产物两种,如图8所示。例如,由于等离子体蚀刻会损害金属硬掩模层24的表面,而形成如图8所示的副产物层46。在具体实施例中,其中金属硬掩模层24包含钛,则副产物层46可能会包含氟化钛。蚀刻含碳的低介电常数介电层20时,沟漕开口42与介层孔开口44的侧壁处会形成碳有机层构成的副产物层48。在介层孔开口44的底部,会形成副产物层50,其可包含氧化铜(CuO)、氟化铜(CuF)或类似物质。然而,可以理解的是,先前所讨论的副产物以及相关的层只是例子,可能会随着不同的低介电常数介电层20、金属硬掩模层24、金属导线12以及蚀刻气体的材料等而改变。副产物层46、48、50可能包含任何以上讨论的有机或无机副产物。
对于后续的处理而言,这些副产物有不利的影响。例如,氟化钛会污染后续形成的扩散阻障层与铜填充物的结构。碳有机材料不仅会增加内连线构造的k值,也会降低内连线构造的可靠度。氧化铜与氟化铜会增加介层孔的电阻并且也影响到介层孔的可靠度。因此,有需要移除这些副产物。
在此较佳实施例中,提供清洗溶液,再通过将上方形成有上述结构的晶片浸入在此清洗溶液中,来移除副产物。此清洗溶液的较佳的温度是介于约20℃至约70℃之间。较佳的清洗时间是小于8分钟,更佳是小于4分钟。然而,温度高于70℃或低于20℃、清洗时间大于8分钟也可以使用。本领域技术人员可以通过例行的经验而找到最佳的时间与温度。
此清洗溶液较佳包含四种成份:用来移除有机副产物的有机溶剂;用来移除无机副产物的金属试剂;用来控制清洗过程的置换剂(substitutive agent);以及水(较佳为去离子)。在此较佳实施例中,此清洗溶液包含约0.01%至约90%重量百分比的有机溶剂、约0.01%至约30%重量百分比的金属试剂、约0.01%至约30%重量百分比的置换剂以及约0.01%至约70%重量百分比的水。更佳为有机溶剂的重量百分比为介于约50%至约80%、金属试剂的重量百分比为介于约0.01%至约10%、置换剂的重量百分比为介于约0.01%至10%以及水的重量百分比为小于约50%。
此有机溶剂较佳包含选自由单甲基醚丙二醇(propylene glycolmonomethyl ether)、乙二醇(ethylene glycol)、1,4-丁炔二醇(1,4-butynediol)、丁酸内酯(butyrolactone)、二乙二醇单丁醚(diethylene glycol monobutyl ether)、二乙二醇单己醚(diethylene glycol monohexyl ether)、N-N二甲基乙酰胺(N,N-dimethyl acetamide)、N-甲基-2-吡咯烷酮(N-methyl-2-pyrrolidone)、环戊酮(cyclopetanone)及二甲基亚砜(dimethylsulfoxide)构成的群组中的一种或多种。
此金属试剂较佳包含选自由草酸(oxalic acid)、丙二酸(malonic acid)、柠檬酸(citric acid)、乳酸(lactic acid)、甘醇酸(glycolic acid)、丙酸(propionicacid)、苯并三唑(benzotriazole)、1,2,4-1H-三氮唑(1,2,4-1H-triazole)、7-甲基哚吲-2-羧酸(7-methylindole-2-carboxylic acid)、硫代甘油(thioglycerol)、1-吡咯啉-5-羧酸物(1-pyrroline-5-carboxylate)、四甲基氟化铵(tetramethyl ammoniumfluoride)、1,2-乙烷二羧酸(1,2-ethanedicarboxylic acid)及乙醛酸(GlyoxylicAcid)构成的群组中的一种或多种。
此置换剂较佳包含选自由四甲基氢氧化铵(tetramethyl ammoniumhydroxide)、四乙基氢氧化铵(tetraethyl ammonium hydroxide)、四正丁基氢氧化铵(tetra-n-butylammonium hydroxide)、3-氨基丙酸(3-aminopropanoic acid)、4-氨基丁酸(4-aminobutyric acid)、6-氨基己酸(6-aminohexanoic acid)及5-氨基戊酸(5-aminovaleric acid)构成的群组中的一种或多种。
在具体清洗溶液中,有机溶剂包含约60%至约80%重量百分比的二甲基亚砜及/或N-甲基-2-吡咯烷酮,金属试剂包含约0.5%至约2%重量百分比的柠檬酸、硫代甘油及/或1,2,4-1H-三氮唑,置换剂包含约0.5%至约2%重量百分比的四甲基氢氧化铵及/或四正丁基氢氧化铵以及约25%重量百分比的水。在另一具体清洗溶液中,有机溶剂包含约60%至约80%重量百分比的二甲基亚砜及/或N-甲基-2-吡咯烷酮,金属试剂包含约0.5%至约2%重量百分比的四甲基氟化铵、硫代甘油及/或1,2,4-1H-三氮唑,置换剂包含约0.5%至约2%重量百分比的四正丁基氢氧化铵以及约25%重量百分比的水。
在清洗处理之后,副产物层46、48以及50会被移除。图9显示形成阻障层52、介层孔导通物54以及金属导线56。阻障层52较佳包含钛、氮化钛、钽、氮化钽、碳化硅、碳氧硅化物或类似的材料。阻障层52可防止介层孔导通物材料,特别是铜,扩散至低介电常数介电层20而引发电路失效。填入导电材料在沟漕开口42与介层孔开口44中,较佳的导电材料例如为铜、钨、金属合金、金属硅化物或金属氮化物。然后利用化学机械研磨法(CMP)移除过量的材料,留下金属导线56与介层孔导通物54。最好也利用化学机械研磨法移除金属硬掩模层24,或者可以在化学机械研磨法后,再以蚀刻法移除金属硬罩层24。
本发明的较佳实施例所提供的清洗溶液可以同时移除有机以及无机副产物。因此,也可以用于其他会产生有机及/或无机副产物的半导体形成方法。可应用的方法包括,但不限于双镶嵌方法、单镶嵌方法及/或任何其他以干蚀刻来蚀刻含碳的低介电常数材料的方法。
本发明的较佳实施例具有几项优点。仅需要一个步骤移除有机以及无机副产物,因此,可明显地简化清洗方法。实验结果显示内连线结构的产率也获得改善。另外,内连线结构的寄生电容仍保持在较低值。
Claims (12)
1.一种半导体晶片的清洗溶液,包括:
有机溶剂;
金属试剂;
置换剂;以及
水。
2.如权利要求1所述的半导体晶片的清洗溶液,其特征在于该有机溶剂的重量百分比介于0.01%至90%之间,该金属试剂的重量百分比介于0.01%至30%之间,该置换剂的重量百分比介于0.01%至30%之间,以及该水的重量百分比介于0.01%至70%之间。
3.如权利要求1所述的半导体晶片的清洗溶液,其特征在于该有机溶剂包括选自由单甲基醚丙二醇、乙二醇、1,4-丁炔二醇、丁酸内酯、二乙二醇单丁醚、二乙二醇单己醚、N-N二甲基乙酰胺、N-甲基-2-吡咯烷酮、环戊酮及二甲基亚砜构成的群组中的一种或多种。
4.如权利要求1所述的半导体晶片的清洗溶液,其特征在于该金属试剂包括选自由草酸、丙二酸、柠檬酸、乳酸、甘醇酸、丙酸、苯并三唑、1,2,4-1H-三氮唑、7-甲基哚吲-2-羧酸、硫代甘油、1-吡咯啉-5-羧酸物、四甲基氟化铵、1,2-乙烷二羧酸及乙醛酸)构成的群组中的一种或多种。
5.如权利要求1所述的半导体晶片的清洗溶液,其特征在于该置换剂包括选自由四甲基氢氧化铵、四乙基氢氧化铵、四正丁基氢氧化铵、3-氨基丙酸、4-氨基丁酸、6-氨基己酸及5-氨基戊酸构成的群组中的一种或多种。
6.一种集成电路的内连线结构的形成方法,包括:
形成低介电常数介电层在基底上;
形成金属硬掩模在该低介电常数介电层上;
图案化该金属硬掩模以在该金属硬掩模中形成第一开口,其中经由该第一开口露出该低介电常数介电层;
经由该第一开口蚀刻该低介电常数介电层以在该低介电常数介电层之中形成第二开口;
通过将该基底与该基底上方的结构浸入清洗溶液,以进行清洗步骤,其中该清洗溶液包括:
有机溶剂;
金属试剂;
置换剂;以及
水;
形成阻障层在该第二开口之中;以及
填入导电材料在该第二开口。
7.如权利要求6所述的集成电路的内连线结构的形成方法,还包括在形成该低介电常数介电层之前形成金属图案在介电层中,其中在该低介电常数介电层蚀刻步骤之后,经由该第二开口露出该金属图案。
8.如权利要求6所述的集成电路的内连线结构的形成方法,其特征在于蚀刻该低介电常数介电层的步骤包括等离子体蚀刻。
9.如权利要求6所述的集成电路的内连线结构的形成方法,其特征在于该有机溶剂的重量百分比介于0.01%至90%之间,该金属试剂的重量百分比介于0.01%至30%之间,该置换剂的重量百分比介于0.01%至30%之间,以及该水的重量百分比介于0.01%至70%之间。
10.如权利要求6所述的集成电路的内连线结构的形成方法,其特征在于该基底浸入该清洗溶液中的时间小于8分钟。
11.如权利要求6所述的集成电路的内连线结构的形成方法,其特征在于该清洗溶液的温度介于20℃至70℃之间。
12.如权利要求6所述的集成电路的内连线结构的形成方法,其特征在于蚀刻该低介电常数介电层的步骤包括:
经由位于该金属硬掩模上的光致抗蚀剂内的开口蚀刻部分的低介电常数介电层;
灰化该光致抗蚀剂;以及
利用该金属硬掩模作为掩模,并蚀刻该低介电常数介电层使得该第二开口包含沟槽开以及介层孔开口,其中蚀刻该介层孔开口深及该低介电常数介电层的底部。
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