TW483154B - Method of manufacturing Ta2O5 capacitor using Ta2O5 thin film as dielectric layer - Google Patents

Method of manufacturing Ta2O5 capacitor using Ta2O5 thin film as dielectric layer Download PDF

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TW483154B
TW483154B TW089123450A TW89123450A TW483154B TW 483154 B TW483154 B TW 483154B TW 089123450 A TW089123450 A TW 089123450A TW 89123450 A TW89123450 A TW 89123450A TW 483154 B TW483154 B TW 483154B
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pentoxide
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TW089123450A
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Kee-Jeung Lee
Kwang-Chul Joo
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Hyundai Electronics Ind
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Chemical Vapour Deposition (AREA)

Description

483154 五、發明說明（1) 〈發明之背景〉 本發明係有關一種半導體元件之電 特別是-種以五氧化二钽（Ta2〇5)薄法， 高電容量之電容器製造方法。 為；I電層而具有 〈先前技藝之描述〉 就我們熟知，習見之電容器， 取記憶體（DRAM )記憶體元件儲存次為如動態隨機存 客且右一拄媛，品—从樣士 域存貝料之用；此種電容器 夕具有、？籌，而戎結構中’多具有一 層電極之間之介電層；以如此方式 下層电=二上 曰 A门。士 A㊉ 八形成之電容器之電容 Ϊ，係同％只电極之面積、與介電層之介電常數成正比， 並與兩電極之間之間隔，即：介電層之厚度成反比。 電容器之電容量，因此得以因電極之表面積增加而增 加，亚因介電材質具有較高之介電常數、或/與介電層之 厚度之減少，而形成一種介電性較高之介電層；由於在不 引起介電失效的情形下，介電層之厚度之減少容易受侷 限，因此習見增加電容量之方法，多集中於增加電極表面 積，或/與使用一具有較高介電常數之介電層。 電極之表面積可藉由一具有立體結構，如圓柱狀結 $、或其他增加了高度而以聚合矽（p〇lysiUc〇n)為材 貝之半球形顆粒狀（Hemi Spherical Grain，HSG)結 構’使下層電極之有效面積增加；然而，上述圓柱狀、或 聚合石夕（polysilicon)之半球形顆粒狀（Hemi Spherical Grain，HSG )立體結構之下層電極，製造上則 更加困難；尤其在這些案例當中，由於下層電極高度之增
第4頁 483154 五、發明說明（2) 加’晶胞區域（cell region)與外層圓周區域 (peripheral circuit region )之間的型態上 (topology )的差距也會跟著增加；這些高度上的差距， 使得接下來的製造過程效能降低、且複雜度升高，尤其是 使知接下來光刻印刷（photolithography)過程當中，產 生厚度與曝光程度控制上的問題。 因此，目前的努力的方向，係生產一種具有高電容量 之電容器，並集中於發展一種具以更高介電常數之介電 層。 舉例來說 很廣泛地被使 種更簡單，只 用作為介電層 )多介於4至5 電容器無法提 一代動態隨機 的，是下一代 鬲於2 56M晶胞 容量，來有效 間；因此，一 電層之Ta205電 結構做為介電 (Ta2〇5 )薄膜 之介電常數， ，具有 用為介 具有氧 ，因為 之間， 供足多句 存取記 動態隨 、而需 降低軟 種具有 容器則 層之電 之電容 因此一 氧-氮-氧（0N0 )層之疊層狀結構已 電層；然而，為了增加電容量，有一 化氮層（Ν 0 )的疊層結構被提出而使 上述氧化氮層（NO)之介電常數（ε 因此使用本一氧化氮層（NO )結構之 的電容量，來生產多於256M晶胞之下 憶體（DRAM )之產品中·；但可預期 機存取記憶體（DRAM )產品將會需 要每晶胞25fF (25fF/cell)之曰高^電 體錯誤的產生與軟體之更新計算時、 介電常數25至27之Τ〜〇5薄膜來^為八 被提出，取代上述以氧化氮層（^ 容器；由於上述利用五氧化二起 ） 器’具有比氧化氮層（NO )結構 種五氧化二钽（Ta205 )電容器巧 係可
483154
輕易生產出具有高於2 56M晶胞之下—. 體（DRAM)之產品。 戈動悲^機存取記憶 然而，以上述五氧化二鈕（Ta ^ 介電層來製作高容量電容器，其對2製5 ‘ J，膜作為 仍有下列困難點·· 私雖有功效，但 1 ·因為上述五氧化二鈕（Ta 〇、 人 化學量，因此一可被替換之钽（Ta5)原：ς有不穩定之 位的薄膜巾，使一小部分的外漏電流產生：且：：氧氣空 的數量，會因薄膜中鈕（Ta)原 Μ卜漏電流 =數之不同而不同；因此一額=二原序子之二成 五乳化二鈕（Ta205 )薄膜後，需被操作用於去：：貝 的體積；而此種額外料，使得製 避：：：？ 雜化。 你“、、j避免地被複 、2.五氧化二鈕（Τ\〇5)薄膜會同時氧化兩種 成亡下層電極組成之材質，即：聚合矽（polysi ; 與氮化鈦（TiN);結果’從五氧化二组（Ta.2〇5)薄〇: 產生的氧原子（〇 )，易於退火過程中與電極之5材料、 ^應=氧化，並於電極之間的介面上形成一低介電'性 層。而上述之氧化層之形成，同時降低了介面之均一=、 與所製成之電容器之與電性特徵。 二五氧化二组（Ta2〇5 )層之前導化合物的有機物 钽^氧基化物（Ta (〇C2H5)5)，係與氧氣（〇2)或氧化、二 氮氣體（)產生化學反應而產生碳原子、與如甲烧^ (c^4)、乙烧（（^4)之碳分子化合物、與水蒸氣（Η。 五、發明說明（4) ^ :=替地合併於五氧化二钽（Μ 電容哭3 存加速了外漏電流之產生，丑降：： 电奋為的介電特性。 並降低了 〈發明之總論〉 _ 口此，本發明旨在提供一種製造五氧化_ 4 薄膜做為介雪思七< _儿—裡表把乳化—叙（Ta^ ) 依本發ΐ之！！ίΐ:组（Ta2〇5)電容器製造方法， 之五备 製 氧化二鈕（τ〜〇5)薄膜做為介雷# 之五氧化二紐（Ta〇q)電交哭从士、土 丁咖μ 兩"電層 程庠，土人 2 為的方法不需額外加入氧化 過程十客除以五氧化二鈕（Ta2〇5)薄膜做為介電層之製造 產生的氧氣空位；此為本發明之第一目的。& 六抑=本發明之此種發明，提供一五氧化二鈕（T°a〇 :=、方法，足以避免電極中之五氧化二組 2 5 : 声；此I· t的（2 )產 學反應，而產生介電性氧化 9 此為本發明之另一目的。 ，本發明之此種發明，提供一種五氧化二鈕 電谷器的製造方、去，可藉由你$ — 2 5 ) 去除有機呤所 々命甘入 化一鈕（Ta2〇5 )薄膜中 本發明？ Ϊ貝 ，,電性與外漏電流的特性；此為 十设昍之再一目的。 的製：ί t明之此種發明’提供一種達到上述目的電容器 方法係包括：使用一種半導體基層，在其 上开(ίί疋圖#，炎覆盍上—介f絕緣層；於中介絕緣層 “之：：層電極、將下層電極之表面氮化；將非晶性狀 ^ . 虱化二鈕（Τ\〇5 )薄膜沈積於上述經氮化之下層
電極表面，·以低溫退火上述非晶性五氧化二纽心K
叫154 、發明說明（5) 膜’並將經過低溫退火之上述五氧化二钽（Ta2〇5 )薄膜置 於高溫中退火而形成一結晶狀五氧化二钽（Ta2〇5 )薄膜， 做為介電層；最後，於上述結晶化之介電層上，形成_上 層電極。 至於本發明之詳細構造、應用原理、作用與功效、則 可參照下列附圖所做之說明即可得到完全的瞭解。 〈較佳具體實施例之描述〉 習見之電容器之製造方法之實施例作用之情形與其缺 點’已如前所述，此處不再重複敘述。 請參照第1 A圖；可明顯看出一半導體基層1，藉由基 層ί形成一特定下層圖樣（未示出），即：提供/種形成 例如電晶體或電阻器之基礎結構；藉由上述基層1，形成 一中介絕緣層2，並覆蓋於上述基礎結構上；藉由所述介 貝絕緣層2，使用已知方法，形成一下層電極3，|下層電 極3與基層1上選定之部位接觸；下層電極3較佳的係以摻 雜的聚合矽層（doped P〇lysilic〇n)為材料製造，而形
成一疊層狀結構體；另有一種方法，係從氮化钽（TiN )、氮化鈦（TaN)、鹤（W)、石夕化鶴（⑽）、釕（Ru )、二氧化釕（Ru02 ) 、I r (鉉、 卜 、、 # (PU 二氧化銀（Ir〇2\ /寻1^彳又I释取代所述摻雜的聚合矽層（doped ΓΗ: Sh 形成如圓柱狀或半顆粒形結晶狀 广工 Spherieal Grain，HSG)之三度
483154 五、發明說明（6) 請參照1B圖，下層電極3的表面經過 絕緣層2表面上氣氣的吸收上二下化 田中虱化的過私係用以避免於下層 電極/、乳化—钽（Ta205 )薄膜之間的介面之上發生不 需要的氧化過程。 n k 氮化的過程，利用充滿阿摩尼亞（NH3 )、或反應氣 體（ΐνΐ )的LPCVD腔室釋放出電漿i至5分鐘，於RF力量 50至5 0 0W、氣體流速介於5〇〇至5〇〇 sccm、盥 6()脫 耳“。…壓之條件下操作；氣化過程期、：，1= =度需介於3 0 〇至5 〇 〇 °C之間；此外，亦可利用快速加熱過 程（Rapid Thermal Process ，RTP)，於650-95(TC 之 =^且溫度提升速率環境於5〇 —15〇〇c/分鐘的氨氣（Nl) 晨兄中退火一晶片2 0至1 8 0秒；或是，於溫度約 5 〇 0 -10 〇 〇 °c的電熱熔爐中下退火一晶片5至3 〇分鐘。 、、 為了增進電容特性，一項利用氟化氫（H F )蒸氣或溶 液的清潔程序，可於氮化程序進行前操作，而去除位於下 層電極3表面上的一切自然氧化物（如二氧化矽（S i 〇2 ) )，此外’一項利用ΝΗ40Η溶液或硫酸（H2S04 )的清潔程 序亦可在利用氟化氫（HF )蒸氣之清潔程序之前/後操 作’以改良下層電極3之均一性。 在氮化程序之後，可藉由於二氧化氮（N02 )或氧（〇2 )環境中退火一晶片的程序，操作一項簡易氧化的過程； 其中’簡易氧化過程，係藉由於溫度約7〇〇-80 0 °C的電熔
第9頁 五、發明說明（7) ------ ' ------ 一~ 爐中退火曰曰片5 - 1 〇分鐘而達成；此外，所述簡易氧化 之過程，亦Μ 错，操作以快速加熱過程（Rapid Thermal roce/s ’ RTP )於約75〇一95〇。〇的環境中，退火一晶片； =了氮化程序之外’所述簡易氧化的過程，可更有效地抑 於下層私極與五氧化二鋁（τ〜〇 之間介面上 要的氧化。 卜而 ？ 此外，f* ;rh、& ^ $虱化過程，可被省略。在此案例中，一厚 度、力在5 入的砂氮化物（Si3N4 )層沈積於下層電極3 t，而五氧化二叙（Ta2〇5 )薄膜隨即沈積於上述矽氮化物 層上。 =參照第1 c圖，一五氧化二鈕（Ta2〇5)薄膜以非晶性 之狀，沈積於已於下層電極3上所形成之氮化物層4上；所 述非晶性之五氧化二鈕（TaJ5 )薄膜接著於低溫中退火； 於初，的低溫中退火之後，五氧化二鈕（TaJ5 )薄瞑接著 置入高溫中退火，而形成一結晶狀五氧化二鈕（τ 膜5而做為電容器之介電層。 . 非晶性之五氧化二鈕（Taj5 )薄膜，係為一經過選定 之鈕（Ta )化合物蒸氣與一反應氣體氨氣（Ni ) ( My 0 00 seem)或氧氣（〇2) (1〇 一 3〇〇 seem)，於溫度介於 3 00-6 0 0 °C、壓力小於10脫耳（t〇rr )的LpcVD腔室條件、 中’具有厚度約50-150A而發生於下層電極3表面上之化 ，反應產品。上較量之反應氣體可以流量控制器（咖 flow controller，MFC)控制注入；而鈕（Ta)化合物蒸 氣，係由鈕乙氧基化物（Ta ( OCgH5)5 )溶液（較佳者，使
483154 五、發明說明（8) 用1度至少99· 9 99 9 % )，以少於i 〇〇 mg/分鐘的速率，利 用流量控制器（mass f l〇w contr〇1 ler , MFC )注入一蒸 發器或一蒸發管，並蒸發所提供之鈕乙氧基化物（Ta (OCgH5 \ )浴液，之後將所形成之蒸氣，經過一注射管， 注入LPCVD腔室中。在上述過程期間，蒸發器或蒸發管， 包括有任何開口、喷嘴、供應管、與其他暴露於鈕（) 化合物蒸氣之表面，係維持於丨5 〇 — 2 〇 〇 〇c的溫度狀態下， 以便於防止紐（Ta )化合物蒸氣的凝結。 施予非晶性之五氧化二鈕（τ、〇5 )薄膜之低溫退火程 序，係利用臭氧（〇3 )或紫外線臭氧（υν_〇3 )的方式，於 300至50JTC環境中操作2至10分鐘，·由於此種退火程序，、« 使在五氧化二鈕（Τ〜〇5 )薄膜中具有可替換性的鈕（^) 原子，即：氧氣空位，可被去除；且，於非晶形五氧化二 鈕（TaA)薄膜中被釋放的碳原子，係被有效的氧氣氧 化，而形成如一氧化碳（C0)，或二氧化碳（c〇2)等具 有揮發性的碳化合物。 ，下來施予非晶形五氧化二鈕（τ〜〇5)薄膜之高溫退 )程序’於充滿氧化二轉0)、氧氣（〇2)、或氮氣 (Μ ，且溫度介於650-95(rc條件下的熔爐中操作5一3〇 ^鐘，在本過程當中，雜質（例如揮發性的碳化合物）鱼 其他反應的產物，可從非晶形五氧化二鈕（Μ)薄膜； 被去除；此高溫退火程序，提高了非晶形五氧化二钽 (TaJ5 )薄膜的密度，同時並使其結晶化。 請參照圖，一電容器之上層1極6°形成於五氧化 483154
案號 89123450 五、發明說明（9) 二妲（TaJ5 )薄膜5上，以本發明之創作， 二鈕（Ta205 )電容器1 〇。上層電極6 乳化 衝層6b構成的一豐層狀結構；其中金屬層 (T i N )、氮化鈕（TaN )、鎢（w ) . ^ ，、&虱化鈦 m ^ 〈W )、石夕化鎢（WSi )、釕 (Ο 、二虱化釕（Ru〇2) 、Ir (銥）、二氧化銥〇 )、广(Pt)之材質中做選擇’而較佳 2 ) ’而具有約1〇-1〇〇入左右的厚度；緩衝層6b較佳 的係以換雜的聚合石夕層構成’而藉以避免電容器 徵於接下來的加熱過程期間被降低。 $ $付 r 述’與習見之五氧化二組（TaA)薄膜做比 較，本發明中之五氧化二!旦（Ta2〇5)薄膜， 與雜質存在的裎度，已經大為被抑制或減少；力是二種 藉由本發明產生之五氧化二㉟（Ta2〇5)電容器， 時具有經改良過之外漏電流之特性、與經改良過之介電 性；此外，本發明之五氧化二钽（TaA) t容器更提供了 一種具有約25-27之介電常數之介電層。 在本發明之五氧化二鈕（Taj5 )電容器製造期間，下 層電極可藉由相對簡單的疊層狀結構形成，且仍然可提供 足夠的電容量’·藉由使用此簡單之疊層狀結構，下層電極 的製造過程可被簡化，因此同時減少了製造時間與花費； 此外，_•施予五氧化二鈕（Τ&〇5)薄膜的傳統快速加熱過程 (Rapid Thermal Process，RTP )與多階段低溫氧化過 程，能夠被省略，進一步地減少了製造成本、與增加了生 產力。
第12頁 483154 五、發明說明（ίο) 由上述所知，本發明之此種五氧化二鈕（T a2 05 )薄膜 做為介電層之五氧化二钽（Ta205 )電容器製造方法，確實 具有製造出高介電性之薄膜，與高電容量之電容器、並提 高其效能與生產力之功效，而其並未見諸公開使用，合於 專利法之規定，懇請賜准專利，實為德便。 需陳明者，以上所述乃是本發明較佳具體的實施例， 若依本發明之構想所作之改變，其所產生之功能作用仍未 超出說明書及圖式所涵蓋之精神時，均應在本發明之範圍 内，合予陳明。 483154 圖式簡單說明 第1A至ID圖，係本發明之製造五氧化二鈕（Ta205 )薄 膜做為介電層之五氧化二钽（Ta205 )電容器製造方法之較 佳具體實施例截面示意圖。 〈圖示中元件編號與名稱對照〉 1 :基層 10 :五氧化二钽（Ta205 )電容器 2 :中介絕緣層 3 :下層電極 4 :氮化層 5 :五氧化二钽（Ta205 )薄膜 6 :上層電極 6 a :金屬層 6b :緩衝層
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Claims (1)

  1. 483154 年/2月〉/曰修正/更正/補充 _案號 89123450 曰 修正 六、申請專利範圍 1. 一種半導體元件之電容器之製造方 於：是種半導體元件之電容器之製造方法 法，其特徵在 ，包含下列步 驟： 準備一種 將半導體 藉由上述 將下層電 於非晶性 於氮化過之下 退火上述 溫度中； 具有下層圖樣的半導體基層； 基層覆以一層中介絕緣層； 中介絕緣層，形成一下層電極； 極之表面氮化； 的狀態下，沈積一五氧化二鈕（Ta2 05 )薄膜 層電極表面上； 非晶性之五氧化二鈕（Ta2 05 )薄膜於初始的 進一步退火五氧化二钽（Ta205 )薄膜於第二種溫度， 初始的溫度為高，並足以形成一結晶狀之五 05 )薄膜，而為介電層；最後 狀之五氧化二钽（Ta?〇s )薄膜，形成上層電 此第二溫度較 氧化二钽（Ta 藉由結晶 極者。 2. 如申請專利範圍第1項所述之方法 係包含一摻雜的聚合$夕層者。 3. 如申請專利範圍第1項所述之方法 係為一傳導層體，包含由氮化鈦（T i N ) 、矽化鎢（WS i )、釕（Ru ) (銥）、二氧化銥（Ir02 ) 者。 專利範圍第1項所述之方法 )、鎢（w ) (Ru02 ) 、Ir 體群中所選出 4.如申請 其中下層電極 其中下層電極 氮化鈕（TaN k二氧化釕 •翻（P t )之導 更進一步於下
    第15頁 483154 _案號891234?^_j 曰 修正_ 六、申請專利範圍 層電極之氮化之前，包括以氟化氫（HF )溶液或蒸氣清潔 下層電極之步驟者。 5 ·如申請專利範圍第4項所述之方法，其中更進一步 地包含了，於上述氟化氫（HF )清潔步驟前或之後，利用 NIOH溶液或硫酸（h2s〇4 )清潔下層電極之步驟者。 6 ·如申請專利範圍第1項所述之方法，其中氮化的步 驟，係包含了，於充滿阿摩尼亞（NH3 )或\/112環境的 LPCVD腔室中，在卜5分鐘内形成電漿（plasma)者。 7 ·如申請專利範圍第6項所述之方法，其中氮化的步 驟’於半導體基層之溫度維持於5 〇〇 °c進行者。 8 ·如申請專利範圍第1項所述之方法，其中氮化的步 驟’包括了利用快速加熱過程（Rap i d Therma 1 ?1：0。635，1^?)，於65〇 — 95〇。〇的阿摩尼亞（題3)環境 中，退火半導體基層者。 9 ·如申請專利範圍第1項所述之方法，其中氮化的步 驟’包括了於溫度約在5 0 0 — 1 〇〇〇。〇而充滿阿摩尼亞（NH3 )的炫爐中，退火一半導體基層者。 I 0 ·如申請專利範圍第1項所述之方法，更包含了一個 當氣化的程序完成之後，立即於二氧化氮（N02 )或氧氣 (〇2 )的環境中退火下層電極之步驟者。 II ·如申請專利範圍第1項所述之方法，其中非晶性五 氧化一叙（Τ〜〇5 )薄膜，係同時注入定量之鈕（Ta )化合 物蒸氣與包括阿摩尼亞（Nh3 )與氧氣（〇2)的反應氣體於 LPCVD腔室中；上述LPCVD腔室維持在溫度3〇〇6〇(pc，且
    第16頁 483154 _ 案號 891234BA 年月日 修正 六、申請專利範圍 壓力小於10脫耳（torr )者。 1 2 ·如申請專利範圍第1丨項所述之方法，其中，所形 成之非晶性五氧化二鈕（Τ〜〇5)薄膜厚度介於5〇 —15〇A 者。 1 3 ·如申請專利範圍第丨丨項所述之方法，其中，鈕 (T a )化合物蒸氣之形成，係於蒸發器或蒸發管中，以一 定速率引入Ta(〇C2H5)溶液；其中蒸發器或蒸發管溫度維持 於150-200 C之間’而引入速率低於i〇〇mg/分鐘者。 1 4 ·如申請專利範圍第1項所述之方法，其中施予非晶 性五氧化二组（T a2 〇5 )薄膜之低溫加熱退火製程，係利用 臭氧或紫外線-臭氧（UV-〇3)於3 0 0 -50 0 °C溫度中進行 者。 1 5 ·如申請專利範圍第1項所述之方法’其中施予非晶 性五氧化二钽（Ta2〇5 )薄膜之高溫退火製程，係於充滿氧 化二氮（N20)、氧氣（〇2)、或氮氣（N2)，且溫度介於 6 50 -9 5 0 °C條件下的熔爐中進行5-30分鐘者。 1 6 ·如申請專利範圍第1項所述之方法，其中電容器之 上層電極之材質，係從包括氮化鈦（TiN )、氮化钽（TaN )、鎢（W )、石夕化鎢（w S i )、釕（Ru )、一氧化釕 (Ru02 ) 、Ir (銥）、二氧化銥（Ir02 )、鉑（PO 等中 選擇出者。 1 7 ·如申請專利範圍第1 β項所述之方法’其中電容器 之上層電極具有一疊層狀結構，藉由一聚合矽緩衝層覆蓋 於一金屬層上所構成者。
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CN1172360C (zh) 2004-10-20
US6410400B1 (en) 2002-06-25
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JP2001203338A (ja) 2001-07-27
GB2362033A (en) 2001-11-07
GB2362033B (en) 2004-05-19

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