CN1295341A - 采用Ta2O5薄膜作为电介质膜的Ta2O5电容器的制造方法 - Google Patents
采用Ta2O5薄膜作为电介质膜的Ta2O5电容器的制造方法 Download PDFInfo
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- 239000003990 capacitor Substances 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 title abstract 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 238000000137 annealing Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 30
- 239000007789 gas Substances 0.000 claims description 17
- 229910052757 nitrogen Inorganic materials 0.000 claims description 16
- 229910052760 oxygen Inorganic materials 0.000 claims description 11
- 238000001704 evaporation Methods 0.000 claims description 9
- 230000008020 evaporation Effects 0.000 claims description 8
- 239000011229 interlayer Substances 0.000 claims description 7
- 239000010410 layer Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 238000002425 crystallisation Methods 0.000 claims description 5
- 230000008025 crystallization Effects 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000010276 construction Methods 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 238000007669 thermal treatment Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- 239000010409 thin film Substances 0.000 abstract description 10
- 238000000151 deposition Methods 0.000 abstract 1
- 230000001546 nitrifying effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 70
- 150000004767 nitrides Chemical class 0.000 description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 239000001301 oxygen Substances 0.000 description 8
- 229910052799 carbon Inorganic materials 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 150000001721 carbon Chemical group 0.000 description 2
- -1 carbon chemical compound Chemical class 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000006227 byproduct Substances 0.000 description 1
- 150000001722 carbon compounds Chemical class 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000003411 electrode reaction Methods 0.000 description 1
- JVOQKOIQWNPOMI-UHFFFAOYSA-N ethanol;tantalum Chemical compound [Ta].CCO JVOQKOIQWNPOMI-UHFFFAOYSA-N 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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Abstract
一种半导体器件的电容器的制造方法,采用Ta2O5薄膜作为电介质膜,提高泄漏电流特性和介电特性。该方法包括以下工序:提供半导体衬底,其上形成有预定的下部图形,覆盖有层间绝缘膜;在所述层间绝缘膜上形成电容器下部电极;对所述下部电极表面进行氮化处理;在所述表面氮化处理后的下部电极上蒸镀非晶态Ta2O5薄膜作为电介质膜;依次进行针对所述非晶态Ta2O5薄膜的低温退火和高温退火;在由所述Ta2O5薄膜构成的电介质膜上形成电容器上部电极。
Description
本发明涉及半导体器件的电容器的制造方法，特别是涉及采用Ta2O5薄膜作为电介质膜的高容量Ta2O5电容器的制造方法。
众所周知，电容器在DRAM这样的存储器件中的作用，是作为存储数据的存储处使用的。所述电容器的结构是在下部电极和上部电极之间夹入电介质膜，其容量与电极表面积和电介质膜的介电常数成正比，而与电极间隔、也就是电介质膜厚度成反比。
扩大电极表面积，使用具有高介电常数的电介质膜、或减小电介质膜的厚度，可以增大所述电容器的容量。但是，由于减小所述电介质膜厚度的方式受到限制，所以以扩大电极表面积、或者使用高介电常数的电介质膜的方式，努力增大电容器的容量。
将电容器的下部电极形成为三维结构，具有半球(Hemi SphericalGrain：HSG)形状的表面，或者增大高度，由此扩大所述电极表面积。但是，难以形成具有三元结构或半球形表面的下部电极。而且，如果增大下部电极的高度，就会增大单元区域与周边电路区域之间的台阶，不能确保后续工序例如曝光工序时的焦点深度(DOF)，对集成工序有恶劣影响。
因此，制造高容量电容器的最近努力，主要是在开发高介电常数的电介质膜方向上进行。
作为一个例子，虽然以往采用氧化膜/氮化膜/氧化膜(ONO)结构的氮化膜作为电介质膜，但考虑容量增大的侧面，提出并采用氮化膜/氧化膜(NO)结构的氮化膜作为电介质膜。但是，由于所述NO结构的氮化膜的介电常数(ε)低至4～5左右，所以具有NO结构氮化膜作为电介质膜的NO电容器，难以适用于256M以上的第二代DRAM产品，因为这样的产品为了防止产生软错误和刷新时间缩短，要求具有25fF/单元以上的足够的容量。由此，提出了用具有25～27左右的高介电常数的Ta2O5薄膜代替NO结构的氮化膜。由于所述Ta2O5薄膜的介电常数比NO结构的氮化膜高很多，所以Ta2O5电容器易于适用做256M以上的第二代DRAM产品。
但是，由于以下理由，所述Ta2O5薄膜用作电介质膜存在着难度。
第一方面，由于所述Ta2O5薄膜的化学计量比(stoichiometry)不稳定，因Ta和O的组成比差，局部存在作为膜内泄漏电流原因起作用的氧空位状态的置换型Ta原子。因此，为了去除所述氧空位，在形成所述Ta2O5薄膜之后必须进行其他的氧化工序，由此导致工序复杂。
第二方面，所述Ta2O5薄膜的下部电极和上部电极的材料，由于是氧化反应性高的多晶硅或TiN，所以在后续热处理时，膜内存在的氧通过与所述电极的反应，在各个界面形成低介电的氧化层。因此，界面均匀性降低，结果电容器的电气特性劣化。
第三方面，所述Ta2O5薄膜中，通过作为Ta2O5的前驱物的乙醇钽(Ta(OC2H5)5)的有机物与O2或N2O气体反应，膜内存在碳原子和CH4、C2H4等碳化合物和水分(H2O)这样的杂质，这些杂质导致泄漏电流增大，使介电特性进一步劣化。
因此，本发明的目的在于提供一种Ta2O5电容器的制造方法，采用Ta2O5薄膜作为电介质膜，可省略用于去除薄膜内存在的氧空位的其他氧化工序。
本发明的另一目的在于提供一种Ta2O5电容器的制造方法，采用Ta2O5薄膜作为电介质膜，可以防止所述薄膜内存在的氧与电极之间反应而产生低介电氧化层。
本发明的又一目的在于提供一种Ta2O5电容器的制造方法，采用Ta2O5薄膜作为电介质膜，通过去除所述薄膜内存在的碳成分，可提高泄漏电流特性和介电特性。
为了实现上述目的，本发明的Ta2O5电容器的制造方法包括以下工序：提供半导体衬底，其上形成有预定的下部图形，覆盖有层间绝缘膜；在所述层间绝缘膜上形成电容器下部电极；对所述下部电极表面进行氮化处理；在所述表面氮化处理后的下部电极上蒸镀非晶态Ta2O5薄膜；对所述非晶态Ta2O5薄膜进行低温退火；为了获得作为电介质膜的结晶Ta2O5薄膜，对所述低温退火后的非晶态Ta2O5薄膜进行高温退火；在由所述结晶Ta2O5薄膜构成的电介质膜上形成上部电极。
附图的简要说明如下：
图1A～图1D是说明本发明的半导体器件电容器的制造方法的剖面图。
以下将参考图1A-图1D说明本发明的Ta2O5电容器的制造方法。
如图1A所示，提供形成有预定下部图形、即晶体管和电阻器等基本构造物(未示出)的半导体衬底1，在衬底1上形成层间绝缘膜2，覆盖所述构造物。采用公知工序在层间绝缘膜2上形成电容器的下部电极3，使其与衬底1的预定部分接触。所述下部电极3最好是由掺杂的多晶硅层形成，由此形成层叠结构。而且，所述下部电极3可以用选自TiN、TaN、W、WSi、Ru、RuO2、Ir、IrO2、Pt中的一种金属层形成，代替掺杂的多晶硅层。而且，所述下部电极3可以形成为具有圆筒形这样的三维结构和HSG形状表面，以便增大表面积。
如图1B所示，对下部电极3的表面进行氮化处理，结果在所述下部电极3表面和层间绝缘膜2上形成吸附氮原子的氮化膜4。为了防止后续形成Ta2O5薄膜或热处理时，所述下部电板3和Ta2O5薄膜的界面产生过氧化，进行所述氮化处理。
在NH3气体或N2/H2气体气氛的LPCVD室内，通过1～5分钟的等离子体放电，完成所述氮化处理。这时，衬底1的温度应维持在300～500℃。而且，可以在NH3气氛中、650～950℃温度下，利用快速热处理(RTP)进行退火，完成所述氮化处理。而且，也可以在NH3气氛中、500～1000℃温度下，通过炉内退火完成所述氮化处理。
为了提高电容器的性能，可以在所述氮化处理前，采用HF蒸汽或HF溶液进行清洗，其结果，下部电极3表面上产生的自然氧化膜(SiO2)被去除。而且，为了提高所述下部电极3的均匀性，可以在所述采用HF的清洗前后，采用NH4OH溶液或H2SO4溶液进行清洗。
在所述氮化处理后，可以在NO2或O2气氛中通过退火，进行微量氧化处理。在所述氮化处理之外增加进行所述微量氧化处理，可以更有效地抑制下部电极和Ta2O5薄膜的界面产生的过氧化。
另一方面，可以省略所述氮化处理。此时，在下部电极3上蒸镀5～30厚的氮化硅膜(Si3N4)，随后在所述氮化硅膜上紧接着连续蒸镀Ta2O5薄膜。
如图1C所示，在表面形成了氮化膜4的下部电极3上，按非晶状蒸镀作为电介质膜的Ta2O5薄膜5，之后通过依次进行的低温退火和高温退火，形成非晶态Ta2O5薄膜。
利用例如MFC(Mass Flow Controller)这样的流量调节器，向保持300～600℃温度和10乇以下压力的LPCVD室内，定量供给Ta化合物蒸汽和作为反应气体的NH3气体(10～1000sccm)或O2气体(10～300sccm)，作为下部电极3表面的表面化学反应结果，形成所述非晶态Ta2O5薄膜，厚度是50～150左右。利用MFC向蒸发器或蒸发管内，按100mg/分钟以下的定量供给99.999％以上的Ta(OC2H5)5溶液，蒸发获得所述Ta化合物蒸汽，之后通过供给管注入反应室内。此时，为了防止蒸发的气体冷凝，使含有小孔或喷嘴的蒸发器或蒸发管以及构成Ta蒸汽流路的供给管保持在150～200℃的温度。
按本地或非本地状态，采用O3或UV-O3在300～500℃的温度下，进行针对所述非晶Ta2O5薄膜的低温退火。所述低温退火的结果，除去了非晶Ta2O5薄膜内存在的置换型Ta原子、即氧空位，从而使所述非晶Ta2O5薄膜内存在的未结合碳原子被活性氧氧化，由此产生CO或CO2这样的挥发性碳化合物气体。
在N2O、O2或N2气体气氛的炉内，在650～950℃温度进行5～30分钟的高温退火，所述退火针对已进行所述低温退火的非晶Ta2O5薄膜。所述高温退火的结果，除去了非晶Ta2O5薄膜内作为反应副产物残留的挥发性碳化合物气体这样的杂质，由此使得非晶Ta2O5薄膜结晶化和致密化。
如图1D所示，在Ta2O5薄膜5上形成电容器上部电极6，由此制成本发明的Ta2O5电容器。所述上部电极6形成为金属层6a和缓冲层6b的层叠结构。这里，所述金属层6a由选自TiN、TaN、W、WSi、Ru、RuO2、Ir、IrO2、Pt中的一种金属形成，最好由TiN形成，其厚度是100～600左右。所述缓冲层6b由掺杂多晶硅层形成，以便防止电容器的电气特性因后续的热处理而劣化。
除此之外，本发明在不脱离其实质的范围内可作出多种变化实施。
如上所述，本发明的Ta2O5薄膜与已有技术相比，可以容易地去除膜内存在的氧空位和碳杂质，而且可以抑制上部和下部电极的氧化反应。由此，本发明Ta2O5电容器具有提高的泄漏电流特性和介电特性。本发明的Ta2O5电容器由于采用具有25～27介电常数的Ta2O5薄膜作为电介质，故可以获得高容量。
而且，下部电极即使形成为比较简单的层叠结构，也能获得充分的容量，由此可以使下部电极的形成工序简单化。结果，可以节省工序时间和生产成本。此外，由于可以省略针对Ta2O5薄膜的快速热处理和多阶段低温氧化工序，所以有利于降低成本和提高生产率。
Claims (17)
1．一种半导体器件的电容器制造方法，其特征在于，包括以下工序：
提供半导体衬底，其上形成有预定的下部图形，覆盖有层间绝缘膜；
在所述层间绝缘膜上形成电容器下部电极；
对所述下部电极表面进行氮化处理；
在所述表面氮化处理后的下部电极上蒸镀非晶态Ta2O5薄膜；
对所述非晶态Ta2O5薄膜进行低温退火；
为了获得作为电介质膜的结晶Ta2O5薄膜，对所述低温退火后的非晶态Ta2O5薄膜进行高温退火；
在由所述结晶Ta2O5薄膜构成的电介质膜上形成上部电极。
2．根据权利要求1的半导体器件的电容器的制造方法，其特征在于，所述下部电极由掺杂的多晶硅层形成。
3．根据权利要求1的半导体器件的电容器的制造方法，其特征在于，所述下部电极由选自TiN、TaN、W、WSi、Ru、RuO2、Ir、IrO2、Pt中的一种金属层形成。
4．根据权利要求1的半导体器件的电容器的制造方法，其特征在于，还包括在所述下部电极表面氮化处理工序之前，采用HF蒸汽或HF溶液清洗所述下部电极表面的工序。
5．根据权利要求4的半导体器件的电容器的制造方法，其特征在于，还包括在采用所述HF的清洗工序前或后，采用NH4OH溶液或H2SO4溶液清洗所述下部电极表面的工序。
6．根据权利要求1的半导体器件的电容器的制造方法，其特征在于，在NH3气体或N2/H2气体气氛的LPCVD室内，通过1～5分钟的等离子体放电，进行所述氮化处理。
7．根据权利要求6的半导体器件的电容器的制造方法，其特征在于，在所述半导体衬底温度保持在300～500℃的状态，进行所述氮化处理。
8．根据权利要求1的半导体器件的电容器的制造方法，其特征在于，在NH3气氛中、650～950℃温度下，利用快速热处理退火，进行所述氮化处理。
9．根据权利要求1的半导体器件的电容器的制造方法，其特征在于，在NH3气氛中、500～1000℃温度下，通过炉内退火进行所述氮化处理。
10．根据权利要求1的半导体器件的电容器的制造方法，其特征在于，还包括在所述下部电极表面氮化处理工序之后，在NO2或O2气氛中进行退火的工序。
11．根据权利要求1的半导体器件的电容器的制造方法，其特征在于，向保持300～600℃温度和10乇以下压力的LPCVD室内，定量供给Ta化合物蒸汽气体和作为反应气体的NH3气体或O2气体，形成所述非晶态Ta2O5。
12．根据权利要求11的半导体器件的电容器的制造方法，其特征在于，所述非晶态Ta2O5薄膜的厚度是50～150。
13．根据权利要求11的半导体器件的电容器的制造方法，其特征在于，向维持在150～200℃的蒸发器或蒸发管内，按100mg/分钟以下的定量供给Ta(OC2H5)溶液，生成所述Ta化合物蒸汽。
14．根据权利要求1的半导体器件的电容器的制造方法，其特征在于，采用O3或UV-O3在300～500℃的温度，进行针对所述非晶态Ta2O5薄膜的低温退火。
15．根据权利要求1的半导体器件的电容器的制造方法，其特征在于，在N2O、O2或N2气体气氛的炉内，在650～950℃温度进行5～30分钟的针对所述非晶态Ta2O5薄膜的高温退火。
16．根据权利要求1的半导体器件的电容器的制造方法，其特征在于，所述电容器的上部电极由选自TiN、TaN、W、WSi、Ru、RuO2、Ir、IrO2、Pt中的一种金属形成。
17．根据权利要求16的半导体器件的电容器的制造方法，其特征在于，所述电容器的上部电极由金属层和多晶硅材质的缓冲层的层叠结构构成。
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| DE (1) | DE10055450A1 (zh) |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7091541B2 (en) | 2003-07-08 | 2006-08-15 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device using a conductive film and method of manufacturing the same |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100421044B1 (ko) * | 2000-07-06 | 2004-03-04 | 삼성전자주식회사 | 반도체 메모리 소자의 커패시터 제조 방법 |
| KR100408410B1 (ko) * | 2001-05-31 | 2003-12-06 | 삼성전자주식회사 | 엠아이엠(ｍｉｍ) 커패시터를 갖는 반도체 소자 및 그제조 방법 |
| US7781819B2 (en) | 2001-05-31 | 2010-08-24 | Samsung Electronics Co., Ltd. | Semiconductor devices having a contact plug and fabrication methods thereof |
| KR100400252B1 (ko) * | 2001-06-29 | 2003-10-01 | 주식회사 하이닉스반도체 | 탄탈륨 옥사이드 캐퍼시터의 형성 방법 |
| KR101153978B1 (ko) * | 2002-03-26 | 2012-06-14 | 카부시키카이샤 시.브이.리서어치 | 비결정질 금속 산화막의 제조 방법 및 비결정질 금속산화막을 가지는 커패시턴스 소자와 반도체 장치를제조하는 방법 |
| KR100464649B1 (ko) * | 2002-04-23 | 2005-01-03 | 주식회사 하이닉스반도체 | 이중 유전막 구조를 가진 반도체소자의 캐패시터 및 그제조방법 |
| KR100540476B1 (ko) * | 2002-06-22 | 2006-01-10 | 주식회사 하이닉스반도체 | 반도체 소자의 캐패시터 제조방법 |
| KR100451516B1 (ko) * | 2002-06-28 | 2004-10-06 | 주식회사 하이닉스반도체 | 반도체 소자의 캐패시터 제조방법 |
| US20040115946A1 (en) * | 2002-12-16 | 2004-06-17 | Hall Lindsey H. | Use of a sulfuric acid clean to remove titanium fluoride nodules |
| KR100722997B1 (ko) * | 2003-06-30 | 2007-05-30 | 주식회사 하이닉스반도체 | 반도체 장치의 캐패시터 제조 방법 |
| KR101048890B1 (ko) * | 2004-12-01 | 2011-07-13 | 주식회사 하이닉스반도체 | 반도체 소자의 커패시터 형성 방법 |
| KR100695887B1 (ko) * | 2004-12-09 | 2007-03-20 | 삼성전자주식회사 | 티타늄질화막 형성 방법 및 상기 티타늄질화막을 이용한금속-절연체-금속 커패시터의 하부전극 형성 방법 |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57167669A (en) * | 1981-03-27 | 1982-10-15 | Fujitsu Ltd | Capacitor and manufacture thereof |
| JPH05121655A (ja) * | 1991-10-25 | 1993-05-18 | Nec Corp | 半導体装置の製造方法 |
| JPH06151751A (ja) * | 1992-11-13 | 1994-05-31 | Hitachi Ltd | 半導体集積回路装置及びその製造方法 |
| JP2679599B2 (ja) * | 1993-12-02 | 1997-11-19 | 日本電気株式会社 | 半導体装置の製造方法 |
| JPH07211791A (ja) * | 1994-01-17 | 1995-08-11 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
| US6104203A (en) * | 1995-05-16 | 2000-08-15 | Trio-Tech International | Test apparatus for electronic components |
| KR0155879B1 (ko) * | 1995-09-13 | 1998-12-01 | 김광호 | 오산화 이탄탈륨 유전막 커패시터 제조방법 |
| KR970018589A (ko) * | 1995-09-29 | 1997-04-30 | 김광호 | 반도체 메모리 장치의 커패시터 제조방법 |
| KR0165484B1 (ko) * | 1995-11-28 | 1999-02-01 | 김광호 | 탄탈륨산화막 증착 형성방법 및 그 장치 |
| US5930584A (en) * | 1996-04-10 | 1999-07-27 | United Microelectronics Corp. | Process for fabricating low leakage current electrode for LPCVD titanium oxide films |
| KR19980015749A (ko) * | 1996-08-23 | 1998-05-25 | 김광호 | 반도체 소자의 커패시터 제조방법 |
| JPH10247723A (ja) * | 1997-03-04 | 1998-09-14 | Oki Electric Ind Co Ltd | 半導体装置のキャパシタの製造方法 |
| DE19825736C2 (de) * | 1997-06-11 | 2003-09-18 | Hyundai Electronics Ind | Verfahren zum Bilden eines Kondensators einer Halbleitervorrichtung |
| FR2766211B1 (fr) * | 1997-07-15 | 1999-10-15 | France Telecom | PROCEDE DE DEPOT D'UNE COUCHE DIELECTRIQUE DE Ta2O5 |
| JPH11224938A (ja) * | 1997-12-04 | 1999-08-17 | Fujitsu Ltd | 半導体装置及びその製造方法 |
| KR100492901B1 (ko) * | 1997-12-27 | 2007-11-02 | 주식회사 하이닉스반도체 | 반도체장치의고유전체캐패시터제조방법 |
| US6162744A (en) * | 1998-02-28 | 2000-12-19 | Micron Technology, Inc. | Method of forming capacitors having high-K oxygen containing capacitor dielectric layers, method of processing high-K oxygen containing dielectric layers, method of forming a DRAM cell having having high-K oxygen containing capacitor dielectric layers |
| KR100328454B1 (ko) * | 1999-06-29 | 2002-03-16 | 박종섭 | 반도체 소자의 캐패시터 제조 방법 |
| KR100331270B1 (ko) * | 1999-07-01 | 2002-04-06 | 박종섭 | ＴａＯＮ박막을 갖는 커패시터 제조방법 |
| GB2358284B (en) * | 1999-07-02 | 2004-07-14 | Hyundai Electronics Ind | Method of manufacturing capacitor for semiconductor memory device |
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1999
- 1999-11-09 KR KR10-1999-0049503A patent/KR100373159B1/ko not_active IP Right Cessation
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- 2000-11-08 GB GB0027298A patent/GB2362033B/en not_active Expired - Fee Related
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7091541B2 (en) | 2003-07-08 | 2006-08-15 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device using a conductive film and method of manufacturing the same |
| CN1294655C (zh) * | 2003-07-08 | 2007-01-10 | 松下电器产业株式会社 | 半导体器件及其制造方法 |
| US7244982B2 (en) | 2003-07-08 | 2007-07-17 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device using a conductive film and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
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| GB0027298D0 (en) | 2000-12-27 |
| KR100373159B1 (ko) | 2003-02-25 |
| JP2001203338A (ja) | 2001-07-27 |
| GB2362033A (en) | 2001-11-07 |
| TW483154B (en) | 2002-04-11 |
| US6410400B1 (en) | 2002-06-25 |
| GB2362033B (en) | 2004-05-19 |
| CN1172360C (zh) | 2004-10-20 |
| KR20010045962A (ko) | 2001-06-05 |
| DE10055450A1 (de) | 2001-05-10 |
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