TW478165B - Semiconductor element and its production method - Google Patents

Semiconductor element and its production method Download PDF

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Publication number
TW478165B
TW478165B TW089100324A TW89100324A TW478165B TW 478165 B TW478165 B TW 478165B TW 089100324 A TW089100324 A TW 089100324A TW 89100324 A TW89100324 A TW 89100324A TW 478165 B TW478165 B TW 478165B
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Taiwan
Prior art keywords
layer
tungsten
tungsten oxide
semiconductor device
oxide layer
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TW089100324A
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English (en)
Inventor
Martin Schrems
Dirk Drescher
Helmut Wurzer
Helmut Tews
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Infineon Technologies Ag
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Publication of TW478165B publication Critical patent/TW478165B/zh

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    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Inorganic Compounds Of Heavy Metals (AREA)
  • Physical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

478165 κι ____ 五、發明說明（I ) (請先閱讀背面之注意事項再填寫本頁) 本發明係關於一種半導體組件及其製造方法，特別是 有關一種半導體組件，其具有場效電晶體之閘極介電質 及/或具有一種在記憶胞中之所謂〃儲存式節點介電質 (storage node dielectrikum) ” 。 爲了保持或提高國際上之競爭力，則須使此種達成指 定之電子式功能所需之成本持續地下降且因此可持續地 提咼生產力。近年來生產力之提高所需之保證是CMOS 技術或DRAM技術。此二種技術是藉由使結構持續地變 小而使生產力提f。 經濟部智慧財產局員工消費合作社印製 但MO S電晶體之結構持續地變小會帶來以下問題：爲 了有效地控制電晶體，通常須使用一些較閘極介電質還 薄之介電層。若像目前一般情況一樣使用二氧化矽作爲 •閘極介電質，則閘極介電質之層厚度在使用0.1 // m技術 時必須較1 · 5 // m還小。但以足夠之精確度可再生性地製 造此種薄的二氧化矽層是很困難的。只有0. 1 μ m之差異 即表示層厚度之變動是在10%之數量級（order)中。此外， 在此種薄的二氧化矽層中會造成一些流經二氧化矽層之 漏電流，這是因爲由於量子力學之穿透(tunnel)效應而使 電荷載體可克服這些由二氧化矽層所產生之位障。 在發展高積體式記憶體組件時，各別記憶胞之晶胞 (cell)電容儘管持續性之小型化仍須保持其電容量或更加 改良而提高。爲了達成此一目的，同樣亦須使用一些薄 的介電層，通常是氧化矽層或氧化物-氮化物-氧化物層 (0N0)以及使用折疊式電容器電極（溝渠式晶胞，堆疊晶 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 478165 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（）） 胞）。但在使記憶體介電質之厚度降低時亦會大大地提高 此種流經介電質之電流。 因此建議由具有較高介電常數（ε ,.)之材料來取代一般 之二氧化矽層或氧化物-氮化物-氧化物層。利用此種材 料，則可使用較厚之大於5nm之層來作爲閘極介電質或 記憶體介電質，但這些層在電性上對應於厚度較5nm小 很多之二氧化矽層。此種層之厚度較容易控制而可大大 地降低流經此層之隧道電流。 例如可使用氧化鈦或五氧化鉅或使用由氧化物/氧化 鈦或氧化物/五氧化鉅所構成之層堆疊來用作閘極介電 質之材料。記憶體介電質用之材料例如可選擇鈦酸緦鋇 (BST，（Ba，Sr)Ti03)、鈦酸鉛銷（PZT，Pb(Zr，Ti))或以鑭來摻 雜之鈦酸鉛锆或JS酸緦鉍（SBT，SrBi 2Ta 20 9)。 可惜這些材料就其這些新的應用而言具有一系列之 缺點。因此爲了製造一種由氧化鈦或五氧化鉬所構成之 閘極介電質通常是使用CV：b製程。但這樣所製成之各層 具有一些污點，這些污點是來自CVD方法中所使用之程 序氣體。這些污點會在各層中形成電荷以及所謂〃截取 (traps)〃，這些都會對電晶體之功能有不良影響。此外， 這些層或層堆疊通常不會使介電常數（ε ')提升至足夠 大。 在可用作記憶體介電質之一些新材料中，已證實這些 材料不易以化學方式來蝕刻或不可蝕刻，其中此種蝕刻 去除作用（在使用〃活性（r e a c t i ν e) 〃氣體時）主要是或 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------------訂---r------線 (請先閱讀背面之注意事項再填寫本頁) 478165 經濟部智慧財產局員工消費合作社印製 κι ______Β7 _ 五、發明說明（3 ) 幾乎只與此種蝕刻之物理成份有關。由於此種蝕刻具有 較少之化學成份或不具備化學成份，則即將結構化之層 之飩刻侵蝕是與遮罩或基層（蝕刻停止層）之蝕刻侵蝕 處於同一個數量級中，即，相對於蝕刻遮罩或基層之蝕 刻選擇性通常是很小的（介於0.3和3 · 0之間）。這樣所 造成之結果是：由於遮罩之腐蝕以及遮罩上傾斜之/側面 及不可避免的多角形平，面之形成（斜切，變細），因此只 能確保此結構化有很小之尺寸精確性。此種多角形平面 因此會限制：此種在結構化時所可達成之最小之結構大 小以及在即將結構化之各層中側面輪廓（pro file)之可達 成之斜度。 此外，爲了製成BST層、PZT層或SBT層，則複雜且 •昂貴之沈積方法以及不易處理之一些位障層（例如，鉑 或釕）是需要的。取決於所缺乏之熱穩定性條件，則B S T 層另外亦可不用於所謂〃深溝渠電容器〃中。 本發明之目的是提供一種半導組件及其製造方法，其 可避免上述問題或大大地減小上述之問題。此目的是藉 由申請專利範圍第1項之半導體組件及第8、9以及1 5 項之方法來達成。 本發明有利之其它實施形式、構造和外觀敘述在說明 書中申請專利範圍各附屬項中及所附之圖式中。 依據本發明，須製備一種半導體組件，其具有至少一 種由氧化鎢（wo A,)所構成之已結構化之層。本發明之半導 體組件之特徵是：氧化鎢（WOj層之相對介電常數（£ ,.) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------------訂---Γ------線 (請先閱讀背面之注音心事項再填寫本頁) ^165 A7 B7 1、發明說明（Η ) 較50大。 本發明之半導體組件具有之優點是：非常大之相對介 電辱數（ε ,.)能以較簡易之方式以氧化鎢（wΟ 層（例 如，X= 2-3 )來產生。本發明之半導體組件所具有之其 它優點是：目前在半導體技術中所使用之設備同樣可用 來產生氧化鎢層（WO A,)。不必使用特殊可調整之昂貴之設 備。產生氧化鎢層（WO /)所用之鎢只會少量地擴散至矽 中，因此在本發明之半導體組件中只有很小之污染危險 性。但使用氧化鎢層（WO A〇不是只限於矽技術中，這些層 亦可用在其它半導體（例如，GaAs)中。 較佳是使用氧化鎢層（WO J作爲記憶體-、閘極-、隧道 -或STI-襯墊-介電質。 •此外，氧化鎢層之相對介電常數’（ε J較1 0 0大是有利 的，特別是大於1 5 0時。 依據本發明之其它形式，此種半導體組件具有至少一 種由含有鎢之層及氧化鎢層（WOj所構成之層堆疊，情況 需要時亦可具有一種由含有鎢之層及氧化鎢層（woy所 構成之已結構化之層堆疊。 此外，較佳是此種半導體組件具有至少一種由氧化鎢 層（WO x)和至少一層位障層所構成之層堆疊，情況需要時 亦可具有一種由氧化鎢層（WO 和至少一層位障層所構 成之已結構化之層堆疊。 較佳是此種含鎢很多之層由鎢、矽化鎢或氮化鎢所構 成。 本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公釐） (請先閱讀背面之注音？事項再填寫本頁) # 訂-ΙΊ------線· 經濟部智慧財產局員工消費合作社印製 478165 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（5 ) 此外，位障層較佳是由氧化矽、氮化矽、氧化氮、氮 化鎢或氮化鈦所構成。 依據本發明，其亦提供此種半導體組件（其具有氧化 鎢層）之製造方法。本發明之方法具有以下之各步驟爲 其藏徵： (a) 製備一種含有鎢之層， (b) 此種含有鎢之層是在一種含氧之大氣中進行熱氧 化， (c) 此種由氧化鎢構成之層在溫度5 5 0至1 1 〇〇°C之間， 較佳是700至1 100 °C之間，受到一種熱處理，使此 種由氧化鎢（WO x)所構成之層所具有之相對介電常 數（ε ,.)較J0還大。 •依據本發明，另外亦提供一種半導體組件（其具有氧 化鎢層）之製造方法。本發明之方法之特徵是以下各步 驟： (a) 製備一種含有鎢之層， (b) 此種含有鎢之層是在一種含氧之大氣中進行熱氧 化，以便產生一種由氧化鎢（WO x)所構成之層，其相 對介電常數（ε r)較50還大。 較佳是使用一種由鎢、矽化鎢或氮化鎢所構成之層以作 爲含鎢之層。 此外，此種含鎢之層以CVD方法或PVD方法來製成是 有利的。 此種含鎢之層較佳是在5 0 0至1 2 00 °C之溫度中進行熱 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------------訂---1------線 (請先閱讀背面之注意事項再填寫本頁) 478165 A7 B7 五、發明說明（b ) 氧化作用。 依據本發明之其它實施形式，在熱氧化作用之後此種 由氧化鎢（WO A,)所構成之層在5 5 0至1 1 00 °C之間的溫度 (較佳是700至1100 °C )中受到一種熱處理。此種熱處 理較佳是在一種鈍性之大氣中進行。 此外，本發明亦提供此種半導體組件（其具有一種氧 化鎢層）之其它製造方法。本發明之方法之特徵是以下 各步驟： (a) 製備此種半導體組件之表面； (b) 氟化鎢和水在氣體形式之狀態中引導至此表面而產 生一種由氧化鎢（W Ο A.)所構成之層。 此種由氧化鎢（WO 所構成之層較佳是在5 5 0至1 100 •°C之間（較佳是在700至1 100°C之間）的溫度中受到一 種熱處理。特別有利的是此種處理是在一種鈍性之大氣 中進行。 氧化鎢層例如可較鐵電層或鉑層大大地更容易k結構 化。這些氧化鎢層在一般之結構化方法中基本上只可藉 由物理性之蝕刻成份來蝕刻且因此相對於其它層而言只 具有很小之選擇性。因此， 本發明之另一目的是提供一種已結構化之氧化鎢層之 製造方法。此目的是由申請專利範圍第1 8項之方法來達 成。 本發明提供一種已結構化之氧化鎢層之製造方法。本 發明之方法之特徵是以下各步驟： 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) # 訂——τ------線· 經濟部智慧財產局員工消費合作社印製 |0· 1. 爹正 & W補充 五、發明說明（7) (a) 製備一種氧化鎢層， (b) 在氧化鎢層上施加一種遮罩， (c )對應於此遮罩在氧化用之大氣中在溫度大於1 3 〇 π時對 該氧化鎢層進行乾式蝕刻，該氧化用之大氣具有至少一 種鹵素化合物，特別是CF4。 本發明之方法所具有之優點是：氧化鎢層基本上能以化學 成份（即，不具備物理性蝕刻成份）而被乾式蝕刻。因此， 本發明之方法相對於其它材料（例如，矽或氧化矽）而言具
I 有一種很高之選擇性。 此種氧化鎢層較佳是依據申請專利範圍第8至16項中任一 項之方法來產生。 此外，遮罩是一種多晶矽時是有利的。 蝕刻溫度介於20 0 °C和300 °C之間（特別是大約2 50 °C )時 亦是有利的。特別有利的是：氧化用之大氣中之鹵素化合物 之成份是介於1至10%之間。 本發明以下將依據圖式來詳述。圖式簡單說明如下： 第1至4圖本發明之方法之實施形式之圖解。 第5至6圖本發明之方法的另一實施形式之圖解。 第7圖矽基板1上由導電性氮化鎢層2，氧化鎢層3 '和導 電性氮化鎢層4所構成之層堆疊。 第1圖是具有矽基板1之矽晶圓之一部份。第1圖中所示 之矽晶圓之狀態例如對應於矽晶圓在標準CMOS製程中在各別 之電晶體之隔離區（未圖示）及CMOS電晶體之井狀區已產生 之後所具有之狀態。 在矽基板1之表面上現在施加一種大約1至5ηπι厚之 二氧化矽層2以作爲位障層。此種氧化層2例如可藉由 478165— A7 B7__ 五、發明說明（S ) (請先閱讀背面之注意事項再填寫本頁) 熱氧化作用而產生。若熱氧化作用是在大氣中（其另外 含有NO分子或N 20分子）進行，則可製成一種氮化之 二氧化矽層2。二氧化矽層2具有一種很低之〃截取點 (Trap)〃密度，這對即將產生之電晶體之功能有良好之作 用。 如本說明書中之導言所述，準確地控制此種薄的氧化 層之厚度是困難的。但由於此種氧化層只是產生此種真 正閘極介電質所需要的一種先前階段而已，此種氧化層2 之層厚度之變動是可承受的而不會對即將產生之電晶體 之功能有不良之影響。 然後在氧化層2上施加一種含鎢之層3。此種含鎢之層 3可以是一種純鎢層、氮化鎢層或矽化鎢層。此種含鎢之 層3例如可藉由濺鍍程序（PVD方法）或CVD方法來產 生。 若使用CVD方法，則可追溯到下述一.系列之方法： C V D W (在矽上，非選擇性） 例如WF6+SiH4 —W +氣體（胚層） WF6+H2 — W +氣體（散裝（bulk)層） 經濟部智慧財產局員工消費合作社印製 CVD W (在矽上，選擇性地對氮化物、氧化物）： 例如 2WF63 Si->2W + 3(SiH4) (此種方法描述在 R.V· Joshi et al·，in J. Appl. Phsy. 71(3) Feb. 1，1 992，pp. 1 42 8 中） 例如WF6+H2— w +氣體 C V D W S i A,: -1 〇- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 478165
i PI 年月日二D、 A7 五、發明說明Μ ) 例如 WF 6+SiH 2C1 2— WSi (例如，X = 2-3 ) +氣體 (同樣描述在 R.V. Joshi et al.，in J. Appl. Phsy. 7 1 (3) Feb. 1，1 992，pp.1 42 8 中）。 CVD WN (氮化鎢，例如，W 2N ): 例如 4WF6 + N2 + 12H2 (電漿 CVD) — 4W2N + 24(HF) (例如，在3 5 0-4 00 °C之溫度時）。 這樣所產生之含鎢之層3之層厚度大約是10至20n m。 這樣所產生之情況顯示在第2圖中。 然後此種含鎢之層3藉由熱氧化作用而轉換成氧化鎢 層3’。此種轉換是在含氧之大氣（例如，〇2或H20)中 在5 0 0至1 200 °C之溫度中進行。在使用一種純鎢層或使 用一種矽化鎢層時，溫度不可超過大約600 °C或須進行一 種所謂 ’’low thermal budget” RT0(Rapid Thermal Oxidation)，以便防止矽擴散至此種含鎢之層3中且可防 止此種含鎢之層3被氧化。 此種含鎢之層3之熱氧化作用會造成一種氧化鎢層 3’，其幾乎不會有污染且具有較50還大之相對介常數（ε ,.)。因此須選取這些層和製程參數，使此種含鎢之層3 完全轉換成氧化鎢層3 ’或此種含鎢之層3之一部份不會 被氧化。 藉由隨後在大約5 5 0至Π 0 0 °C之溫度中在一種鈍性之 大氣中進行熱處理，則可在一種晶體相位中或燒結（s i n t e r) 相位（例如，一些具有斜方對稱或四邊形對稱之相位） 中產生一種氧化鎢層3 ’（ W Ο Λ,，例如X = 2 - 3 )。此種熱處 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公f ) ------------#裝 (請先閱讀背面之注意事項再填寫本頁) 訂---一------線· 經濟部智慧財產局員工消費合作社印製 ^165 ^165 經濟部智慧財產局員工消費合作社印製 A7 B7 1、發明說明（i。） 理可直接涉及氧化鎢層3 ’之產生。但其亦可在稍後之i 程步驟中在製造積體電路時進行。 第3圖所示之層堆疊可良好地應用在MOS電晶體中， 這是因爲二氧化矽層2 (位障層）具有非常小之截取點密 度，已如上所述。就記憶體介電質而言這並非必需的， 其因此亦可不必用在二氧化矽層2中。含有很多鎢之層3 之在熱氧化作用之後仍可能殘留之其餘部份（例如，氮 化鎢）則承擔了一種（導電性）位障層之功能。以此種 方式可以一種簡易且省成本之製程來達成一種很高之電 容。在矽基板1上由導電性氮化鎢層2 (位障層和下電 極），氧化鎢層3 ’和導電性氮化鎢層4 (上電極）所構成 之相對應之層堆疊顯示在第7圖中。 .然後在氧化鎢層V上產生一種導電層4，由此而產生之 情況顯示在第3圖中。但依據所使用之製程在導電層4 之前可沈積另一層位障層（例如，氮化鎢層，未顯示）。 導電層4例如可形成Μ 0 S電晶體之閘極電極且通常是由 摻雜之多晶矽所構成。 然後進行一種光電技術，其中須對多晶矽層4進行結 構化以便產生閘極軌5。閘極軌5又可形成一種遮罩以便 作爲隨後對氧化鎢層3’之蝕刻用。可使用一種〇?4和〇2 所構成之混合物以作爲蝕刻氣體。蝕刻時之溫度大約是 25 0 °C。此蝕刻氣體因此是藉由高頻（HF)耦合輸入或微波 激發而受到驅動以形成一種電漿。C F 4對〇 2之比例大約 是2%至9 8%。 -12· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） ------ ---------— II--訂·---------線 (請先閱讀背面之注意事項再填寫本頁) 478165 A7 B7 五、發明說明（u) π讀失閱讀背面之注意事項再填寫本頁) 此種成爲游離之氟以及氧化鎢之與此種氟因此而成爲 相連接之此種反應解釋了蝕刻本身之現象。因此形成了 揮發性鎢-氟化合物。氧承擔了作爲（多晶）矽用之鈍化 物之任務。藉由氧而形成SiO 2，其鍵結能量（不使用額 外之離子能量）太高以致於不能藉由很少之氟成份來作 重大之蝕刻。氧化鎢層之鈾刻因此須高選擇性地對（多 晶）矽或氧化矽來進行。這樣所造成之情況顯示在第4 圖中。 製造電晶體所用之製程可依據標準CMOS方法繼續進 行，以便產生完整之電晶體。這些步驟都已爲人所知， 因此不必再說明。 第5圖是矽晶圓（其具有矽基板1 )之一部份。矽晶圓 .在第5圖中所示之狀態對應於矽晶圓在標準CMOS製程 中在各別之電晶體之隔離區（未顯示）及CMOS電晶體 之井狀區產生之後所具有之狀態。 經濟部智慧財產局員工消費合作社印製 然後在矽基板1上直接施加一種氧化鎢層3 ’。此種氧 化鎢層3’藉由CVD方法而產生。氟化鎢和水因此在氣體 形式之狀態中引導至基板表面以作爲先質（precurson): 2WF6 + 4H20->(W0F4) + W0 + (HF)或 WF6+H20 + Si— W-0 + (2HF) + (SiH4) 這樣可沈積一種大約2至2 0 n m厚之氧化鎢層3 ’。 隨後在大約5 5 0至1 10CTC之溫度中在鈍性之大氣中進 行熱處理，則可在晶體相位或燒結相位（例如，具有斜 方對稱或四邊形對稱之各種相位）中產生一種氧化鎢層3， -13- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 478165 A7 __B7__五、發明說明（A ) (WO π，例如X二2-3 )。此種熱處理可直接涉及氧化鎢層 3 ’之產生。但此種熱處理亦可在稍後之製程步驟中在製造 積體電路時進行。這樣所產生之情況顯示在第5圖中。 然後在氧化鎢層3 ’上產生一種導電層，但依據所使用 之製程亦可在導電層之前沈積另一個位障層（例如，氮 化鎢層，未顯示）。此導電層和氧化鎢層3 '又可像第4圖 所述一樣被結構化。這樣所造成之情況顯示在第6圖中。 符號說明 1…政基板 2…二氧化砂層 3…含鎢之層 3’…氧化鎢層 .4…導電性氮化鎢層 5…閘極軌 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -1 4 - — — — — — — II I I -I — — — — — —Αν— I I I I I — — — — — — — — — — — — — 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）

Claims (1)

  1. 478165
    六、申請專利範圍 第89100324號「半導體組件及其製造方法」專利案 (90年9月修正） 申請專利範圍 1. 一種半導體組件，其具有至少一層由氧化鎢（31)所構成之 層，其特徵爲：此氧化鎢層（3’）之相對介電常數（ε τ)大於 50 ° 2. 如申請專利範圍第1項之半導體組件，其中該氧化鎢層（3’） 用作記憶體-、閘極-、隧道-或STI-襯墊-介電質。 * 3. 如申請專利範圍第1或第2項之半導體組件，其中該氧 化鎢層（3’）之相對介電常數（ε τ)大於100，特別是大於 150 ° 4. 如申請專利範圍第1或第2項之半導體組件，其中該半 導體組件具有至少一個由含鎢之層（3)和一個氧化鎢層（3·) 所構成之層堆疊。 5. 如申請專利範圍第1或第2項之半導體組件，其中該半 導體組件具有至少一個由氧化鎢層（3，）和至少一個位障層 (2)所構成之層堆疊。 6_如申請專利範圍第4項之半導體組件，其中該含鎢很多 之層（3)是由鎢、矽化鎢或氮化鎢所構成。 7·如申請專利範圍第5項之半導體組件，其中該位障層（2) 是由氧化矽、氮化矽、氧氮化物、氮化鎢或氮化鈦所構 成。 ，、 8· —種半導體組件之製造方法，該半導體組件具有氧化鎢 層’此製is方法之特徵是以下各步驟： 478165 六、申請專利範圍 (a) 製備一種含有鎢之層， (b) 此含有鎢之層是在含氧之大氣中進行熱氧化，以便產 生一種由氧化鎢（W0X)所構成之層，其相對介電常數 U r)大於5 0。 9. 一種半導體組件之製造方法，該半導體組件具有氧化鎢 層，此製造方法之特徵是以下各步驟： (a) 製備一種含有鎢之層， (b) 此含鎢之層是在含氧之大氣中進行熱氧化， (c) 此種由氧化鎢所構成之層在550至llOOt之間的溫度 (較佳是在700至1100°C)時受到一種熱處理，以便 產生一種由氧化鎢（WOx)所構成之層，其相對介電常數 (ε r)大於 50。 10. 如申請專利範圍第8或第9項之方法，其中使用一種由 鎢、矽化鎢或氮化鎢所構成之層作爲該含鎢之層。 11. 如申請專利範圍第8或第9項之方法，其中該含鎢之層 是以CVD方法或PVD方法製成。 12·如申請專利範圍第8或第9項之方法，其中該含鎢之層 在溫度500至1 200°C時進行熱氧化。 这如申請專利範圍第8或第9項之方法，其中在熱氧化之 後此種由氧化鎢（W〇x)所構成之層在溫度550至1100°C(較 佳是在700至ll〇〇°C)時受到一種熱處理。 14·如申請專利範圍第9項之方法，其中熱處理是在鈍性之 大氣中進行。 15.如申請專利範圍第1 3項之方法，其中熱處理是在鈍性 478165 、申請專利範圍 之大氣中進行。 16. —種半導體組件之製造方法，該半導體組件具有氧化鎢 層’此製造方法之特徵是以下各步驟： (a) 製備此種半導體組件之表面； (b) 氟化鎢和水以氣體形式之狀態而被傳送至該表面上， 以便產生一種由氧化鎢（W0X)所構成之層。 17·如申請專利範圍第16項之方法，其中此種由氧化鎢（w〇x) 所構成之層在溫度介於550至1100 °C (較佳是在700至 1100°C)時受到一種熱處理。 18. 如申請專利範圍第17項之方法，其中熱處理是在一種鈍 性之大氣中進行。 19. 一種已結構化之氧化鎢層之製造方法，其特徵是以下各 步驟： (a) 製備一種氧化鎢層， (b) 在此氧化鎢層上施加一種遮罩， (c) 此氧化鎢層在氧化用之大氣中在溫度大於130°C時對應 於遮罩以乾燥方式而被蝕刻，其中該氧化用之大氣具 有至少一種鹵素化合物（特別是CF4 )。 2〇.如申請專利範圍第1 9項之方法，其中該氧化鎢層是依據 申請專利範圍第8至18項中任一項之方法而產生。 21.如申請專利範圍第19或20項之方法，其中該遮罩是一 種多晶矽遮罩。 22如申請專利範圍第19或20項之方法，其中該蝕刻溫度 是介於200°C和300°C之間，特別是大約250°C。 478165 六、申請專利範圍 23.如申請專利範圍第19項之方法，其中該氧化用之大氣中 之鹵素化合物成份是在1至10%之間。 -4-
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