WO2024065881A1 - 具有超高介电常数和/或铁电剩余极化强度的介质薄膜和器件的制备方法及器件 - Google Patents

具有超高介电常数和/或铁电剩余极化强度的介质薄膜和器件的制备方法及器件 Download PDF

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WO2024065881A1
WO2024065881A1 PCT/CN2022/124854 CN2022124854W WO2024065881A1 WO 2024065881 A1 WO2024065881 A1 WO 2024065881A1 CN 2022124854 W CN2022124854 W CN 2022124854W WO 2024065881 A1 WO2024065881 A1 WO 2024065881A1
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dielectric constant
film
dielectric film
ultra
ferroelectric
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江安全
张文笛
江钧
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复旦大学
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G11/00—Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors; Processes for the manufacture thereof or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G11/00—Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors; Processes for the manufacture thereof or of parts thereof
    • H01G11/84—Processes for the manufacture of hybrid or EDL capacitors, or components thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes

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  • the present invention belongs to the technical field of microelectronics and solid-state electronics, and relates to High-k dielectric materials, and in particular to a method for preparing a dielectric film and device having an ultra-high dielectric constant and/or ferroelectric residual polarization strength, and a device.
  • DRAM dynamic random access memory
  • CMOS complementary metal oxide semiconductor logic devices
  • advantages such as fast read and write speed ( ⁇ 20ns) and high read and write times (>10 15 ).
  • the lateral size reduction of DRAM storage cells has approached the process limit of 12nm, and further reduction requires revolutionary changes in the physical properties of storage materials. Therefore, it is necessary to develop new storage dielectric materials with higher dielectric constants (k) in order to store enough charge in small storage cells at technology nodes below 10nm for reliable bit operations of read and write circuits.
  • ZrO2 / Al2O3 / ZrO2 (ZAZ) dielectric layers with three- dimensional capacitor structures are used as high-k materials.
  • EOT 3.9/k ⁇ tphy
  • tphy is the physical thickness of the film
  • the EOT value of storage materials such as TiO2 and SrTiO3 can be reduced to However, it has a low bandgap and therefore suffers from high leakage current, which increases as device size decreases.
  • HZO Hf1- xZrxO2 , 0 ⁇ x ⁇ 1 ultra-thin film ( ⁇ 2nm) as a gate dielectric material has a high dielectric constant ( ⁇ 52), which can reduce EOT ( ⁇ 0.65nm) and suppress the short channel effect of CMOS nanodevices, reduce leakage current, and reduce the threshold voltage to 0.55V and the operating voltage to 1.6V [Cheema, SSet al., Nature 580, 478–482 (2020)], greatly improving the miniaturization of CMOS devices.
  • HZO crystalline thin film materials include monoclinic phase (M phase, space group: P2 1 /c), tetragonal phase (T phase, space group: P4 2 /nmc) and orthorhombic phase (O phase, space group: P ca 2 1 ), among which M phase is the most stable phase at room temperature, T phase is a high temperature phase, and O phase is considered to be a ferroelectric phase.
  • M phase is the most stable phase at room temperature
  • T phase is a high temperature phase
  • O phase is considered to be a ferroelectric phase.
  • HZO polycrystalline thin film is a mixture of M, T and O phases, with ferroelectric (FE) or antiferroelectric (AFE) properties at room temperature, and the dielectric constant generally varies in the range of 16-70.
  • HZO crystal films have ferroelectric remanent polarization ( ⁇ 20 ⁇ C/cm 2 ), which can be applied to non-volatile ferroelectric memory.
  • ferroelectric remanent polarization ⁇ 20 ⁇ C/cm 2
  • the larger the ferroelectric remanent polarization the smaller the memory cell size can be made, and the higher the storage density.
  • the dielectric constant of the current HZO crystal thin film has not reached an ultra-high dielectric constant of more than 100, and the ferroelectric remanent polarization intensity generally does not exceed 40 ⁇ C/cm 2 .
  • the purpose of the present invention is to solve the problems of low dielectric constant, low ferroelectric remanent polarization, low device unit size and high leakage current of the current high-k dielectric film, and to provide a method for preparing a dielectric film and device with ultra-high dielectric constant and/or ferroelectric remanent polarization and a device, wherein the highest dielectric constant and ferroelectric remanent polarization can be greater than 921 and 404 ⁇ C/cm 2 respectively, the information storage density is high, and the compatibility with CMOS integration process is good.
  • the present invention provides a method for preparing a dielectric film and a device having an ultra-high dielectric constant and/or ferroelectric remanent polarization, comprising:
  • Step a forming a dielectric film on a substrate or on a substrate with a second electrode; the dielectric film comprises a Hf1- xZrxO2 film, which is a crystalline or amorphous film; wherein 0 ⁇ x ⁇ 1;
  • Step b forming a first electrode on the dielectric film
  • Step c dividing the first electrode into a plurality of discrete microstructures, each microstructure having a lateral dimension of 1 nm to 50 ⁇ m;
  • Step d annealing treatment, so that the low dielectric constant phase in the dielectric film is reduced, the high dielectric constant phase is increased, and the average dielectric constant of the dielectric film is greater than 100.
  • step b and/or after step c active ions are implanted into the dielectric film.
  • the active ions include any one or more of carbon, nitrogen, oxygen, boron, helium, phosphorus, iron, aluminum, zinc, cobalt, tin, nickel, titanium, silicon, phosphorus, argon, chlorine, bromine, sulfur, iodine, fluorine, hydrogen, silver, gold, copper, and platinum; and the implantation dose of the active ions is 10 10 -10 20 ions/cm 2 .
  • the dielectric film is further divided into discrete microstructures.
  • the segmentation comprises etching.
  • a lateral dimension of each microstructure is 1 nm to 1 ⁇ m.
  • the annealing treatment temperature is 300° C. to 900° C.
  • the annealing treatment time is 1 second to 8 hours.
  • the method further comprises: applying positive and negative electric pulses to the device after the annealing treatment.
  • the dielectric film has a thickness of 0.5 nm to 50 nm.
  • the Hf1 - xZrxO2 film is further doped with at least one of Si , Er, Y and Al elements, with a doping concentration of 0-50 mol%.
  • the preparation method of the Hf1 - xZrxO2 thin film comprises at least one of a sol-gel method, a sputtering deposition method, a pulsed laser deposition method, a metal organic chemical vapor deposition method, an atomic layer deposition method, and an ion beam evaporation method.
  • the dielectric film further comprises: a low-k dielectric material layer, and the low-k dielectric material layer is stacked with the Hf1 - xZrxO2 film for use.
  • the method further comprises: processing the device after the annealing treatment, removing the first electrode and the substrate, and obtaining a dielectric film with an ultra-high dielectric constant and/or ferroelectric remanent polarization strength.
  • the present invention also provides a device prepared by the above-mentioned preparation method, characterized in that the device comprises: a substrate or a substrate with a second electrode, a dielectric film, and a first electrode;
  • the dielectric film comprises a Hf 1-x Zr x O 2 film, which is a crystalline or amorphous film; wherein 0 ⁇ x ⁇ 1;
  • the first electrode includes a plurality of discrete microstructures, or the first electrode and the dielectric film both include a plurality of discrete microstructures; the lateral size of each microstructure is 1 nm to 50 ⁇ m.
  • the device includes: any one or more of: a supercapacitor, a CMOS device, a dynamic random read/write memory (DRAM), a charge capture memory device, a three-dimensional stacked flash memory (3D NAND), and a non-volatile ferroelectric memory (FRAM or FeFET).
  • a supercapacitor a CMOS device
  • DRAM dynamic random read/write memory
  • charge capture memory device a three-dimensional stacked flash memory (3D NAND), and a non-volatile ferroelectric memory (FRAM or FeFET).
  • FRAM or FeFET non-volatile ferroelectric memory
  • the HZO film in the present invention exhibits a high dielectric constant (greater than 100) as the size of the first electrode is reduced after ion implantation and rapid annealing, which can significantly reduce EOT, and the storage charge capacity can be increased by at least 10 times at the same size.
  • the thickness of the dielectric layer can be appropriately increased to obtain lower leakage current, smaller operating voltage, longer information retention time, and higher read and write times.
  • the present invention further etches the dielectric film into discrete microstructures, thereby promoting the transition from a low dielectric constant phase to a high dielectric constant phase in the dielectric film through the size effect, thereby further improving the dielectric constant of the dielectric film.
  • the present invention further promotes the transition from a low dielectric constant phase to a high dielectric constant phase in the dielectric film by adjusting the process, such as implementing an annealing process, and/or applying an electric pulse, thereby increasing the dielectric constant of the dielectric film to above 900, thereby generating a giant dielectric constant effect and showing ultra-high specific capacitance and charge storage density, which can effectively reduce the operating voltage and leakage current of DRAM and CMOS devices.
  • the ultra-high dielectric constant dielectric film of the present invention demonstrates that the charge density at 1.2V is stable at 100 ⁇ C/ cm2 , and the number of cycles exceeds 1012 without causing dielectric breakdown.
  • the dielectric constant of the HZO crystal film with all O-phase grains can exceed 2400, far exceeding the performance indicators of existing supercapacitors, and with low energy consumption.
  • HZO material is a pseudo-ferroelectric, i.e., an electret. Therefore, the ferroelectric remnant polarization intensity can be increased by size effect and microelectronics process to more than 20 times that of conventional materials ( ⁇ 404 ⁇ C/ cm2 ), and can be applied to non-volatile high-density ferroelectric memory with metal/HZO/metal architecture.
  • the dielectric films and devices with ultra-high dielectric constant and ferroelectric remanent polarization strength of the present invention can be widely used in supercapacitors, CMOS devices, dynamic random access memory (DRAM), charge capture devices, three-dimensional stacked flash memory (3D NAND), non-volatile ferroelectric memory (FRAM and FeFET) and other devices.
  • FIG. 1 is a schematic diagram of the preparation state of the TiN-HZO-TiN capacitor according to Example 1 of the present invention.
  • FIG. 2a and FIG. 2b are comparison diagrams of dielectric constant and loss of TiN/HZO/TiN thin film capacitors of different sizes prepared by the method of Example 1 as a function of frequency (f).
  • FIG. 3a-3c are schematic diagrams showing the giant dielectric effect induced by applying electric pulse technology on a small-sized capacitor prepared by the method of Example 1.
  • FIG. 3a-3c are schematic diagrams showing the giant dielectric effect induced by applying electric pulse technology on a small-sized capacitor prepared by the method of Example 1.
  • 4a-c are comparison diagrams of the changes in charge density in the capacitor before and after the giant dielectric effect is induced by the electric pulse technology (before and after the electric pulse is applied).
  • 5a-5c are comparison diagrams of the change of charge density in the capacitor with the applied voltage after the giant dielectric effect is induced by electric pulse technology.
  • Figures 6a-6c are high-precision transmission electron microscopy (HAADF-STEM) imaging analysis of the crystal structure of the dielectric film before and after fatigue.
  • HAADF-STEM transmission electron microscopy
  • FIG. 7 is a schematic diagram of the preparation state of a TiN-HZO-TiN capacitor according to Example 2.
  • Figures 9a-9c are schematic diagrams of the giant polarization intensity of the TiN/HZO/TiN capacitor caused by ion implantation and size effect in the electrode edge region in the method of Example 2, showing the ferroelectric hysteresis loop of electric displacement-electric field (DE) at different sizes ( Figure 9a), the change of charge and discharge current of flippable and non-flippable domains with time under different applied voltages (Figure 9b), and the change of their polarization intensity (P sw and P nsw ) with holding time ( Figure 9c).
  • the test frequency of the DE hysteresis loop is 1MHz.
  • FIG. 10 is a schematic diagram of the preparation state of a TiN-HZO gate dielectric layer in Example 3.
  • FIG. 11 is a schematic diagram showing the preparation state of a TiN-HZO gate dielectric layer in Example 4.
  • FIG. 12 a and FIG. 12 b are schematic diagrams showing the state of effectively capturing electrons or holes under positive and negative writing electric fields using ultra-high dielectric constant/low dielectric constant TiN/HZO/Si 3 N 4 /TiN stacked capacitors.
  • FIG. 13 is a schematic structural diagram of a TiN/HZO/Si 3 N 4 /HZO/TiN multi-layer capacitor.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components.
  • installed should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components.
  • the "discrete microstructure” described herein means that the microstructure is distributed in the form of isolated islands, which are not connected to each other and can be uniform or non-uniform; the lateral size of the microstructure is 1nm to 50 ⁇ m, the size of each microstructure can be the same or different, and the pattern of each microstructure is selected from at least one of square, trapezoid, triangle, circle, etc., and can also be irregular.
  • the microstructures on the same electrode and/or dielectric film can be the same or different.
  • the "giant dielectric effect” and “giant ferroelectric effect” mentioned in this article refer to the phenomenon that the dielectric constant and ferroelectric remnant polarization strength increase sharply due to ion implantation into the dielectric film before depositing the first electrode, etching the first electrode or the dielectric film, and performing rapid annealing.
  • the "super dielectric constant” mentioned herein refers to a dielectric constant k greater than 100
  • the “super ferroelectric effect” refers to a dielectric constant k greater than 100 and a ferroelectric remanent polarization greater than 40 ⁇ C/cm 2 .
  • the "giant dielectric constant” mentioned herein refers to a dielectric constant k greater than 900, and the “giant ferroelectric effect” refers to a ferroelectric remnant polarization greater than 400 ⁇ C/cm 2 .
  • the low-k in the “low-k dielectric material” described herein refers to a dielectric constant k ⁇ 20, usually 3-9; the “high dielectric constant” described herein refers to a dielectric constant k>20.
  • DRAM cells consist of transistors and capacitors, where the transistors serve as memory cell selectors and data is stored in the form of charge in the capacitor cells. As the size of the capacitors shrinks, the amount of charge stored in the capacitors decreases. In order to obtain a sufficiently high readout signal margin over thermal noise or other parasitic capacitances, it is difficult to maintain a sufficiently high critical charge number using conventional ZrO2/Al2O3/ZrO2 or ZrO2 / Al2O3 dielectric layers . The minimum equivalent oxide thickness (EOT) of these conventional dielectric stacks is approximately However, future DRAM technology requires further reduction of EOT (below ), and the leakage current is also required to be within an acceptable range ( ⁇ 10 -7 A/cm 2 ).
  • EOT equivalent oxide thickness
  • HZO materials have many advantages, such as large bandgap (>5eV), extremely thin thickness ( ⁇ 1nm), good reliability and durability of electrical operation, compatibility with CMOS integrated circuit processes, three-dimensional spatial growth and gap filling capabilities, and many potential applications, such as ferroelectric field effect transistors (FeFETs), ferroelectric random access memories (FRAMs), negative capacitance, logic and synaptic devices.
  • FeFETs ferroelectric field effect transistors
  • FRAMs ferroelectric random access memories
  • negative capacitance logic and synaptic devices.
  • HZO has metastable high-k crystalline phases, such as ferroelectric O phase (k value 25-30) and antiferroelectric T phase (k value 35-40).
  • the most stable phase in HZO at room temperature is the M phase with a relatively low k value ( ⁇ 20).
  • Post-metallization thermal annealing techniques such as rapid thermal annealing (RTP) or high pressure post-metallization annealing (HPPMA) have been tried to stabilize high-k phases (such as O phase and T phase) in HZO, but its k value is still low compared with other dielectrics (such as TiO 2 and SrTiO 3 , etc.).
  • RTP rapid thermal annealing
  • HPPMA high pressure post-metallization annealing
  • the present invention promotes the transformation of the low dielectric constant phase to the high dielectric constant phase in the HZO film through ion implantation and device size effect, so that the HZO film can exhibit ultra-high dielectric constant and ultra-high ferroelectric residual polarization intensity, and can significantly reduce EOT.
  • the charge capacity stored in the memory cell of the same size can be increased by at least 10 times.
  • the present invention can implement any one or any two or more of the following methods:
  • the upper electrode or the upper electrode/dielectric film is made into a discrete microstructure
  • the low dielectric constant phase is transformed into a high dielectric constant phase
  • the low dielectric constant phase is transformed into a high dielectric constant phase.
  • the dielectric constant may be super-high or extremely high, while the ferroelectric remnant polarization intensity is small; the ferroelectric remnant polarization intensity may be extremely high, while the dielectric constant does not reach super-high.
  • the present invention provides a method for preparing a dielectric film and a device having an ultra-high dielectric constant and/or ferroelectric remanent polarization, comprising the following steps:
  • Step a forming a dielectric film on a substrate or on a substrate with a second electrode; the dielectric film comprises a Hf1- xZrxO2 film, which is a crystalline or amorphous film; wherein 0 ⁇ x ⁇ 1;
  • Step b forming a first electrode on the dielectric film
  • Step c dividing the first electrode into a plurality of discrete microstructures, each microstructure having a lateral dimension of 1 nm to 50 ⁇ m;
  • Step d annealing treatment, so that the low dielectric constant phase in the dielectric film is reduced, the high dielectric constant phase is increased, and the average dielectric constant of the dielectric film is greater than 100.
  • active ions are implanted into the entire dielectric film, and the dielectric film is preferably amorphous.
  • the role of ion implantation is to improve the dielectric and ferroelectric properties of the dielectric film.
  • active ions can also be implanted into the dielectric film at the edge of the first electrode after step c (before step d).
  • active ions may not be implanted before step b, and may be implanted before the annealing treatment.
  • the active ions include any one or more of carbon, nitrogen, oxygen, boron, helium, phosphorus, iron, aluminum, zinc, cobalt, tin, nickel, titanium, silicon, phosphorus, argon, chlorine, bromine, sulfur, iodine, fluorine, hydrogen, silver, gold, copper, and platinum; the implantation dose of the active ions is 10 10 -10 20 ions/cm 2 .
  • the ion implantation methods include, but are not limited to, ion implanters and reactive ion etching (ICP, RIE) machines commonly used in microelectronics processes.
  • ICP reactive ion etching
  • the dielectric film can also be divided into discrete microstructures, that is, the stack of the first electrode and the dielectric film is divided into discrete microstructures.
  • the division includes etching, and conventional microelectronic dry or wet etching processes can be used, including but not limited to reactive ion etching (RIE), plasma etching (ICP), chemical solution etching (SC-1 solution etching), etc.
  • RIE reactive ion etching
  • ICP plasma etching
  • SC-1 solution etching chemical solution etching
  • the lateral size of each microstructure can be adjusted to 1 nm to 1 ⁇ m.
  • the device after the microstructure is formed can also be subjected to rapid high temperature annealing.
  • the annealing process includes but is not limited to tube furnace annealing, rapid thermal annealing (RTP), high pressure metallization post annealing (HPPMA), microwave annealing (MVA), laser annealing, etc.
  • the annealing is carried out in a protective atmosphere such as nitrogen and argon, the annealing temperature is 300°C to 900°C, and the annealing time is 1s to 8h.
  • the protective atmosphere of the annealing process is nitrogen, the annealing temperature is 500° C. to 600° C., and the time is 35 s to 2 h. In some embodiments, rapid high temperature annealing is used, and the annealing time is 30 s to 60 s.
  • the thickness of the dielectric film is preferably 0.5 nm to 50 nm. In practical applications, the thickness of the dielectric film can be appropriately increased within this thickness range, thereby obtaining lower leakage current, lower operating voltage, longer information retention time, and higher read and write times, thus broadening the application range of the ultra-high dielectric constant dielectric film of the present invention.
  • the high dielectric constant O phase content can be increased by optimizing the preparation process of the HZO film during the formation of the HZO film on the substrate.
  • the preparation process of the HZO film includes but is not limited to sol-gel method, sputtering deposition method, pulsed laser deposition method, metal organic chemical vapor deposition method, atomic layer deposition, ion beam evaporation method, etc.
  • the HZO film is prepared by atomic layer deposition and, after completion, is subjected to a post-metallization thermal annealing treatment.
  • the HZO film comprises: a HZO film with a stacked structure formed by alternately growing HfO2 and ZrO2 , or a Hf1-xZrxO2 composite film, or a Hf1 - xZrxO2 composite film doped with other ions.
  • the HZO film may also be doped with one or more elements including but not limited to Si, Er, Y, Al, etc., with a doping concentration of 0-50 mol%.
  • the dielectric film further comprises: other dielectric materials. That is, the HZO film can be used alone or in combination with other dielectric material stacks to improve the dielectric constant of the stacked dielectric film, and can be applied to CMOS gate dielectric materials, DRAM or other supercapacitors.
  • the other dielectric material can be a low-k dielectric material layer, such as SiO 2 , Si 3 N 4 , etc.
  • the method further comprises: applying positive and negative electric pulses to the device after the annealing treatment in step d, so as to further promote the transformation of the low dielectric constant phase to the high dielectric constant phase in the dielectric film.
  • the substrate may be a silicon substrate, a silicon substrate with SiO 2 attached, or other conventional substrates.
  • the materials of the first electrode and the second electrode can be selected from but not limited to any one or more of TiN, W, Al, n/p-Si, PtSi, Mo, Cu, Co, Ta, Ru, Ir, Ti, Cr, etc.
  • the present invention provides a dielectric film and device with ultra-high dielectric constant and/or ferroelectric residual polarization.
  • the dielectric film with ultra-high dielectric constant and ferroelectric residual polarization is processed by any one or more of the above-mentioned ion implantation, etching into isolated island microstructure, annealing, positive and negative pulses, etc.
  • the device comprises: a substrate, a dielectric film with ultra-high dielectric constant and ferroelectric residual polarization, and a first electrode, which are stacked in sequence; the first electrode comprises a plurality of discrete microstructures, or the first electrode and the dielectric film both comprise a plurality of discrete microstructures; the lateral size of each microstructure is 1nm to 50 ⁇ m.
  • a second electrode is attached to the substrate and is located between the substrate and the dielectric film.
  • the devices include: any one or any two or more of supercapacitors, CMOS devices, dynamic random read/write memory (DRAM), charge capture memory devices, three-dimensional stacked flash memory (3D NAND), and non-volatile ferroelectric memory (FRAM or FeFET).
  • CMOS devices dynamic random read/write memory
  • DRAM dynamic random read/write memory
  • charge capture memory devices charge capture memory devices
  • 3D NAND three-dimensional stacked flash memory
  • FRAM or FeFET non-volatile ferroelectric memory
  • first electrodes of different lateral sizes are etched through Example 1, and ions are implanted into the edge area of the electrode, combined with high-temperature rapid annealing, to promote the transition from the low dielectric constant phase to the high dielectric constant phase in the HZO dielectric film, so as to verify the influence of the lateral size of the first electrode of the capacitor on the dielectric constant and ferroelectric remanent polarization strength of the dielectric film.
  • FIG. 1 it is a schematic diagram of the preparation state of a TiN-HZO-TiN capacitor.
  • an HZO film 103 (which may be a crystalline or amorphous film) is prepared on a Si substrate 101 with a TiN electrode (second electrode 102B) by atomic layer deposition, and then a layer of TiN is grown by physical vapor deposition as the first electrode 102A.
  • step S1 photoresist is spin-coated on the surface of the first electrode 102A, and square patterns of different sizes are formed by optical exposure or electron beam exposure, and then a layer of metal Cr is grown by thermal evaporation process, and the metal Cr in the unexposed area is stripped off by lift-off process, and the remaining square pattern area is covered with Cr mask 104.
  • step S2 a reactive ion etching (RIE) process is used to remove the first electrode 102A in the area not covered by the Cr mask 104, and active ions 105 are implanted into the HZO in the edge area of the electrode.
  • RIE reactive ion etching
  • Step S3 removing the Cr mask by wet etching, and then placing the sample in a N2 atmosphere by a rapid thermal annealing process, annealing at 500°C to 600°C for 30s to 60s, to prepare a capacitor containing a dielectric film with ultra-high dielectric constant and ferroelectric remanent polarization strength.
  • the HZO film is a Hf 0.5 Zr 0.5 O 2 film.
  • the first electrode TiN of the TiN/Hf 0.5 Zr 0.5 O 2 /TiN sandwich structure film is etched into an island square pattern to form a capacitor structure of different sizes with the second electrode TiN, and the HZO film in the electrode edge area is implanted with active ions (O 2- , S 6+ and F - in this example), with a total implantation dose of about 10 16 ions/cm 2 ; then it is rapidly annealed at 550°C for 40s, wherein the Hf 0.5 Zr 0.5 O 2 film thickness is 10nm, and its dielectric constant and loss are measured as a function of frequency.
  • the dielectric constant and loss of TiN/HZO/TiN film capacitors of different sizes prepared by the method of Example 1 are respectively shown as a function of frequency (f). It is found that the smaller the lateral size of the first electrode, the larger the dielectric constant. When the size is 5.2 ⁇ m, the dielectric constant can be greater than 100 ( Figure 2a). At a frequency of 1MHz, when the lateral size of the first electrode is reduced from 32 ⁇ m to 5.2 ⁇ m, the dielectric constant increases monotonically from 30 to 132, proving that the reduction in the size of the first electrode can effectively increase the dielectric constant of the HZO film. At the same time, a very wide dielectric loss peak appears near 20kHz (Figure 2b).
  • the device size effect combined with the excitation of external electric pulses, can promote the steady transformation of the low dielectric constant phase of Hf1 - xZrxO2 film to the high dielectric constant phase, so that the dielectric constant of the 4.4 ⁇ m capacitor at 1MHz is significantly increased from the original 30 to 921.
  • positive and negative electric pulses are applied to the capacitor prepared by the process shown in Figure 1 of Example 1 to further promote the transition from the low dielectric constant phase to the high dielectric constant phase, so that the HZO film has a giant dielectric constant.
  • the capacitor structure that produces a giant dielectric constant is TiN/HZO/TiN
  • the film thickness of the HZO film is 10nm
  • the lateral size of the first electrode TiN is less than 10 ⁇ m
  • the dielectric constant is 800-1400
  • the O phase content is 38%.
  • the application of electric pulse technology can also induce the giant dielectric effect that occurs in small-sized capacitors prepared using the process shown in Figure 1, proving that the ultra-high dielectric constant dielectric film obtained by the processing method of the present invention can be used in high-density energy storage.
  • the first electrode TiN of another TiN/ Hf0.5Zr0.5O2 /TiN film was etched into unconnected square patterns with a lateral size of 4.4 ⁇ m, and ion implantation ( O2- , S6 + and F- in this example) was performed on the HZO film in the edge area of the electrode with an implantation dose of 1016 ions/ cm2 .
  • Figure 3b shows the variation of the ferroelectric remanent polarization intensity of capacitors with lateral sizes of 4.4 ⁇ m and 5.4 ⁇ m with the number of applied pulses, which drops to 0 after 1.01 ⁇ 107 and 4.16 ⁇ 107 cycles, respectively.
  • the above experimental results predict that the smaller the size of the capacitor, the fewer the number of electric pulse cycles applied to produce giant dielectrics, and the larger the dielectric constant.
  • Figure 3c shows the variation of the energy storage density of fatigue capacitors with sizes of 4.4 ⁇ m and 5.4 ⁇ m with the applied electric field, proving that the larger the absolute value of the applied electric field, the greater the storage energy density.
  • Figures 4a-4c show the change of the charge density in the capacitor before and after the giant dielectric effect is induced by the electric pulse technology (before and after the electric pulse is applied).
  • Figure 4a shows the measurement equivalent circuit of the TiN/Hf 0.5 Zr 0.5 O 2 /TiN capacitor with a size of 4.4 ⁇ m prepared by the method of Example 1.
  • the HZO capacitor is connected in series with a 1M ⁇ resistor.
  • the width of the applied electric pulse is 5ms, and the applied voltage (V) is gradually increased from 0.2V to 2V, with a step size of 0.2V.
  • Figures 4b and 4c respectively show the change of the charging current of the capacitor before and after the electric pulse is applied.
  • Figure 4b represents before the electric pulse is applied
  • Figure 4c represents after the electric pulse is applied.
  • Figures 5a-5c show the change of the charge density in the capacitor with the applied voltage after the giant dielectric effect is induced by the electric pulse technology.
  • Figure 5a is the measurement equivalent circuit of the TiN/Hf 0.5 Zr 0.5 O 2 /TiN capacitor with a size of 4.4 ⁇ m prepared by the method of Example 1.
  • the HZO capacitor is connected in series with a 100 ⁇ resistor.
  • the applied electric pulse width is 100ns, and the applied voltage (V) is gradually increased from 0.2V to 2V, with a step size of 0.2V.
  • Figure 5b shows the change of the charging current of the capacitor after fatigue with time, and its charging current is significantly higher than that of Figure 4b.
  • the charge density (P nsw ) of the capacitor under different voltages is obtained.
  • Figure 5c shows that the charge density of the capacitor remains stable as the number of charging cycles increases, wherein the applied rectangular pulse voltage/pulse width is +/-1.2V/50ns, and the repetition period is 10MHz.
  • the charge density can reach 100 ⁇ C/cm 2 at 1.2V, and it stabilizes to 10 12 with the number of charge and discharge cycles without causing electrical breakdown, proving that it can be applied to fields such as DRAM and can improve the miniaturization of storage units ( ⁇ 10nm).
  • the thickness of the dielectric film can also be appropriately increased to obtain lower leakage current, smaller operating voltage, longer information retention time, and higher read and write times.
  • Figures 6a-6c are high-resolution transmission electron microscopy imaging analysis of the crystal structure of the dielectric film before and after fatigue, showing the changes in the crystal structure of the dielectric film before and after the giant dielectric effect is induced by the electric pulse technology.
  • Figure 6a is a high-angle annular dark field scanning transmission electron microscopy (HAADF-STEM) imaging analysis of a typical O-phase grain in a TiN/HZO/TiN capacitor structure with a size of 5.7 ⁇ m prepared by the method of Figure 1.
  • HAADF-STEM high-angle annular dark field scanning transmission electron microscopy
  • Figure 6b is a HAADF-STEM imaging of a typical O-phase grain in the HZO crystal film after fatigue (after applying an electric pulse), showing that the low dielectric constant M phase embedded in the O-phase grain disappears and is completely converted into the O phase, and the ferroelectric remanent polarization intensity is 0 ⁇ C/ cm2 (see the right figure in Figure 6c), resulting in a sharp increase in the overall dielectric constant of the film and a giant dielectric effect.
  • the electron diffraction spots after Fourier transformation of the O-phase grains after fatigue all show an orthorhombic phase (i.e., O-phase).
  • Figure 6c is a sample component analysis comparison diagram of the dielectric film before and after fatigue.
  • Example 2 The following is combined with Example 2 to demonstrate that the O phase ratio in the HZO film can be controlled by etching the lateral dimensions of the stack of the first electrode 102A and the HZO film 103, thereby promoting the transition of the low dielectric constant phase to the high dielectric constant phase in the film.
  • FIG7 it is a schematic diagram of another TiN-HZO-TiN capacitor in the preparation state. Except for step S2 of etching the TiN/HZO stack, the other steps are the same as those in Example 1.
  • a TiN/Hf 0.5 Zr 0.5 O 2 /TiN sandwich structure film is grown on a silicon substrate, and then the TiN/HZO stack is etched into an isolated capacitor structure with a size of less than 10 ⁇ m, and then rapidly thermally annealed (550°C) for 50 seconds in a nitrogen atmosphere, and then the top TiN electrode (first electrode) is etched away using SC-1 cleaning solution.
  • the X-ray diffraction test results of HZO crystal films of different sizes measured at 0.45 ° grazing incidence at a synchrotron radiation light source are shown in Figure 8.
  • the continuous HZO crystal film is mainly composed of T phase and O phase, without M phase.
  • the proportion of O phase grains increases significantly as the lateral size of the HZO crystal film decreases.
  • the proportion of O phase can be as high as 99%, and the T phase in the HZO crystal film is almost completely converted into O phase.
  • the capacitor size is less than 300nm
  • the low dielectric constant tetragonal/monoclinic phase can be completely converted into orthorhombic phase
  • the O phase content in the HZO crystal film is close to 100%
  • the dielectric constant of the HZO crystal film can be greater than 2400. It can be seen that the dielectric constant and ferroelectric polarization strength of HZO can be effectively improved through ion implantation, reduction of the lateral dimensions of the first electrode and the HZO film, and rapid annealing process.
  • the ferroelectric residual polarization is also improved by ion implantation.
  • a plasma etcher is used to etch an unannealed amorphous or crystalline hafnium oxide film capacitor into an isolated capacitor. Using a mixed atmosphere of SF6 and O2 , etching is performed at a power of 50 to 100 W for 1 to 5 minutes. Under the bombardment of reactive ions, a large number of active ions are implanted into the HZO film at the edge of the electrode. Then the entire capacitor is rapidly annealed at 550°C for 30 seconds.
  • the small-sized HZO film capacitor not only has a high dielectric constant, but also exhibits a high ferroelectric residual polarization.
  • Figures 9a-9c show that the residual polarization intensity in the TiN/HZO/TiN stacked capacitor of this embodiment increases sharply as the lateral size of the HZO film decreases, and can reach 404 ⁇ C/ cm2 at 0.3 ⁇ m (Figure 9a), which is more than 20 times the polarization intensity of conventional HZO. It can be applied to non-volatile ferroelectric memory and can significantly improve the readout charge number or information storage density of the memory.
  • Figure 9b shows that after applying a -/+3V write voltage, the readout current of the memory changes with time at different read voltages, and the step size of the readout voltage change is 0.2V.
  • the dielectric film with ultra-high dielectric constant and ferroelectric polarization strength provided by the present invention can be applied to high-density integrated non-volatile/volatile memory and ultra-large-scale logic devices, and has advantages such as low-voltage operation.
  • FIG10 it is a schematic diagram of the preparation state of a TiN-HZO gate dielectric layer.
  • the Si substrate 101 does not have a TiN lower electrode (second electrode 102B), and a HZO film 103 is directly prepared on the Si substrate 101, which is in an amorphous state.
  • the entire HZO film is ion implanted (O 2- , S 6+ and F - in this example), and the implantation dose is 10 16 ions/cm 2.
  • a layer of TiN is grown as the first electrode 102A by a physical vapor deposition process.
  • Step S1 spin-coating photoresist on the surface of the first electrode 102A, forming square patterns of different sizes by optical exposure or electron beam exposure, then growing a layer of metal Cr by thermal evaporation, and stripping off the metal Cr in the unexposed area by lift-off process, leaving the square pattern area covered with Cr mask 104.
  • the first electrode 102A is etched into discrete microstructures to obtain a TiN-HZO gate dielectric layer.
  • Step S2 using a reactive ion etching (RIE) process to remove the first electrode 102A in the area not covered by the Cr mask 104, and etching the first electrode 102A into discrete microstructures to obtain a TiN-HZO gate dielectric layer.
  • RIE reactive ion etching
  • Step S3 removing the Cr mask by wet etching, and then placing the sample in a N2 atmosphere by a rapid thermal annealing process, annealing at 500°C to 600°C for 30s to 60s, to prepare a capacitor containing a dielectric film with ultra-high dielectric constant and ferroelectric remanent polarization strength.
  • FIG. 11 it is a schematic diagram of another TiN-HZO gate dielectric layer preparation state.
  • the Si substrate 101 does not have a TiN lower electrode (second electrode 102B), and the HZO film 103 is directly prepared on the Si substrate 101. Then, a layer of TiN is grown by physical vapor deposition process as the first electrode 102A.
  • Steps S1 to S3 are the same as those in Example 3, except that the first electrode 102A and the HZO film are all etched into discrete microstructures to obtain a TiN-HZO gate dielectric layer.
  • ultra-thin and ultra-high dielectric constant HZO gate dielectric materials provides a new alternative material and new device direction for future silicon transistors, subverting the physical properties of existing traditional high-k dielectric materials and having a significant impact on the entire microelectronics industry.
  • HfO2 traditional stacked dielectrics
  • AFE- ZrO2 AFE- ZrO2
  • FE-Zr FE-Zr: HfO2 with a thickness of 1.5-1.0 W
  • the ultra-high dielectric constant dielectric film of the present invention shows ultra-high specific capacitance and charge storage density, and can effectively reduce the operating voltage and leakage current of DRAM and CMOS devices.
  • Example 2 The same method as in Example 1 is used, except that after forming the HZO film 103 on the second electrode 102B, a low dielectric constant Si 3 N 4 film 106 is also formed, and a layer of TiN is grown by physical vapor deposition as the first electrode 102A.
  • the dielectric film includes the HZO film and the Si 3 N 4 film, and the capacitor prepared is a TiN/HZO/Si 3 N 4 /TiN stacked capacitor, as shown in FIG12a.
  • Figures 12a and 12b demonstrate the effective capture of electrons or holes by using ultra-high dielectric constant/low dielectric constant TiN/HZO/Si 3 N 4 /TiN stacked capacitors under positive and negative write electric fields, proving that the combination of HZO film processed by the method of the present invention and low dielectric constant materials can be applied to non-volatile storage of information, greatly reducing the erase voltage, such as can be used in charge capture type memory.
  • a layer of HZO film is deposited on the low dielectric constant Si 3 N 4 film 105 in embodiment 5 to obtain a TiN/HZO/Si 3 N 4 /HZO/TiN multi-layer capacitor, as shown in FIG13 .
  • the present invention can etch a first electrode or a stack of a first electrode and a dielectric film with a nanometer thickness into an isolated capacitor through a microelectronic device etching process combined with active ion implantation, size effect and external electric pulse, thereby generating a giant dielectric effect (k>900) and a giant ferroelectric effect (residual polarization intensity>400 ⁇ C/ cm2 ), breaking through the dielectric constant limit of traditional ultra-thin film materials ( ⁇ 52).
  • the DRAM unit size can be easily reduced to a technical node below 10nm, the miniaturization of the device is improved, the storage density is increased by at least 10 times, and the leakage current is reduced.
  • the ultra-high dielectric constant dielectric film of the present invention can also be stacked with other low dielectric constant materials ( SiO2 , Si3N4 , etc.), which can effectively enhance the charge capture function, form a non-volatile charge capture memory, significantly improve the charge capture efficiency, greatly reduce the erase voltage, and extend the erase life of the memory, and can be applied to 3D NAND.
  • Each device in the 3D NAND flash memory is a metal- Al2O3 - nitride -silicon oxide charge capture device with a TiN/W metal gate and a polysilicon channel.
  • the diameter of the channel hole is limited, and the physical thickness of the barrier layer cannot be increased due to the limited channel hole diameter, so the use of high-k dielectrics has the advantage of reducing EOT.
  • a high dielectric constant HZO layer in the barrier layer to increase the capacitance to enhance its performance, a larger storage window and a higher operating speed can be provided.
  • the application of the ultra-high dielectric constant dielectric film of the present invention in the charge capture memory will not affect the retention characteristics, because there may be no ferroelectric remnant polarization in the ultra-high-k HZO crystal film.
  • the capacitance boosting effect in charge capture memory can be enhanced, thereby improving the performance of 3D NAND devices, reducing the erase voltage and extending the device life.
  • the present invention improves the ferroelectric residual polarization intensity through ion implantation, size effect and microelectronic process.
  • the ion implantation and size effect can cause the residual polarization intensity in the capacitor of the ultra-high dielectric constant HZO crystal thin film material to increase sharply as the size decreases. It can reach 404 ⁇ C/ cm2 at 0.3 ⁇ m, which is more than 20 times the polarization intensity of conventional HZO. It can be applied to non-volatile ferroelectric memory of metal/HZO/metal structure, and can significantly improve the readout charge number or information storage density of the memory.
  • the ultra-high dielectric constant dielectric film of the present invention can also be applied to supercapacitors as capacitor storage dielectric materials to improve energy storage density.
  • Dielectric capacitors are widely used in many fields, such as high-power applications such as electronic circuits, microwave communications, hybrid vehicles, distributed power systems, renewable energy storage and fusion with various functions (filtering, coupling, decoupling, etc.), and different applications require capacitors with different characteristic types.
  • capacitors used for microwave communication applications should have very high quality factors (extremely low dielectric losses), while capacitors used for decoupling circuits require large capacitance per unit volume.
  • the lower energy density of dielectric capacitors limits their practical applications.
  • the present invention can be applied to the gate insulating layer in complementary metal oxide semiconductor CMOS, and can reduce the size of CMOS devices to less than 5nm, greatly reduce the operating voltage ( ⁇ 1V), reduce the short channel effect and leakage current, and can be applied to the manufacturing process of CMOS devices with technology nodes below 3-5nm.
  • CMOS complementary metal oxide semiconductor
  • ⁇ 1V operating voltage
  • CMOS devices with technology nodes below 3-5nm.
  • SiO2 silicon dioxide
  • the ultra-thin SiO2 cannot suppress the generation of tunneling current.
  • HZO as an ultra-high k material, can effectively suppress tunneling current under the condition of thinner thickness or constant thickness.
  • ultra-high dielectric constant HZO can increase the gate capacitance to maintain effective control of carriers in the channel and reduce the operating voltage.
  • the HZO ultra-high k thin film material grown by atomic layer deposition (ALD) overcomes the compatibility problem that plagues traditional perovskite-based ferroelectric materials.
  • the thickness of the HZO film can be reduced to less than 1nm, which is helpful for integration into the most advanced large-scale devices.
  • the HZO/Si heterojunction has good thermodynamic stability and good lattice matching properties.

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Abstract

本发明公开了一种具有超高介电常数和/或铁电剩余极化强度的介质薄膜和器件的制备方法及器件。该方法包含：步骤a，在衬底上或附有第二电极的衬底上形成介质薄膜；该介质薄膜包含Hf1-xZrxO2薄膜，其为晶体或非晶态薄膜；0≤x≤1；步骤b，在所述介质薄膜上形成第一电极；步骤c，将第一电极分割为若干离散的微结构，每个微结构的横向尺寸为1nm～50μm；步骤d，退火处理，使得所述介质薄膜中低介电常数相减少，高介电常数相增加。采用本发明的方法提供的超高介电常数和/或铁电剩余极化强度的介质薄膜和器件，最高介电常数和铁电剩余极化强度分别可大于921和404μC/cm2，信息存储密度高，能够有效地降低器件的操作电压和漏电流，且与CMOS集成工艺兼容性良好，应用前景良好。

Description

具有超高介电常数和/或铁电剩余极化强度的介质薄膜和器件的制备方法及器件 技术领域
本发明属于微电子和固体电子学技术领域，涉及High-k介质材料，具体涉及一种具有超高介电常数和/或铁电剩余极化强度的介质薄膜和器件的制备方法及器件。
背景技术
随着信息化和大数据时代的迅速发展，对数据存储密度的需求变高，例如，要求器件可缩微性更好(3-5纳米)，互补金属氧化物半导体逻辑器件(CMOS)的操作电压更小，功耗更低。在经典的冯·诺依曼体系结构中，动态随机存取存储器(DRAM)主要用作存储器层次结构中的内存，具有读写速度快(～20ns)和读写次数高(>10 15)等优点。随着信息量的需求呈指数增长，为了提高存储密度，DRAM存储单元的横向尺寸缩减已经逼近工艺极限12nm，进一步缩减需要存储材料的物理性能发生变革性变化。因此，需要开发具有更高介电常数(k)的新存储介电材料，以便在10nm以下技术节点的小存储单元中存储足够多的电荷，供读写电路进行可靠的位操作。
为了突破这一技术瓶颈，用作下一代DRAM电容器介质薄膜的高k材料已被大量研究。
在最新的DRAM技术中，具有三维电容器结构的ZrO 2/Al 2O 3/ZrO 2(ZAZ)介电层被用作高k材料。研究表明，实现EOT<0.5nm对提高存储密度非常关键。然而，目前可从ZAZ介电薄膜中获得的最小等效氧化物厚度(EOT＝3.9/k×t phy，t phy为薄膜的物理厚度)约为0.6nm，不能达到要求。
TiO 2和SrTiO 3等存储材料的EOT值可缩小到
Figure PCTCN2022124854-appb-000001
但其具有较低的带隙，因此会有高泄漏电流问题，而且该问题会随器件尺寸缩小而增大。
由于具备CMOS兼容性和较宽的带隙，HZO(Hf 1-xZr xO 2，0≤x≤1)超薄膜(～2nm)作为栅介质材料具有较高的介电常数(～52)，可以降低EOT(～0.65nm)和压制CMOS纳米器件的短沟道效应，降低了漏电流，阈值电压可降低至0.55V，操作电压可减小至1.6V[Cheema,S.S.et al.,Nature 580,478–482(2020)]，大大地提高了CMOS器件的可缩微性。
HZO晶体薄膜材料中常见的相结构包含有单斜相(M相，空间群：P2 1/c)、四方相(T相，空间群：P4 2/nmc)和正交相(O相，空间群：P ca2 1)，其中，M相是室温中最稳 定的相，T相是高温相，O相被认为是铁电相。通常HZO多晶薄膜为M、T和O相的混合体，室温具有铁电性(FE)或反铁电(AFE)性，介电常数一般在16-70范围内变化。为了显著提高HZO的介电常数，尝试通过用不同的材料(如Si、Er、Y、Al等)掺杂来稳定其O和T相，减少M相，进而提高介电常数：Park等人最近证明，在使用RTP(快速热处理，rapid thermal processing)处理后的Hf 0.5Zr 0.5O 2薄膜中，物理厚度为6.5nm时，介电常数高达47，最低EOT值为
Figure PCTCN2022124854-appb-000002
而且，对于富含锆的Hf 0.3Zr 0.7O 2薄膜，介电常数更高，但其物理厚度更高(约9.2nm)，从而降低了高k值的优势。另外，HZO晶体薄膜具有铁电剩余极化强度(～20μC/cm 2)，可应用于非易失性铁电存储器。一般铁电剩余极化强度越大，存储单元尺寸可以做得越小，存储密度就越高。
而且，目前的HZO晶体薄膜的介电常数没有达到100以上的超高介电常数，铁电剩余极化强度一般不超过40μC/cm 2。
发明的公开
本发明的目的是解决目前的高k介质薄膜的介电常数不够高，铁电剩余极化强度不够大，器件单元尺寸不够小，以及高泄漏电流问题，提供一种具有超高介电常数和/或铁电剩余极化强度的介质薄膜和器件的制备方法及器件，最高介电常数和铁电剩余极化强度分别可大于921和404μC/cm 2，信息存储密度高，且与CMOS集成工艺兼容性良好。
为了达到上述目的，本发明提供了一种具有超高介电常数和/或铁电剩余极化强度的介质薄膜和器件的制备方法，包含：
步骤a，在衬底上或附有第二电极的衬底上形成介质薄膜；所述介质薄膜包含Hf 1-xZr xO 2薄膜，其为晶体或非晶态薄膜；其中，0≤x≤1；
步骤b，在所述介质薄膜上形成第一电极；
步骤c，将第一电极分割为若干离散的微结构，每个微结构的横向尺寸为1nm～50μm；
步骤d，退火处理，使得所述介质薄膜中低介电常数相减少，高介电常数相增加，介质薄膜平均介电常数大于100。
可选地，在步骤b之前和/或在步骤c之后，将活性离子注入到所述介质薄膜中。
可选地，所述活性离子包含碳、氮、氧、硼、氦、磷、铁、铝、锌、钴、锡、镍、钛、硅、磷、氩、氯、溴、硫、碘、氟、氢、银、金、铜、铂中任意一种或两种以上；所述活性离子的注入剂量为10 10-10 20ions/cm 2。
可选地，还将所述介质薄膜分割为离散的微结构。
可选地，所述分割包含刻蚀。
可选地，每个微结构的横向尺寸为1nm～1μm。
可选地，所述退火处理的温度为300℃～900℃，退火处理时间为1s～8h。
可选地，该方法还包含：对退火处理后的器件施加正负电脉冲。
可选地，所述介质薄膜的厚度为0.5nm～50nm。
可选地，所述Hf 1-xZr xO 2薄膜还掺杂有Si、Er、Y、Al元素中的至少一种，掺杂浓度为0-50mol％。
可选地，所述Hf 1-xZr xO 2薄膜的制备方法包含溶胶凝胶法、溅射沉积法、脉冲激光沉积法、金属有机化学气相沉积法、原子层沉积、离子束蒸发中的至少一种。
可选地，所述介质薄膜还包含：低k介电材料层，该低k介电材料层与所述Hf 1-xZr xO 2薄膜叠合使用。
可选地，该方法还包含：对退火处理后的器件进行处理，去除第一电极和衬底，得到具有超高介电常数和/或铁电剩余极化强度的介质薄膜。
本发明还提供了一种采用上述的制备方法制备的器件，其特征在于，该器件包含：衬底或附有第二电极的衬底、介质薄膜、第一电极；
所述介质薄膜包含Hf 1-xZr xO 2薄膜，其为晶体或非晶态薄膜；其中，0≤x≤1；
所述第一电极包含若干离散的微结构，或，所述第一电极和所述的介质薄膜均包含若干离散的微结构；每个微结构的横向尺寸为1nm～50μm。
可选地，所述器件包含：超级电容器、CMOS器件、动态随机读写存储器(DRAM)、电荷捕获存储器件、三维堆叠闪存(3D NAND)、非易失性铁电存储器(FRAM或FeFET)中任意一种或任意两种以上。
本发明的有益效果
1)本发明中HZO薄膜在离子注入和快速退火后随着第一电极尺寸的缩小，表现出高介电常数(大于100)，可以显著降低EOT，同样尺寸下存储电荷容量至少可以提高10倍以上。在实际应用中，可以适当增加介质层的厚度，从而得到更低的漏电流，更小的操作电压，信息保持时间更长，读写次数更高。
2)本发明还通过进一步将介质薄膜刻蚀为离散的微结构，通过尺寸效应促进介质薄膜内低介电常数相向高介电常数相转变，进一步地提高介质薄膜的介电常数。
3)本发明还通过调整工艺，如实施退火工艺，和/或施加电脉冲，进一步促进介质薄膜内低介电常数相向高介电常数相转变，将介质薄膜的介电常数提高到900以上，即产生巨介电常数效应，且显示出超高的比电容和电荷存储密度，能够有效地降低DRAM和CMOS器件的操作电压和漏电流。
4)本发明的超高介电常数介质薄膜，实例演示了在1.2V下的电荷密度稳定在100μC/cm 2，循环次数超过10 12而不引起介电击穿。通过工艺参数的调节和电容器的尺寸 效应，可实现全O相晶粒的HZO晶体薄膜的介电常数会超过2400，远远超越现有超级电容器的性能指标，且能耗低。
5)本发明发现HZO材料属于伪铁电体，即为驻极体。故可以通过尺寸效应和微电子工艺提高铁电剩余极化强度，达到常规材料的20倍以上(～404μC/cm 2)，可应用于具有金属/HZO/金属架构的非易失高密度铁电存储器中。
6)本发明的超高介电常数和铁电剩余极化强度的介质薄膜和器件可以广泛应用于超级电容器、CMOS器件、动态随机存储器(DRAM)、电荷捕获器件、三维堆叠闪存(3D NAND)、非易失性铁电存储器(FRAM和FeFET)等器件。
附图的简要说明
图1为本发明的实施例1的TiN-HZO-TiN电容器的制备状态示意图。
图2a、图2b分别为采用实施例1的方法所制备的不同尺寸的TiN/HZO/TiN薄膜电容器的介电常数和损耗随频率(f)的变化对比图。
图3a-3c为采用施加电脉冲技术诱发采用实施例1的方法制备出的小尺寸电容器出现的巨介电效应示意图。
图4a-c为采用电脉冲技术诱发巨介电效应前后(施加电脉冲前后)电容器中充电电荷密度的变化对比图。
图5a-5c为在采用电脉冲技术诱发巨介电效应后电容器中充电电荷密度随外加电压的变化对比图。
图6a-6c为疲劳前后介质薄膜晶体结构的高精度透射电镜(HAADF-STEM)成像分析图。疲劳前薄膜中高介电常数O相晶粒内嵌低介电常数M相(图6a)，疲劳后该内嵌的M相消失(图6b和图6b’)，导致薄膜整体介电常数急剧增大。疲劳前后M、O、T晶粒的总量变化不大(图6c)。
图7为实施例2的一种TiN-HZO-TiN电容器的制备状态示意图。
图8采用实施例2的方法所制备的不同尺寸的TiN/HZO/TiN薄膜电容器的小角度X射线衍射(XRD)图。随着HZO薄膜器件横向尺寸缩小，高介电常数O相含量逐渐增加。
图9a-9c为实施例2的方法中随着电极边缘区域中离子注入和尺寸效应所引起的TiN/HZO/TiN电容器的巨极化强度示意图，展示了不同尺寸下电位移-电场(D-E)的铁电电滞回线(图9a)、不同外加电压下可翻转与不可翻转电畴的充放电电流随时间变化(图9b)以及它们的极化强度(P sw和P nsw)随保持时间的变化(图9c)。其中D-E电滞回线的测试频率为1MHz。
图10为实施例3的一种TiN-HZO栅介质层的制备状态示意图。
图11为实施例4的一种TiN-HZO栅介质层的制备状态示意图。
图12a、图12b分别为采用超高介电常数/低介电常数的TiN/HZO/Si 3N 4/TiN叠层电容器在正负写入电场下实现对电子或空穴的有效捕获的状态示意图。
图13为一种TiN/HZO/Si 3N 4/HZO/TiN多叠层电容器的结构示意图。
附图标识：
衬底101、第一电极102A、第二电极102B、HZO薄膜103、掩膜104、活性离子105、低介电常数Si3N4薄膜106。
实现本发明的最佳方式
下面将结合附图对本发明的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明的描述中，需要说明的是，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
本文所述“离散的微结构”是指微结构呈孤岛的形式分布，彼此不相连，可以均匀也可以不均匀；微结构的横向尺寸为1nm～50μm，每个微结构的大小可以相同或不同，每个微结构的图形选自正方形、梯形、三角形、圆形等中的至少一种，也可以不规则。同一电极和/或介质薄膜上的微结构可以相同或不同。
本文所述“巨介电效应”、“巨铁电效应”分别指沉积第一电极前对介质薄膜进行了离子注入，然后对第一电极或介质薄膜进行刻蚀，并进行快速退火处理，导致介电常数、铁电剩余极化强度急剧增大的现象。
本文所述的“超介电常数”指介电常数k大于100，“超铁电效应”指介电常数k大于100，铁电剩余极化强度大于40μC/cm 2。
本文所述的“巨介电常数”指介电常数k大于900，“巨铁电效应”指铁电剩余极化强度 大于400μC/cm 2。
本文所述的“低k介电材料”中的低k是指介电常数k＜20，通常为3～9；本文所述的“高介电常数”是指介电常数k＞20。
DRAM单元由晶体管和电容器组成，其中，晶体管用作存储单元选择器，而数据以电荷的形式存储在电容器单元中。随着电容器尺寸缩减，电容器内存储的电荷数减小。为了在热噪声或其他寄生电容上获得足够高的读出信号裕度，使用传统的ZrO 2/Al 2O 3/ZrO 2或ZrO 2/Al 2O 3介电层来保持足够高的临界电荷数将很困难。这些传统介电叠层的最小等效氧化物厚度(EOT)约为
Figure PCTCN2022124854-appb-000003
然而，未来的DRAM技术要求进一步降低EOT(低于
Figure PCTCN2022124854-appb-000004
)，漏电流也要求在可接受范围内(<10 -7A/cm 2)。
HZO材料具有众多优点，如禁带宽度大(>5eV)、极薄的厚度(<1nm)、良好的电学操作的可靠性和耐久性、与COMS集成电路工艺兼容、具有三维空间生长和填隙能力，存在很多潜在的应用，如铁电场效应晶体管(FeFET)、铁电随机存取存储器(FRAM)、负电容、逻辑和突触器件。研究表明，HZO具有亚稳态高k晶相，例如铁电O相(k值25-30)和反铁电T相(k值35-40)。然而，在室温下HZO中最稳定的相是具有相当低的k值(<20)的M相。尝试使用快速热退火(RTP)或高压金属化后退火(HPPMA)等金属化后热退火技术来稳定HZO中高k相(如O相和T相)，但与其他介质(如TiO 2和SrTiO 3等)相比其k值仍然较低。
本发明通过离子注入和器件尺寸效应，促使HZO薄膜内低介电常数相向高介电常数相转变，可使得HZO薄膜表现出超高介电常数和超高铁电剩余极化强度，并可以显著降低EOT，同样尺寸下存储器单元中所存储的电荷容量至少可以提高10倍以上。
为了提高HZO薄膜内的高介电常数相的含量，实现介质薄膜的平均介电常数大于100，铁电剩余极化强度大于40μC/cm 2，本发明可以实施以下的任意一种或任意两种以上方法：
1)对所述整个非晶或晶态HZO介质薄膜进行离子注入，然后形成第一电极；
2)通过离子注入的方式，将活性离子注入到第一电极边缘部分的Hf 1-xZr xO 2薄膜中；
3)利用尺寸效应，将上电极或上电极/介质薄膜制成离散的微结构；
4)通过施加正负电脉冲，使得低介电常数相向高介电常数相转化；
5)通过HZO晶体薄膜的制备方法的工艺优化，提高高介电常数相的含量；
6)通过退火处理，使得低介电常数相向高介电常数相转化。
需要注意的是，采用不同的技术手段组合，也可能出现介电常数超高或巨高，而铁电剩余极化强度较小；也可能出现铁电剩余极化强度极高，而介电常数并未达到超高。
为了获取更高的介电常数和更大的铁电极化强度，也可以同时实施上述技术手段。
一些实施例中，本发明提供了一种具有超高介电常数和/或铁电剩余极化强度的介质薄膜和器件的制备方法，包含以下步骤：
步骤a，在衬底上或附有第二电极的衬底上形成介质薄膜；所述介质薄膜包含Hf 1-xZr xO 2薄膜，其为晶体或非晶态薄膜；其中，0≤x≤1；
步骤b，在所述介质薄膜上形成第一电极；
步骤c，将第一电极分割为若干离散的微结构，每个微结构的横向尺寸为1nm～50μm；
步骤d，退火处理，使得所述介质薄膜中低介电常数相减少，高介电常数相增加，介质薄膜平均介电常数大于100。
一些实施例中，在步骤b之前，将活性离子注入到整个所述介质薄膜中，所述介质薄膜呈非晶态效果更佳。离子注入的作用是提高介质薄膜的介电性和铁电性。为取得更高的介电常数和铁电剩余极化强度，还可以在步骤c之后(步骤d之前)，将活性离子注入到第一电极边缘处的介质薄膜中。
一些实施例中，也可以在步骤b之前不注入活性离子，待退火处理前再注入活性离子。
所述活性离子包含碳、氮、氧、硼、氦、磷、铁、铝、锌、钴、锡、镍、钛、硅、磷、氩、氯、溴、硫、碘、氟、氢、银、金、铜、铂中任意一种或两种以上；所述活性离子的注入剂量为10 10-10 20ions/cm 2。
离子注入的方式包括但不限于微电子工艺中常用的离子注入机和反应离子刻蚀(ICP、RIE)机。
为促使介质薄膜中低介电常数相向高介电常数相转变，还可以将所述介质薄膜分割为离散的微结构，即将第一电极与介质薄膜的叠层均分割为离散的微结构。所述分割包含刻蚀，可采用微电子常规干法或湿法刻蚀工艺，包括但不限于反应离子刻蚀(RIE)、等离子刻蚀(ICP)、化学溶液腐蚀(SC-1溶液腐蚀)等。
由于横向尺寸越小，介电常数和铁电剩余极化强度越大，为得到巨介电常数和巨铁电极化的介质薄膜，可调整每个微结构的横向尺寸为1nm～1μm。
为促使介质薄膜中低介电常数相向高介电常数相转变，，还可以将形成微结构后的器件进行快速高温退火处理。退火工艺包括但不限于管式炉退火、快速热退火(RTP)、高压金属化后退火(HPPMA)、微波退火(MVA)、激光退火等。一些实施例中，所述退火在氮气、氩气等保护气氛中进行，退火温度为300℃～900℃，退火时间为1s～8h。
一些实施例中，退火工艺的保护气氛为氮气，退火温度为500℃～600℃，时间35s～2h，一些实施例中，采用快速高温退火，退火时间为30s～60s。
所述介质薄膜的厚度优选为0.5nm～50nm。在实际应用于，可以在该厚度范围内适当增加介质薄膜的厚度，从而得到更低的漏电流，更小的操作电压，信息保持时间更长，读 写次数更高，扩宽了本发明的超高介电常数介质薄膜的应用范围。
一些实施例中，为了进一步提高介质薄膜的介电常数，还可以在衬底上形成的HZO薄膜的过程中，通过优化HZO薄膜的制备工艺，提高高介电常数O相含量。该HZO薄膜的制备工艺包含但不限制于溶胶凝胶法、溅射沉积法、脉冲激光沉积法、金属有机化学气相沉积法、原子层沉积、离子束蒸发法等。
为进一步提高HZO薄膜的性能，所述HZO薄膜通过原子层沉积，在制备完成后，还采用金属化后热退火处理。
所述HZO薄膜包含：由HfO 2和ZrO 2交替生长形成叠层结构的HZO薄膜，或Hf 1-xZr xO 2复合薄膜，或其他离子掺杂的Hf 1-xZr xO 2复合薄膜。
所述HZO薄膜还可以掺杂包含但不限于Si、Er、Y、Al等中的一种或以上元素，掺杂浓度为0-50mol％。
一些实施例中，所述介质薄膜还包含：其他介电材料。也就是说，所述HZO薄膜可以单独使用，也可以与其他电介质材料叠层组合使用，以提高叠层介电薄膜的介电常数，可应用于CMOS栅介质材料、DRAM或其他超级电容器。一些实施例中，其他介电材料可以是低k介电材料层，如SiO 2、Si 3N 4等。
一些实施例中，该方法还包含：对步骤d退火处理后的器件施加正负电脉冲，进一步促使介质薄膜中低介电常数相向高介电常数相转变。
所述衬底可以是硅衬底，也可以是附有SiO 2的硅衬底，或其他常规衬底。
所述第一电极、第二电极材料可以选择但不限于TiN、W、Al、n/p-Si、PtSi、Mo、Cu、Co、Ta、Ru、Ir、Ti、Cr等中任意一种或以上。
采用上述方法，本发明提供了一种具有超高介电常数和/或铁电剩余极化强度的介质薄膜和器件。所述超高介电常数和铁电剩余极化强度的介质薄膜采用上述离子注入、刻蚀成孤岛状微结构、退火、正负脉冲等任意一种以上方式处理过。所述器件包含依次叠层设置的：衬底、超高介电常数和铁电剩余极化强度的介质薄膜、第一电极；所述第一电极包含若干离散的微结构，或，所述第一电极和所述的介质薄膜均包含若干离散的微结构；每个微结构的横向尺寸为1nm～50μm。
一些实施例中，所述衬底上附有第二电极，其位于衬底与所述介质薄膜之间。
所述器件包含：超级电容器、CMOS器件、动态随机读写存储器(DRAM)、电荷捕获存储器件、三维堆叠闪存(3D NAND)、非易失性铁电存储器(FRAM或FeFET)中任意一种或任意两种以上。
以下通过实施例1刻蚀不同横向尺寸的第一电极，并对电极的边缘区域进行离子注入，结合高温快速退火，促使HZO介质薄膜中低介电常数相向高介电常数相转变，用于 验证电容器的第一电极的横向尺寸对介质薄膜的介电常数和铁电剩余极化强度的影响。
实施例1
如图1所示，为一种TiN-HZO-TiN电容器的制备状态示意图。
首先，提供TiN-HZO-TiN薄膜三明治结构：采用原子层沉积法在带有TiN电极(第二电极102B)的Si衬底101上制备出HZO薄膜103(可以是晶体或非晶薄膜)，随后采用物理气相沉积工艺生长一层TiN作为第一电极102A。
步骤S1，在第一电极102A表面旋涂光刻胶，通过光学曝光或电子束曝光等方式，形成不同尺寸的正方形图形，随后采用热蒸发工艺生长一层金属Cr，并通过lift-off工艺剥离掉未曝光区域的金属Cr，剩下正方形图形区域覆盖Cr掩膜104。
步骤S2，采用反应离子刻蚀工艺(RIE)将没有Cr掩膜104覆盖区域的第一电极102A去除，并对电极边缘区域的HZO进行了活性离子105注入，剩余Cr掩膜104覆盖区域的第一电极102A与第二电极102B形成尺寸不等(200nm～50μm)的TiN-HZO-TiN电容器。
步骤S3，通过湿法腐蚀的方法将Cr掩膜去除，随后采用快速热退火工艺将样品放置在N 2气氛中，在500℃～600℃温度下退火30s～60s，制备得到包含超高介电常数和铁电剩余极化强度的介质薄膜的电容器。
本例中，所述HZO薄膜为Hf 0.5Zr 0.5O 2薄膜。将TiN/Hf 0.5Zr 0.5O 2/TiN三明治结构薄膜的第一电极TiN刻蚀成孤岛正方形图案，与第二电极TiN形成尺寸大小不等的电容器结构，并对电极边缘区域的HZO薄膜进行了活性离子(本例中为O 2-、S 6+和F -)注入，注入总剂量约为10 16ions/cm 2；然后在550℃快速退火40s，其中，Hf 0.5Zr 0.5O 2膜厚为10nm，并测量其介电常数和损耗随频率的变化。
如图2a、图2b所示，分别展示了采用实施例1的方法所制备的不同尺寸的TiN/HZO/TiN薄膜电容器的介电常数和损耗随频率(f)的变化。发现第一电极横向尺寸越小，介电常数越大，尺寸为5.2μm时介电常数可大于100(图2a)，在1MHz频率下，当第一电极横向尺寸从32μm缩减到5.2μm时，介电常数从30单调增加到132，证明第一电极尺寸的缩小能够有效地提高HZO薄膜的介电常数。同时在20kHz附近出现一个很宽的介电损耗峰(图2b)。当对第一电极横向尺寸分别为4.4μm和5.4μm电容器连续施加±4V/500ns矩形电脉冲，施加脉冲数分别为1.01×10 7和4.16×10 7后，发现疲劳后(fatigued)的电容器的铁电剩余极化强度突然减小为0，同时样品的介电常数急剧增大，1MHz是分别为921和597(图2a)，即产生了巨介电效应，同时20kHz附件的介电损耗峰也随之消失(图2b)。可见，利用器件尺寸效应，结合外加电脉冲的激励，可促进Hf 1-xZr xO 2薄膜低介电常数相向高介电常数相稳步转变，使得4.4μm尺寸的电容器在1MHz介电常数从 原先30显著增大至921。
一些实施例中，还对实施例1中图1所示流程制备的电容器施加正负电脉冲，进一步促使低介电常数相向高介电常数相转变，使得HZO薄膜拥有巨介电常数。其中，产生巨介电常数的电容器结构为TiN/HZO/TiN，HZO薄膜的膜厚为10nm，第一电极TiN横向尺寸小于10μm，介电常数为800～1400，O相含量为38％。
如图3a-3c展示了采用施加电脉冲技术也可以诱发采用图1所示流程制备出小尺寸电容器中所出现的巨介电效应，证明了本发明的处理方法得到的超高介电常数介质薄膜可应用于高密度能量存储。本例中，将另一TiN/Hf 0.5Zr 0.5O 2/TiN薄膜的第一电极TiN刻蚀成不相连的横向尺寸为4.4μm的正方形图案，对电极边缘区域的HZO薄膜进行了离子注入(本例中为O 2-、S 6+和F -)，注入剂量为10 16ions/cm 2，然后在550℃快速退火60s，然后施加±4V/500ns电脉冲，频率为1MHz，同时测量D-E铁电电滞回线随施加脉冲数的变化(图3a)，发现当施加脉冲数为1.01×10 7时，铁电电滞回线突然蜕变为一个线性电介质回线，即铁电性消失，促使薄膜中低介电常数相向高介电常数相转变，同时产生了巨介电效应。图3b显示横向尺寸分别为4.4μm和5.4μm电容器铁电剩余极化强度随施加脉冲数的变化，在1.01×10 7和4.16×10 7周期数后分别降为0。以上实验结果预示了电容器尺寸越小，产生巨介电所施加的电脉冲周期数会越少，同时介电常数越大。图3c显示尺寸分别为4.4μm和5.4μm疲劳后电容器的能量存储密度随外加电场的变化，证明外加电场绝对值越大，存储能量密度越大。
图4a-4c展示采用电脉冲技术诱发巨介电效应前后(施加电脉冲前后)电容器中充电电荷密度的变化。图4a显示采用实施例1的方法制备的尺寸为4.4μm的TiN/Hf 0.5Zr 0.5O 2/TiN电容器的测量等效电路，HZO电容器与一个1MΩ电阻串联，施加电脉冲宽度为5ms，外加电压(V)从0.2V逐渐增大到2V，步长为0.2V。图4b、图4c分别显示该电容器施加电脉冲前后的充电电流随时间变化，图4b代表施加电脉冲之前，图4c代表施加电脉冲之后。通过以上电流对时间的积分，得出充电电荷密度(P nsw)随外加电压的变化。从以上曲线的实线的拟合斜率，计算出疲劳前后(施加电脉冲前后)的介电常数的变化相差约6倍，证明施加电脉冲可以大幅提高电容器的充电电荷密度。
图5a-5c展示了在采用电脉冲技术诱发巨介电效应后电容器中充电电荷密度随外加电压的变化。图5a为采用实施例1的方法制备的尺寸为4.4μm的TiN/Hf 0.5Zr 0.5O 2/TiN电容器的测量等效电路，HZO电容器与一个100Ω电阻串联，施加电脉冲宽度为100ns，外加电压(V)从0.2V逐渐增大到2V，步长为0.2V。图5b显示该电容器疲劳后的充电电流随时间变化，其充电电流明显高于图4b。通过电流对时间的积分，得出不同电压下电容器充电的电荷密度(P nsw)。图5c显示该电容器的充电电荷密度随充电周期数增多仍趋于稳 定，其中，外加矩形脉冲电压/脉宽为+/-1.2V/50ns，重复周期为10MHz。1.2V时电荷密度可达100μC/cm 2，且随充放电次数稳定至10 12，没有引起电击穿，证明其可应用于DRAM等领域，能够提高存储单元的可缩微性(<10nm)。在实际应用中，还可以适当增加介质薄膜的厚度，从而得到更低的漏电流，更小的操作电压，信息保持时间更长，读写次数更高。
图6a-6c为疲劳前后介质薄膜晶体结构的高分辨透射电镜成像分析，展示采用电脉冲技术诱发巨介电效应前后介质薄膜晶体结构的变化。图6a为采用图1的方法制备的尺寸为5.7μm的TiN/HZO/TiN电容器结构的HZO晶体薄膜中典型O相晶粒的高角度环形暗场扫描透射电子显微镜(HAADF-STEM)成像分析，发现疲劳前该O相晶粒内嵌低介电常数的M相薄片，导致薄膜整体介电常数大幅降低，铁电剩余极化强度为6.17μC/cm 2(见图6c中的左图)。图6b为疲劳后(施加电脉冲后)HZO晶体薄膜中典型O相晶粒的HAADF-STEM成像图，显示该O相晶粒内嵌的低介电常数的M相消失，全部转化为O相，铁电剩余极化强度为0μC/cm 2(见图6c中的右图)，导致薄膜整体介电常数急剧增大，并产生了巨介电效应。如图6b’所示，疲劳后O相晶粒的傅里叶变换后电子衍射斑显示均呈正交相(即O相)。图6c为疲劳前后介质薄膜的样品组分分析对比图，通过对33％可识别晶粒主晶相含量测量，发现疲劳前后样品中O相为主的晶粒含量基本不发生变化，始终保持在38％左右水平。可以证明，经施加电脉冲可以使得O相为主的晶粒纯度提升，即，其中的M相转化为O相。
以下结合实施例2证明可通过刻蚀第一电极102A和HZO薄膜103叠层的横向尺寸来调控HZO薄膜中O相占比，促使薄膜中低介电常数相向高介电常数相转变。
实施例2
如图7所示，为另一种TiN-HZO-TiN电容器的制备状态示意图。除了步骤S2刻蚀TiN/HZO叠层，其他步骤均与实施例1相同。
本实施例中，首先，在硅衬底上生长TiN/Hf 0.5Zr 0.5O 2/TiN三明治结构的薄膜，然后将TiN/HZO叠层刻蚀成小于10μm尺寸的孤立电容器结构，然后在氮气气氛中快速热退火(550℃)50s，随后使用SC-1号清洗液腐蚀掉顶部TiN电极(第一电极)。采用波长为
Figure PCTCN2022124854-appb-000005
同步辐射光源，在0.45 °掠入射下测量不同尺寸的HZO晶体薄膜的X射线衍射测试结果如图8所示，连续HZO晶体薄膜主要有T相和O相组成，没有M相。通过对2θ＝24.24 °和24.51 °的O(111)和T(011)衍射峰的高斯拟合，得出O相含量的百分比。刻蚀成不同尺寸电容器后，随着HZO晶体薄膜横向尺寸的缩小，O相晶粒占比显著增加。当尺寸缩减到300nm时，O相的比例可高达99％，HZO晶体薄膜中T相几乎全部转化成了O相。当电容器尺寸小于300nm时，低介电常数四方/单斜相能够全部转化为正交相， HZO晶体薄膜中O相含量接近100％，HZO晶体薄膜的介电常数可大于2400。可见，通过离子注入、缩减第一电极和HZO薄膜的横向尺寸和快速退火工艺，能够有效地提高HZO的介电常数和铁电极化强度。
一些实施例中，还通过离子注入提高铁电剩余极化强度。使用等离子刻蚀机将未经退火的非晶或晶体氧化铪薄膜电容器刻蚀成孤立的电容器。使用SF 6和O 2混合气氛，在50～100w的功率下刻蚀1～5min，在反应离子的轰击下，大量的活性离子注入到电极边缘的HZO薄膜中，然后将整个电容器在550℃下快速退火30s，小尺寸的HZO薄膜电容器不仅出现了很高的介电常数，而且呈现出很高的铁电剩余极化强度。
图9a-9c展示了本实施例的TiN/HZO/TiN叠层电容器内剩余极化强度随着HZO薄膜横向尺寸减小急剧增大，0.3μm时可达404μC/cm 2(图9a)，是常规HZO的极化强度20倍以上，可应用于非易失铁电存储器，能够显著提高存储器读出电荷数或信息存储密度。图9b显示在施加-/+3V写入电压后，存储器在不同读电压下读出电流随时间变化，读出电压改变的步长为0.2V。通过对以上读出电流对时间的积分即可以计算出在不同读电压下所得到的电畴反转极化强度(P sw)和电畴不反转极化强度(P nsw)。图9b显示在信息“1”和“0”写入后所得到的3V读电压下P sw和P nsw随保持时间的变化关系，从P sw和P nsw的差别可以识别TiN/HZO/TiN电容器内所存储的逻辑“1”和“0”的信息。
因此，本发明所提供的超高介电常数和铁电极化强度的介质薄膜，可应用于高密度集成的非易失性/易失性存储器和超大规模逻辑器件，具有低电压操作等优点。
实施例3
如图10所示，为一种TiN-HZO栅介质层的制备状态示意图。本例中，Si衬底101上不带有TiN下电极(第二电极102B)，直接在Si衬底101上制备出HZO薄膜103，其呈非晶态。然后，对整个HZO薄膜进行了离子注入(本例中为O 2-、S 6+和F -)，注入剂量为10 16ions/cm 2。随后采用物理气相沉积工艺生长一层TiN作为第一电极102A。
步骤S1，在第一电极102A表面旋涂光刻胶，通过光学曝光或电子束曝光等方式，形成不同尺寸的正方形图形，随后采用热蒸发工艺生长一层金属Cr，并通过lift-off工艺剥离掉未曝光区域的金属Cr，剩下正方形图形区域覆盖Cr掩膜104。采用实施例1同样的步骤S1-S3，将第一电极102A刻蚀成离散的微结构，得到TiN-HZO栅介质层。
步骤S2，采用反应离子刻蚀工艺(RIE)将没有Cr掩膜104覆盖区域的第一电极102A去除，将第一电极102A刻蚀成离散的微结构，得到TiN-HZO栅介质层。
步骤S3，通过湿法腐蚀的方法将Cr掩膜去除，随后采用快速热退火工艺将样品放置在N 2气氛中，在500℃～600℃温度下退火30s～60s，制备得到包含超高介电常数和铁电剩余极化强度的介质薄膜的电容器。
实施例4
如图11所示，为另一种TiN-HZO栅介质层的制备状态示意图。本例中，Si衬底101上不带有TiN下电极(第二电极102B)，直接在Si衬底101上制备出HZO薄膜103。随后采用物理气相沉积工艺生长一层TiN作为第一电极102A。
步骤S1-S3同实施例3，只是将第一电极102A及HZO薄膜全部刻蚀为离散的微结构，得到TiN-HZO栅介质层。
利用超薄和超高介电常数的HZO栅介质材料为未来硅晶体管提供了一个可替代的新材料和新器件的方向，颠覆现有传统高k电介质材料物性，对整个微电子产业产生重大影响。与相同
Figure PCTCN2022124854-appb-000006
厚度的其他传统堆叠电介质HfO 2、AFE-ZrO 2、FE-Zr:HfO 2相比，本发明的超高介电常数的介质薄膜显示出超高的比电容和电荷存储密度，能够有效地降低DRAM和CMOS器件的操作电压和漏电流。
实施例5
采用实施例1相同的方法，只是在第二电极102B上形成HZO薄膜103后，还形成了低介电常数Si 3N 4薄膜106，采用物理气相沉积工艺生长一层TiN作为第一电极102A。本例中，所述介质薄膜包含HZO薄膜及Si 3N 4薄膜，制备得到的电容器为TiN/HZO/Si 3N 4/TiN叠层电容器，如图12a所示。
图12a、图12b演示采用超高介电常数/低介电常数的TiN/HZO/Si 3N 4/TiN叠层电容器在正负写入电场下实现对电子或空穴的有效捕获，证明本发明的方法处理后的HZO薄膜与低介电常数材料的组合可应用于信息的非易失性存储，大大地降低了擦写电压，如可用于电荷捕获型存储器。
为进一步提高对捕获电荷的锁存能力，一些实施例中，在实施例5中低介电常数Si 3N 4薄膜105上再沉积一层HZO薄膜，得到TiN/HZO/Si 3N 4/HZO/TiN多叠层电容器，如图13所示。
综上所述，本发明通过微电子器件刻蚀工艺，结合活性离子注入、尺寸效应和外加电脉冲，可将具有纳米厚度的第一电极或第一电极与介质薄膜的叠层刻蚀成孤立的电容器，从而产生巨介电效应(k>900)和巨铁电效应(剩余极化强度>400μC/cm 2)，突破了传统超薄膜材料的介电常数的限制(≤52)。运用以上具有超高介电常数的介质薄膜，抑制短沟道效应和漏电流影响；在现有工艺条件下，能够将DRAM单元尺寸轻易缩小至10nm以下技术节点，提高器件的可缩微性，存储密度至少扩大了10倍以上，降低了漏电流。
本发明的超高介电常数介质薄膜还可与其他低介电常数材料(SiO 2，Si 3N 4等)叠合在一起，能够有效地增强电荷捕获功能，形成非易失电荷捕获存储器，能够显著地提高电荷捕获效率，大幅降低擦写电压，延长存储器擦写寿命，可应用于3D NAND。3D NAND 闪存中每个器件都是金属-Al 2O 3-氮化物-氧化硅电荷捕获器件，具有TiN/W金属栅极和多晶硅沟道。对于高密度集成，沟道孔的直径受到限制，阻挡层的物理厚度由于有限的沟道孔直径而不能增加，因此使用高k电介质具有缩小EOT的优势。通过在阻挡层中采用高介电常数HZO层增大电容来增强其性能，可以提供更大的存储窗口和更高的操作速度。此外，本发明的超高介电常数介质薄膜在电荷捕获存储器中的应用不会影响保持特性，因为超高k的HZO晶体薄膜中可以不存在铁电剩余极化。通过使用超高介电常数HZO晶体薄膜，能够增强电荷捕获存储器中的电容升压效应，从而提高3D NAND器件性能，降低了擦写电压，延长了器件使用寿命。
本发明通过离子注入、尺寸效应和微电子工艺提高铁电剩余极化强度，离子注入和尺寸效应可引起超高介电常数的HZO晶体薄膜材料电容器内剩余极化强度随着尺寸减小急剧增大，0.3μm时可达404μC/cm 2，是常规HZO的极化强度20倍以上，可应用于金属/HZO/金属架构的非易失铁电存储器，能够显著提高存储器的读出电荷数或信息存储密度。
本发明的超高介电常数介质薄膜作为电容器存储介质材料也可以应用于超级电容器，提高能量存储密度。电介质电容器广泛应用于众多领域，例如具有各种功能(滤波、耦合、去耦等)的电子电路、微波通信、混合动力汽车、分布式电力系统、可再生能源存储以及聚变等大功率应用，不同的应用需要具有不同的特征种类的电容器。例如，用于微波通信应用的电容器应具有非常高的品质因数(极低的介电损耗)，而用于去耦电路的电容器则要求具有每单位体积的大电容。然而，电介质电容器较低的能量密度限制了其实际应用。
本发明可以应用于互补金属氧化物半导体CMOS中的栅极绝缘层，可以将CMOS器件尺寸缩小至5nm以下，大幅降低了工作电压(<1V)，减小了短沟道效应和漏电流，可适用于3-5nm以下技术节点CMOS器件制造工艺。随着大数据和信息化的发展，对器件尺寸缩小提出了更高的要求。传统上，一般采用二氧化硅(SiO 2)作为栅极绝缘层材料，随着CMOS中的栅极绝缘层的厚度不断减小，超薄的SiO 2无法抑制隧穿电流的产生。HZO作为一种超高k材料，可在更薄的厚度或者厚度不变的条件下有效抑制隧穿电流。同时，超高介电常数HZO可以增加栅极电容，以保持对沟道内载流子的有效控制，并降低工作电压。原子层沉积(ALD)生长的HZO超高k薄膜材料克服了困扰传统钙钛矿基铁电材料的兼容性问题。此外，HZO薄膜的厚度可以缩小至1nm以下，有助于集成到最先进的大规模器件中。同时，HZO/Si异质结具有良好的热力学稳定性和良好的晶格匹配特性。
尽管本发明的内容已经通过上述优选实施例作了详细介绍，但应当认识到上述的描述不应被认为是对本发明的限制。在本领域技术人员阅读了上述内容后，对于本发明的多种修改和替代都将是显而易见的。因此，本发明的保护范围应由所附的权利要求来限定。

Claims (15)

  1. 一种具有超高介电常数和/或铁电剩余极化强度的介质薄膜和器件的制备方法，其特征在于，该方法包含：
    步骤a，在衬底上或附有第二电极的衬底上形成介质薄膜；所述介质薄膜包含Hf 1-xZr xO 2薄膜，其为晶体或非晶态薄膜；其中，0≤x≤1；
    步骤b，在所述介质薄膜上形成第一电极；
    步骤c，将第一电极分割为若干离散的微结构，每个微结构的横向尺寸为1nm～50μm；
    步骤d，退火处理，使得所述介质薄膜中低介电常数相减少，高介电常数相增加，介质薄膜平均介电常数大于100。
  2. 如权利要求1所述的具有超高介电常数和/或铁电剩余极化强度的介质薄膜和器件的制备方法，其特征在于，在步骤b之前和/或在步骤c之后，将活性离子注入到所述介质薄膜中。
  3. 如权利要求2所述的具有超高介电常数和/或铁电剩余极化强度的介质薄膜和器件的制备方法，其特征在于，所述活性离子包含碳、氮、氧、硼、氦、磷、铁、铝、锌、钴、锡、镍、钛、硅、磷、氩、氯、溴、硫、碘、氟、氢、银、金、铜、铂中任意一种或两种以上；所述活性离子的注入剂量为10 10-10 20ions/cm 2。
  4. 如权利要求1所述的具有超高介电常数和/或铁电剩余极化强度的介质薄膜和器件的制备方法，其特征在于，还将所述介质薄膜分割为离散的微结构。
  5. 如权利要求1或4所述的具有超高介电常数和/或铁电剩余极化强度的介质薄膜和器件的制备方法，其特征在于，所述分割包含刻蚀。
  6. 如权利要求1或4所述的具有超高介电常数和/或铁电剩余极化强度的介质薄膜和器件的制备方法，其特征在于，每个微结构的横向尺寸为1nm～1μm。
  7. 如权利要求1所述的具有超高介电常数和/或铁电剩余极化强度的介质薄膜和器件的制备方法，其特征在于，所述退火处理的温度为300℃～900℃，退火处理时间为1s～8h。
  8. 如权利要求1所述的具有超高介电常数和/或铁电剩余极化强度的介质薄膜和器件的制备方法，其特征在于，该方法还包含：对退火处理后的器件施加正负电脉冲。
  9. 如权利要求1所述的具有超高介电常数和/或铁电剩余极化强度的介质薄膜和器件的制备方法，其特征在于，所述介质薄膜的厚度为0.5nm～50nm。
  10. 如权利要求1所述的具有超高介电常数和/或铁电剩余极化强度的介质薄膜和器件的 制备方法，其特征在于，所述Hf 1-xZr xO 2薄膜还掺杂有Si、Er、Y、Al元素中的至少一种，掺杂浓度为0-50mol％。
  11. 如权利要求1所述的具有超高介电常数和/或铁电剩余极化强度的介质薄膜和器件的制备方法，其特征在于，所述Hf 1-xZr xO 2薄膜的制备方法包含溶胶凝胶法、溅射沉积法、脉冲激光沉积法、金属有机化学气相沉积法、原子层沉积、离子束蒸发中的至少一种。
  12. 如权利要求1所述的具有超高介电常数和/或铁电剩余极化强度的介质薄膜和器件的制备方法，其特征在于，所述介质薄膜还包含：低k介电材料层，该低k介电材料层与所述Hf 1-xZr xO 2薄膜叠合使用。
  13. 如权利要求1所述的具有超高介电常数和/或铁电剩余极化强度的介质薄膜和器件的制备方法，其特征在于，该方法还包含：对退火处理后的器件进行处理，去除第一电极和衬底，得到具有超高介电常数和/或铁电剩余极化强度的介质薄膜。
  14. 一种采用权利要求1-12中任意一项所述的制备方法制备的器件，其特征在于，该器件包含：衬底或附有第二电极的衬底、介质薄膜、第一电极；
    所述介质薄膜包含Hf 1-xZr xO 2薄膜，其为晶体或非晶态薄膜；其中，0≤x≤1；
    所述第一电极包含若干离散的微结构，或，所述第一电极和所述的介质薄膜均包含若干离散的微结构；每个微结构的横向尺寸为1nm～50μm。
  15. 如权利要求14所述的器件，其特征在于，所述器件包含：超级电容器、CMOS器件、动态随机读写存储器(DRAM)、电荷捕获存储器件、三维堆叠闪存(3D NAND)、非易失性铁电存储器(FRAM或FeFET)中任意一种或任意两种以上。
PCT/CN2022/124854 2022-09-30 2022-10-12 具有超高介电常数和/或铁电剩余极化强度的介质薄膜和器件的制备方法及器件 WO2024065881A1 (zh)

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