WO2021143187A1 - 非对称的铁电功能层阵列、铁电隧道结多值存储单元的制备方法 - Google Patents
非对称的铁电功能层阵列、铁电隧道结多值存储单元的制备方法 Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
- H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
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- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5657—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using ferroelectric storage elements
Definitions
- the invention belongs to the field of microelectronic devices, and particularly relates to an asymmetric ferroelectric functional layer array, an asymmetric ferroelectric tunnel junction multi-value storage unit, a memory and a preparation method thereof.
- Ferroelectric materials are used in the storage field because of their inherent advantages such as fast erasing and writing speed, ultra-low power consumption, large number of cycles, and non-volatile polarization state.
- New types of non-volatile such as FRAM, FeFET and FTJ based on ferroelectric materials sexual memory has received extensive attention.
- the FTJ memory modulates the interface barrier height of the insulating layer by the direction of the ferroelectric polarization to realize the switchable rectification function to realize the switching of high and low resistance states.
- FTJ memory not only has the inherent advantages of ferroelectric memory, such as fast erasing and writing speed, ultra-low power consumption, many cycles, and non-volatility. Compared with FRAM and FeFET, it also has smaller size, simple structure, non-destructive readout, etc. Advantage.
- FTJ memory based on MFIM structure (ie metal-ferroelectric functional layer-insulating layer-metal), compared with MFM structure (ie metal-ferroelectric functional layer-metal) FTJ devices, between the ferroelectric functional layer and the metal electrode A layer of insulating tunneling layer is inserted, which well solves the dielectric shielding effect and depolarization problems caused by the metal electrode.
- the MFIM structure uses the insulating layer as the tunneling layer instead of the ferroelectric functional layer as the tunneling layer, which reduces the requirement for the thickness of the ferroelectric functional layer.
- the use of a thicker ferroelectric functional layer can also achieve the tunneling effect, which is great To a certain extent, the process difficulty and manufacturing cost of preparing the FTJ memory are reduced.
- MFIM-based memories are mostly used in binary memories.
- the principle is that the ferroelectric functional layer exhibits stable polarization in the same direction by applying an electric field. After the applied electric field is removed, since the residual polarization intensity is not 0, the polarization electric field generated by the polarization charge will be caused. The polarization electric field will increase the band energy of the ferroelectric functional layer or reduce the energy of the ferroelectric functional layer. Bring energy.
- the present invention provides a device that can have a number of advantages.
- one aspect of the present invention provides a method for preparing an asymmetric ferroelectric functional layer array.
- the asymmetric ferroelectric functional layer array is formed by alternately stacking N ferroelectric functional layers and N-1 insulating layers. The method includes the following steps:
- An electrode layer is provided, and N ferroelectric functional layers parallel to the first plane direction are grown on the upper surface of the electrode layer, and the adjacent ferroelectric functional layers are separated by an insulating layer, including: Forming an i-th ferroelectric functional layer on the upper surface; forming a j-th insulating layer on the upper surface of the i-th ferroelectric functional layer; forming an (i+1)-th ferroelectric functional layer on the upper surface of the j-th insulating layer;
- the physical parameters during the formation process of the N ferroelectric functional layers are different, so that the N ferroelectric functional layers exhibit different coercive field values
- N is an integer greater than or equal to 2
- the physical parameters include at least one of the following: the type of the ferroelectric functional layer material, the doping mode of the ferroelectric functional layer material, the crystallization condition of the ferroelectric functional layer, and the thickness of the ferroelectric functional layer material.
- a second aspect of the present invention provides a method for manufacturing a multi-value memory cell of an asymmetric ferroelectric tunnel junction, the method comprising:
- An asymmetric ferroelectric functional layer array is formed on the upper surface of the first electrode layer, which includes: N ferroelectric functional layers parallel to the first plane direction, and an insulating layer is passed between adjacent ferroelectric functional layers isolate;
- the method for forming the asymmetric ferroelectric functional layer array includes:
- a first electrode layer is provided, and N ferroelectric functional layers parallel to the first plane direction are grown on the upper surface of the first electrode layer, and the adjacent ferroelectric functional layers are separated by an insulating layer, including: Forming an i-th ferroelectric functional layer on the upper surface of the electrode layer; forming a j-th insulating layer on the upper surface of the i-th ferroelectric functional layer; forming an (i+1)-th ferroelectric function on the upper surface of the j-th insulating layer Floor;
- the physical parameters during the formation process of the N ferroelectric functional layers are different, so that the N ferroelectric functional layers exhibit different coercive field values
- N is an integer greater than or equal to 2
- the physical parameters include at least one of the following: the type of the ferroelectric functional layer material, the doping mode of the ferroelectric functional layer material, the crystallization condition of the ferroelectric functional layer, and the thickness of the ferroelectric functional layer material.
- the method includes:
- a method of atomic layer deposition, physical vapor deposition or spin coating is used to alternately grow N ferroelectric functional layers and N-1 insulating layers on the upper surface of the first electrode layer.
- a physical vapor deposition method is used to form a second electrode layer on the upper surface of the asymmetric ferroelectric functional layer array.
- the preparation materials of the N ferroelectric functional layers are selected from doped or undoped HfO 2 , Hf x Zr 1-x O 2 , BiFeO 3 , BaTiO 3 , Pb(Zr 1-x Ti x ) At least one of O 3 , Sr x Ba 1-x O 3 , and polyvinylidene fluoride, and the thickness thereof is 2-20 nm.
- the preparation material of the N-1 insulating layers is selected from at least one oxide of Al, Si, Hf, Zr, Ta, and Ti, and the thickness thereof is 0.5-3 nm.
- the preparation material of the first and second electrode layers is selected from at least one of polysilicon, Al, TiN, TaN, W, Ni, Ta, SrRuO3, and Nd:SrTiO3, and the thickness of the two is 10-200nm.
- the third aspect of the present invention provides a multi-value memory cell with an asymmetric ferroelectric tunnel junction, which is prepared by using the above-mentioned preparation method;
- the N ferroelectric functional layers have different coercive field values, so that the N ferroelectric functional layers exhibit different polarization differences under excitation.
- the fourth aspect of the present invention provides a method for preparing a multi-value memory cell of an asymmetric ferroelectric tunnel junction, characterized in that the method includes:
- first ferroelectric functional layer on the upper surface of the first electrode layer by means of atomic layer deposition, physical vapor deposition or spin coating;
- Forming a first insulating layer on the upper surface of the first ferroelectric functional layer by using atomic layer deposition, physical vapor deposition or spin coating;
- the physical parameters during the formation process of the first and second ferroelectric functional layers are different, so that the two exhibit different coercive field values.
- the physical parameters include at least one of the following: the type of the ferroelectric functional layer material, the doping mode of the ferroelectric functional layer material, the crystallization condition of the ferroelectric functional layer, and the thickness of the ferroelectric functional layer material.
- the preparation materials of the first and second ferroelectric functional layers are selected from doped or undoped HfO2, Hf x Zr 1-x O 2 , BiFeO 3 , BaTiO 3 , Pb(Zr 1-x Ti x )O 3. At least one of Sr x Ba 1-x O 3 and polyvinylidene fluoride, with a thickness of 2-20 nm;
- the preparation material of the first insulating layer is selected from at least one oxide of Al, Si, Hf, Zr, Ta, and Ti, and the thickness thereof is 0.5-3 nm;
- the preparation material of the first and second electrode layers is selected from at least one of polysilicon, Al, TiN, TaN, W, Ni, Ta, SrRuO3, and Nd:SrTiO3, and the thickness of the two is 10-200nm.
- a multi-value memory cell with an asymmetric ferroelectric tunnel junction is provided, which is prepared using the above-mentioned manufacturing method;
- the coercive field value of the first ferroelectric functional layer is different from that of the second ferroelectric functional layer, so that the first and second ferroelectric functional layers exhibit different polarization differences under excitation.
- a sixth aspect of the present invention provides a multi-value memory with an asymmetric ferroelectric tunnel junction, including the above-mentioned asymmetric ferroelectric tunnel junction multi-value memory cell.
- the multi-value memory based on the asymmetric ferroelectric tunnel junction adds multiple modulation insulating tunneling layer barriers by inserting a multilayer ferroelectric functional layer and an insulating layer between metal electrodes Variable of height.
- the polarization directions of multiple ferroelectric functional layers can be modulated by applying pulses of different magnitudes and directions, thereby modulating the height of the tunneling layer barrier, and realizing a variety of different storage states.
- the modulation method based on ferroelectric polarization flip has the advantages of fast speed and low power consumption.
- the ferroelectric material storage device prepared thereby has the characteristics of non-volatility and low reading power consumption; at the same time, a variety of different types can be realized in a memory cell.
- the storage status can greatly increase the storage density and unit storage capacity;
- the manufacturing method of the multi-value memory based on the asymmetric ferroelectric tunnel junction provided by the present invention is compatible with the CMOS process through the use of different doping methods, or different ferroelectric materials, or the same
- the ferroelectric material is annealed at different temperatures or the same ferroelectric material is used but different thicknesses are used to realize the different coercive fields of the multilayer ferroelectric functional layer, the method is simple and the operability is strong;
- the application of the multi-value memory based on the asymmetric ferroelectric tunnel junction provided by the present invention uses the device to have a variety of different storage states in a memory cell, as well as fast, low power consumption, and non-volatile Advantages, it can be applied to low-power multi-value memory chips, memory computing chips, etc., and has great application prospects in the Internet of Things, information processing and other fields.
- FIG. 1 is a schematic diagram of the structure of a multi-value memory cell of an asymmetric ferroelectric tunnel junction implemented according to the present invention
- FIG. 2 is a schematic diagram of the structure of a preferred asymmetric ferroelectric tunnel junction multi-value memory cell implemented according to the present invention
- FIG. 3 is a simulation diagram of the remanent polarization of the ferroelectric layer in different states of the multi-value memory cell of the asymmetric ferroelectric tunnel junction according to the first embodiment of the present invention
- the same reference numerals are used to denote the same elements or structures, among which: the first electrode layer-1, the asymmetric ferroelectric functional layer array-11, the second electrode layer-5, the first ferroelectric layer Functional layer-2, first insulating layer-3, second ferroelectric functional layer.
- the ferroelectric material itself can undergo polarization reversal under the action of external excitation, and the internal polarization state has a nonlinear relationship with the external excitation, and due to the polarization orientation, there are two stable opposite polarization states;
- the resulting tunnel junction of the ferroelectric material (“metal-ferroelectric functional layer-insulating layer-metal" structure), which can adjust the ferroelectric function by applying external excitation to produce different polarization states of the ferroelectric functional layer
- the level of the tunneling barrier at the interface between the layer and the insulating layer can be adjusted to control the amount of charge that can be tunneled, forming two resistance states: high and low. Therefore, the present invention proposes an asymmetric ferroelectric tunnel junction multi-value memory cell and a preparation method thereof based on the good storage characteristics of the single-layer ferroelectric tunnel junction.
- the first aspect of the present invention provides an asymmetric ferroelectric tunnel junction multi-value memory cell, which includes a first electrode layer 1, an asymmetric ferroelectric functional layer array 11, and an asymmetric ferroelectric functional layer array from bottom to top in the longitudinal direction.
- the second electrode layer 5 The second electrode layer 5.
- the asymmetric ferroelectric functional layer array 11 is composed of N ferroelectric functional layers parallel to the lateral plane, and two adjacent ferroelectric functional layers are separated by an insulating layer, that is, by N ferroelectric functional layers.
- the electrical function layer and N-1 insulating layers are stacked alternately, and the tunnel junction of the entire ferroelectric material is "metal-first ferroelectric function layer-first insulating layer-second ferroelectric function" from bottom to top along the longitudinal plane direction.
- Layer-second insulating layer -...-N-1th insulating layer-Nth ferroelectric functional layer-metal" structure.
- an asymmetric ferroelectric tunnel junction multi-value memory cell with a multi-layer structure is proposed, which inserts N parallel to the lateral plane direction between two metal electrodes.
- the ferroelectric functional layer, and the N ferroelectric functional layers have different coercive field performance parameters, thereby increasing the N-1 modulation variable.
- the coercive field is the critical field strength at which the polarization state of the ferroelectric material reverses under the action of an external electric field.
- the N ferroelectric functional layers will show different After removing the excitation, the N ferroelectric functional layers still maintain different degrees of residual polarization; when a certain logic external excitation is subsequently applied, due to the residual polarization direction of the N ferroelectric functional layers and Different intensities can make the entire asymmetric ferroelectric functional layer array 11 exhibit 2 N resistance states, and 2 N different storage states can be realized in one memory cell.
- the asymmetric ferroelectric functional layer array 11 has two ferroelectric functional layers.
- the multi-valued memory cell extends along the longitudinal direction. From bottom to top, it includes: a first electrode layer 1, a first ferroelectric functional layer 2, a first insulating layer 3, a second ferroelectric functional layer 4, and a second electrode layer 5.
- the first ferroelectric functional layer 2 and the second ferroelectric functional layer 3 have different coercive fields.
- the polarization size and direction of the two ferroelectric functional layers can be modulated, thereby changing the entire
- the tunneling barrier of the material makes the asymmetric ferroelectric functional layer array 11 present 4 different resistance states, and the corresponding 4 states can be used to represent the "00", "01", “10", and "in the binary digital system".
- the 11" state means that 4 different storage states are realized in one storage unit, which can greatly increase storage density and unit storage capacity.
- the main transport mechanism of the ferroelectric functional layer is the drift and diffusion of carriers. That is, under the action of external excitation, the charges/carriers in the ferroelectric material can move in the longitudinal direction over a certain barrier to generate currents of different values.
- the N ferroelectric functional layers have different coercive field performance parameters, so the N ferroelectric functional layers have different physical parameter differences: 1) different types of materials; 2) the same material, doped The method is different; 3) the same material, the annealing temperature is different for crystallization; 4) the same material, the thickness of the ferroelectric functional layer is different; at least one of the above conditions or a mixture of the above conditions are selected. More specifically, the greater the difference in the coercive fields of the N ferroelectric functional layers, the easier it is to modulate different resistance states, and the less likely the memory cell is to be misread.
- ferroelectric materials are used to prepare different ferroelectric functional layers.
- Materials with ferroelectric properties include: oxygen-containing octahedrons, fluorine-containing octahedrons, hydrogen-bonded ferroelectrics, ferroelectric polymers, ferroelectric liquid crystals, For hafnium-based ferroelectric materials, etc., ferroelectric materials with different coercive fields can be used.
- the preparation material of the ferroelectric functional layer is selected from doped or undoped HfO 2 , Hf x Zr 1-x O 2 , BiFeO 3 , BaTiO 3 , Pb(Zr 1-x Ti x )O 3 , Sr At least one of x Ba 1-x O 3 and polyvinylidene fluoride, but not limited thereto.
- a ferroelectric material based on doped HfO 2 can be selected, and the HfO 2 doping ratio, doping elements, etc. can be adjusted to have different coercivity. field.
- the degree of polarization is affected by the thickness, and the greater the difference in thickness, the greater the difference in coercive field performance.
- N is an integer greater than or equal to 2, more specifically 2 to 4, and most specifically 2. This is because the thickness of the asymmetric ferroelectric functional layer array 11 should not be too high, otherwise the current is too small and difficult to read.
- the thickness of each ferroelectric function layer in the asymmetric ferroelectric function layer array 11 is 2-20 nm, more specifically 10 nm. If the thickness of the ferroelectric functional layer is less than 2nm, the depolarization field strength is too large, and the polarization state is difficult to preserve. At the same time, the material lattice of the ferroelectric functional layer is easily damaged after multiple cycles of external excitation. The polarization intensity will also be significantly reduced; as the thickness of the ferroelectric functional layer increases, the amount of charge passing through the ferroelectric functional layer at the same voltage will decrease. If the thickness of the ferroelectric functional layer is greater than 20nm, the amount of charge passing through the ferroelectric functional layer Too little makes the current too small and it is difficult to accurately read the storage state.
- the insulating layer is a tunnelable insulating layer, which is used to isolate two ferroelectric functional layers with different coercive fields.
- the insulating layer has a compact structure, few defects, and a forbidden bandwidth.
- carriers/charges can only pass through by direct tunneling, and it is difficult to flow through other methods.
- the electron affinity of the insulating layer is smaller than that of all ferroelectric functional layers, so that the carriers/charges in the ferroelectric functional layer will not spontaneously migrate into the insulating layer.
- the first electrode layer 1 and the second electrode layer 5 are in Schottky contact with the first and second ferroelectric functional layers.
- the injected electrons can cross the Schottky barrier and enter the conduction band of the ferroelectric functional layer, and conduct electricity through drift diffusion; the electron affinity of the first insulating layer 3 is greater than that of the first ferroelectric functional layer 2 and the second ferroelectric functional layer 4 That is, the forbidden band width of the first insulating layer 3 is greater than the two ferroelectric functional layers, and electrons cannot enter the first or second ferroelectric functional layer through the first insulating layer 3 through drift diffusion.
- the energy band of the first insulating layer 3 is bent, and the first insulating layer 3 is sufficiently thin that electrons can pass through the first insulating layer by direct tunneling. 3 Enter the first or second ferroelectric functional layer, and then enter the first or second electrode layer through drift diffusion.
- the material of the insulating layer is selected from at least one insulating material such as Al, Si, Hf, Zr, Ta, and Ti oxide, but is not limited thereto.
- the thickness of the insulating layer is less than 5 nm; more specifically, the thickness of the insulating layer is 0.5 nm to 3 nm. If the thickness is greater than 3 nm, the tunnelable carriers/charges are too small, resulting in too small read current gap, which is easy Misreading occurs; if the thickness is less than 0.5nm, it does not play a role in isolation.
- the first electrode layer 1 and the second electrode layer 5 may be materials compatible with CMOS processes, including at least one of polysilicon, Al, TiN, TaN, W, Ni, and Ta, but not limited thereto; for example, TiN, At least one of TaN, etc. It may also be a conductive material suitable for the growth of ferroelectric materials, such as at least one of SrRuO 3 and Nd:SrTiO 3 suitable for the growth of perovskite structure ferroelectric materials.
- the thickness of the first electrode layer 1 and the second electrode layer 5 is 10 nm to 200 nm, more specifically, 100 nm.
- the multi-value storage of the asymmetric ferroelectric tunnel junction further includes a substrate, which in turn includes the substrate, the first electrode layer 1, the asymmetric ferroelectric functional layer array 11, and the second electrode along the longitudinal direction from bottom to top.
- Layer 5 the first electrode layer 1, the asymmetric ferroelectric functional layer array 11, and the second electrode along the longitudinal direction from bottom to top.
- applying external excitation is applying at least one of electric energy, thermal energy, light energy, electromagnetic energy, etc., specifically applying electric energy, more specifically applying an external voltage.
- the second aspect of the present invention provides an asymmetric ferroelectric tunnel junction multi-value memory and chip, which includes the above-mentioned asymmetric ferroelectric tunnel junction multi-value memory cell.
- the asymmetric ferroelectric functional layer unit when N is 2, the asymmetric ferroelectric functional layer unit includes 2 ferroelectric functional layers, so 4 different storage states can be implemented in a memory cell, and the memory cell can be used Prepared multi-value memory and chips with 4 storage states, greatly improving the storage density and unit storage capacity; at the same time, the multi-value memory/chip of the asymmetric ferroelectric tunnel junction can be used as a multi-value non-volatile memory. In the integrated chip such as in-storage computing.
- the third aspect of the present invention provides a method for preparing the above-mentioned asymmetric ferroelectric functional layer array 11, and the method includes the following steps:
- Step 1 Provide a first electrode layer 1, forming N ferroelectric functional layers parallel to the first plane direction on the upper surface of the first electrode layer 1, and an insulating layer is passed between two adjacent ferroelectric functional layers isolate;
- Step 2 Crystallize the ferroelectric functional layer so that the N ferroelectric functional layer materials exhibit ferroelectric properties
- N is an integer greater than or equal to 2, that is, there are at least two ferroelectric functional layers, and there is an insulating layer between two adjacent ferroelectric functional layers, that is, there are N ferroelectric functional layers.
- Layers and N-1 insulating layers are alternately stacked to form an asymmetric ferroelectric functional layer array 11.
- the growth method of the ferroelectric functional layer and the insulating layer includes at least one of atomic layer deposition (ALD), physical vapor deposition (PVD) or spin coating, but is not limited to this .
- ALD atomic layer deposition
- PVD physical vapor deposition
- spin coating but is not limited to this .
- atomic layer deposition (ALD) is used.
- the method for preparing the multi-value memory cell of the asymmetric ferroelectric tunnel junction includes the following steps:
- Step 1-1 Provide a first electrode layer 1, and grow the first ferroelectric functional layer 2 on the upper surface of the first electrode layer 1 by ALD, PVD or spin coating;
- Step 1-2 Growing the first insulating layer 3 on the upper surface of the first ferroelectric functional layer 2 by means of ALD or PVD;
- Step 1-3 Growing a second ferroelectric functional layer on the upper surface of the first insulating layer 3 by ALD, PVD or spin coating;
- Step 2 Crystallize the ferroelectric functional layer, so that the N ferroelectric functional layer materials exhibit ferroelectric properties
- the physical parameters of the i-th ferroelectric functional layer are different from the physical parameters of the (i+1)th ferroelectric functional layer, so that the N number of ferroelectric functional layers
- the ferroelectric functional layers exhibit performance differences in coercive fields.
- the physical parameters include at least one of the following: the type of the ferroelectric functional layer material, the doping mode of the ferroelectric functional layer material, the crystallization condition of the ferroelectric functional layer, and the thickness of the ferroelectric functional layer material.
- ferroelectric functional layer materials can be directly selected.
- At least one of atomic layer deposition (ALD), physical vapor deposition (PVD) or spin coating is used in the first electrode.
- ALD atomic layer deposition
- PVD physical vapor deposition
- spin coating is used in the first electrode.
- the coercive field value of different ferroelectric functional layers can be adjusted by using the ratio and process of doping of the ferroelectric functional layer material.
- the Si:HfO 2 ferroelectric functional layer and the Al:HfO 2 ferroelectric functional layer are prepared using atomic layer deposition technology, and the Si and Al atomic layers are respectively deposited during the HfO 2 deposition process, and the correction is controlled by controlling the deposition of different atomic layers. Stubborn field value.
- the thickness of the ferroelectric functional layer material can also be used to control the coercive field values of different ferroelectric functional layers.
- an HZO ferroelectric functional layer with a Hf/Zr ratio of 1:1 is prepared using atomic layer deposition technology, HfO 2 and ZrO 2 monoatomic layer films are alternately deposited, and the coercive field value is controlled by controlling the alternate deposition thickness.
- the crystallization conditions of the ferroelectric functional layer can also be used to control the coercive field values of different ferroelectric functional layers.
- the coercive field value can be controlled by controlling the maximum temperature of annealing or the time of annealing.
- the atomic layer deposition method is a method in which the material materials of the ferroelectric functional layer and the insulating layer are plated layer by layer on the surface of the underlying material in the form of a monoatomic film, and at the same time, the thickness of the different layers is controlled by the number of monoatomic coatings.
- the temperature of the atomic deposition reaction chamber is 200-400°C.
- the physical vapor deposition method is a magnetron sputtering method, and the thickness of different layers is controlled by controlling the sputtering time.
- the sputtering power is 100-200W
- the sputtering time is 1000-1500s
- the inert gas is Ar gas
- the pressure is 0.2-0.8Pa; more specifically, the sputtering power is 150W
- the sputtering time is 1200s.
- the inert gas is Ar gas
- the pressure is 0.5Pa.
- the physical parameters include at least one of the following: doping mode of the ferroelectric functional layer material, the type of the ferroelectric functional layer material, the crystallization condition of the ferroelectric functional layer, and the thickness of the ferroelectric functional layer material.
- the spin coating method rotates the axis perpendicular to the surface of the lower layer, and at the same time coats the liquid coating material on the surface of the lower layer, and controls the thickness of different layers by controlling the time of the spin coating.
- the present invention provides a method for preparing the above-mentioned asymmetric ferroelectric tunnel junction multi-value memory cell, the multi-value memory cell includes the above
- the method includes the following steps:
- Step 1 Provide a substrate, and form a first electrode layer 1 on the upper surface of the substrate;
- Step 2 Form an asymmetric ferroelectric functional layer array 11 on the upper surface of the first electrode layer 1, which includes: N ferroelectric functional layers parallel to the first plane direction, two adjacent ferroelectric functional layers Are separated by an insulating layer;
- Step 3 Form a second electrode layer 5 on the upper surface of the Nth ferroelectric functional layer
- Step 4 Crystallize the ferroelectric functional layer so that the ferroelectric functional layer material exhibits ferroelectric properties
- N is an integer greater than or equal to 2, that is, there are at least two ferroelectric functional layers, and there is an insulating layer between two adjacent ferroelectric functional layers, that is, there are N ferroelectric functional layers. Layers and N-1 insulating layers are alternately stacked to form an asymmetric ferroelectric functional layer array 11.
- Step 2-1 forming an i-th ferroelectric functional layer on the upper surface of the first electrode
- Step 2-2 forming a j-th insulating layer on the upper surface of the i-th ferroelectric functional layer;
- Step 2-3 forming an (i+1)th ferroelectric functional layer on the upper surface of the jth insulating layer;
- the first electrode layer 1 is deposited on the upper surface of the substrate by means of physical vapor deposition (PVD).
- the substrate is a single crystal silicon with SiO2 grown on one side by polishing, and the physical vapor deposition (PVD) method is a magnetron sputtering method.
- the substrate is first cleaned with acetone in an ultrasonic environment for 5-20 minutes, and then washed with alcohol for 5-20 minutes in an ultrasonic environment, rinsed with deionized water, and finally dried with a nitrogen gun; using a magnetron sputtering
- the sputtering power is 150W
- the sputtering time is 1200s
- the inert gas is Ar gas
- the pressure is 0.5Pa.
- the asymmetric ferroelectric functional layer array 11 is deposited and prepared by means of atomic layer deposition (ALD), physical vapor deposition (PVD) or spin coating.
- ALD atomic layer deposition
- PVD physical vapor deposition
- spin coating a coating of atomic layer deposition
- the use of atomic layer deposition (ALD) in the form of a monoatomic film layer by layer on the first electrode material or the corresponding ferroelectric functional layer, the upper surface of the insulating layer, and the number of monoatomic coating is controlled at the same time
- the temperature of the atomic deposition reaction chamber is 200-400°C.
- the second electrode layer 5 may be deposited and prepared by means of physical vapor deposition (PVD).
- PVD physical vapor deposition
- the magnetron sputtering method is used; more specifically, first, photolithography is used to define the pattern of the second electrode layer 5 on the photoresist on the Nth layer of ferroelectric function layer, the material of the second electrode layer 5 is deposited, and the material is peeled off. A pattern of the second electrode layer 5 is formed, and then the photoresist is removed.
- the second electrode layer 5 pattern is defined on the photoresist by photolithography on the upper surface of the Nth layer of ferroelectric function layer, the material of the second electrode layer 5 is deposited, and the material is peeled off. A pattern of the second electrode layer 5 is formed.
- step 4 annealing is used to crystallize the deposited ferroelectric functional layer to form a ferroelectric phase, which exhibits ferroelectricity. Specifically, a rapid annealing method is adopted in a nitrogen atmosphere.
- the method for preparing the multi-value memory cell of the asymmetric ferroelectric tunnel junction includes the following steps:
- Step 1 Provide a substrate, and deposit a first electrode on the substrate by means of PVD on the upper surface of the substrate;
- Step 2-1 Growing the first ferroelectric functional layer 2 on the surface of the first electrode by ALD, PVD or spin coating;
- Step 2-2 Growing an insulating layer on the surface of the first ferroelectric functional layer 2 by means of ALD or PVD;
- Step 2-3 Growing a second ferroelectric functional layer on the surface of the insulating layer by means of PVD;
- Step 3 Use photolithography to define the pattern of the second electrode layer 5 on the photoresist on the surface of the second ferroelectric functional layer, deposit the material of the second electrode layer 5, and peel off to form the pattern of the second electrode layer 5.
- Step 4 Annealing is used to crystallize the deposited first and second ferroelectric functional layer materials to generate a ferroelectric phase, which exhibits ferroelectricity.
- the fourth aspect of the present invention provides a modulation method of the multi-value memory cell of the asymmetric ferroelectric tunnel junction.
- the multi-value memory cell of the asymmetric ferroelectric tunnel junction inserts N ferroelectric functional layers parallel to the lateral plane direction between two metal electrodes, and the N ferroelectric functional layers have different corrections.
- the coercive field performance parameter increases the N-1 modulation variable compared to the single-layer ferroelectric memory cell.
- the coercive field is a measure of the degree of polarization of different ferroelectric materials under the same external excitation conditions. Therefore, the asymmetric ferroelectric functional layer array 11 will exhibit different polarizations under the conditions of external excitation.
- the inventor gave a specific implementation, that is, when N is 2, and it is assumed that the coercive field of the second ferroelectric functional layer is greater than that of the first ferroelectric functional layer 2, and the first and second ferroelectric functional layers When the polarization direction is the top electrode to the bottom electrode, it is positive polarity, and vice versa, it is negative polarity. This assumption is only convenient for presentation.
- the present invention covers the opposite situation and claims its corresponding rights. details as follows:
- the first ferroelectric functional layer is polarized negatively, and the second ferroelectric functional layer is polarized positively. Therefore, the two ferroelectric functional layers have positive charges near the insulating layer. Accumulation reduces the potential energy of electrons, and theoretically forms a similar barrier layer of the first ferroelectric functional layer and a similar anti-barrier layer of the second ferroelectric functional layer. The state is recorded as "01" by the direction of polarization.
- the two ferroelectric functional layers are near the insulating layer.
- the accumulation of negative charges increases the potential of electrons.
- the anti-blocking layer of the first ferroelectric functional layer and the similar blocking layer of the second ferroelectric functional layer are formed. The state is recorded as "10" by the direction of polarization.
- a read operation that is, when a certain conditional external excitation is applied, the entire asymmetric ferroelectric functional layer array 11 can present 4 resistance states, and 4 different storage states can be realized in one memory cell.
- Read operation keep the first electrode layer 1 grounded, and add a suitable positive small voltage V5 to the second electrode layer 5.
- the selection rule of the small positive voltage should ensure that the first iron with a small coercive field is not enough
- the polarization direction of the electrical function layer 2 changes, and then the current level of the top electrode is read, and the stored information can be read.
- This embodiment provides a multi-valued memory cell based on an asymmetric ferroelectric tunnel junction of Hf 0.5 Zr 0.5 O 2 (hereinafter abbreviated as HZO) ferroelectric thin film and Al 2 O 3 insulating layer.
- HZO Hf 0.5 Zr 0.5 O 2
- Al 2 O 3 insulating layer Al 2 O 3 insulating layer.
- the schematic diagram of the structure is shown in FIG. 1 As shown, from bottom to top, it mainly includes a first electrode layer 1, a first ferroelectric functional layer 2, an insulating layer 3, a second ferroelectric functional layer 4, and a second electrode layer 5. Specific steps are as follows:
- Step 1 Preparation of the first electrode layer 1:
- TiN is used as the bottom electrode 1
- a layer of bottom electrode 1 is grown on a single-sided polished and grown SiO 2 single crystal silicon substrate by magnetron sputtering.
- Step 1-1 Substrate cleaning: first clean with acetone in an ultrasonic environment for 10 minutes, then use alcohol for 10 minutes in an ultrasonic environment, rinse with deionized water, and finally blow dry with a nitrogen gun;
- Step 1-2 Magnetron Sputtering Bottom Electrode 1: Using a TiN target, under 150W DC sputtering power, 0.5Pa Ar gas is divided into medium sputtering for 1200s to grow a 100nm TiN bottom electrode.
- Step 2 Preparation of the first ferroelectric functional layer 2
- a 10nm HZO ferroelectric thin film is selected, and an HZO ferroelectric thin film with a Hf/Zr ratio of 1:1 is obtained by an atomic layer deposition technique.
- the temperature of the ALD reaction chamber is 300°C
- the temperature of the TEMA-Hf source is 80°C
- the temperature of the TEMA-Zr source is 90°C.
- HfO 2 and ZrO 2 monoatomic layers are deposited alternately, and deposited alternately 50 times.
- Step 3 Preparation of insulating layer 3
- Example chosen 2nmAl 2 O 3 film, resulting 2nm dense Al 2 O 3 film by atomic layer deposition techniques.
- the temperature of the ALD reaction chamber is 300°C.
- a TMA source is used to react with H 2 O to generate Al 2 O 3 , and a 20-cycle Al 2 O 3 layer is grown.
- Step 4 Preparation of the second ferroelectric functional layer 4
- a 5nm HZO ferroelectric thin film is selected, and an HZO ferroelectric thin film with a Hf/Zr ratio of 1:1 is obtained by an atomic layer deposition technique.
- the temperature of the ALD reaction chamber is 300°C
- the temperature of the TEMA-Hf source is 80°C
- the temperature of the TEMA-Zr source is 90°C.
- HfO 2 and ZrO 2 monoatomic layers are deposited alternately, 25 times.
- Step 5 Preparation of the second electrode layer 5:
- TiN is used as the upper electrode 5
- the upper electrode 5 pattern is prepared on the second ferroelectric functional layer 4 through a photolithography process
- the TiN upper electrode is grown by a magnetron sputtering method.
- Step 5-1 Photolithography: Prepare the upper electrode 5 pattern on the second ferroelectric functional layer 4 by a photolithography process, where the photolithography steps include homogenization, pre-baking, pre-exposure, post-baking, post-exposure, and development;
- Step 5-2 Sputtering: The experiment uses a TiN target, sputtering for 1200s to grow a 100nm upper electrode in an Ar atmosphere of 0.5 Pa at a sputtering power of 150W;
- Step 5-3 Peeling: Soak the film sample prepared in Step 5-2 with acetone, during which it is assisted by ultrasonic cleaning, and then washed with absolute ethanol and deionized water in turn, and finally dried with a nitrogen gun.
- Step 6 Annealing to crystallize the ferroelectric material
- rapid annealing in a nitrogen atmosphere is used to crystallize the first ferroelectric functional layer 2 and the second ferroelectric functional layer 4 to exhibit ferroelectricity.
- the specific setting of rapid annealing is that nitrogen is introduced into the annealing furnace, the annealing temperature is set to room temperature for 2 minutes, 1 minute from room temperature to 500°C, 500°C for 30 seconds, and 2 minutes from 500°C to room temperature.
- This embodiment provides a multi-valued memory cell based on the asymmetric ferroelectric tunnel junction of Si:HfO 2 and Al:HfO 2 ferroelectric thin film and Al 2 O 3 insulating layer.
- the schematic diagram of the structure is shown in FIG. 1. From bottom to top, it mainly includes a bottom electrode 1, a first ferroelectric functional layer 2, an insulating layer 3, a second ferroelectric functional layer 4, and an upper electrode 5. Specific steps are as follows:
- Step 1 Preparation of the first electrode layer 1:
- TiN is used as the bottom electrode 1
- a layer of bottom electrode 1 is grown on a single-sided polished and grown SiO 2 single crystal silicon substrate by magnetron sputtering.
- Step 1-1 Substrate cleaning: first clean with acetone in an ultrasonic environment for 10 minutes, then use alcohol for 10 minutes in an ultrasonic environment, rinse with deionized water, and finally blow dry with a nitrogen gun;
- Step 1-2 Magnetron Sputtering Bottom Electrode 1: Using a TiN target, under 150W DC sputtering power, 0.5Pa Ar gas is divided into medium sputtering for 1200s to grow a 100nm TiN bottom electrode.
- Step 2 Preparation of the first ferroelectric functional layer 2
- the temperature of the ALD reaction chamber is 300°C, using TEMA-Hf as the Hf source, 4DMAS as the Si source, and H 2 O as the O source. Under these conditions, first grow 19 cycle HfO 2 layers, and then grow 1 cycle SiO 2 layer , The growth is repeated 5 times to obtain a Si-doped HfO 2 thin film with a thickness of 10 nm.
- Step 3 Preparation of the first insulating layer 3
- Example chosen 2nmAl 2 O 3 film, resulting 2nm dense Al 2 O 3 film by atomic layer deposition techniques.
- the temperature of the ALD reaction chamber is 300°C.
- a TMA source is used to react with H 2 O to generate Al 2 O 3 , and a 20-cycle Al 2 O 3 layer is grown.
- Step 4 Preparation of the second ferroelectric functional layer 4
- the temperature of the ALD reaction chamber is 300°C, using TEMA-Hf as the Hf source, TMA as the Al source, and H 2 O as the O source. Under these conditions, first grow 15 cycle HfO 2 layers, and then grow 1 cycle Al 2 O With 3 layers, the growth is repeated 7 times to obtain an Al-doped HfO 2 thin film with a thickness of 10 nm.
- Step 5 Preparation of the second electrode layer 5:
- TiN is used as the upper electrode 5
- the upper electrode 5 pattern is prepared on the second ferroelectric functional layer 4 through a photolithography process
- the TiN upper electrode is grown by a magnetron sputtering method.
- Step 5-1 photolithography: preparing the pattern of the upper electrode 5 on the second ferroelectric functional layer 4 through a photolithography process, where the photolithography steps include homogenization, pre-baking, pre-exposure, post-baking, post-exposure, and development;
- Step 5-2 Sputtering: The experiment uses a TiN target, sputtering for 1200s to grow a 100nm upper electrode in an Ar atmosphere of 0.5 Pa at a sputtering power of 150W;
- Step 5-3 Peeling: Soak the film sample prepared in Step 5-2 with acetone, during which it is assisted by ultrasonic cleaning, and then washed with absolute ethanol and deionized water in turn, and finally dried with a nitrogen gun.
- Step 6 Annealing to crystallize the ferroelectric material
- rapid annealing in a nitrogen atmosphere is used to crystallize the first ferroelectric functional layer 2 and the second ferroelectric functional layer 4 to exhibit ferroelectricity.
- the specific setting of rapid annealing is that nitrogen is introduced into the annealing furnace, the annealing temperature is set to room temperature for 2 minutes, 1 minute from room temperature to 800°C, 800°C for 20 seconds, and 2 minutes from 800°C to room temperature.
- This embodiment provides a multi-valued memory cell based on an asymmetric ferroelectric tunnel junction of Hf 0.5 Zr 0.5 O 2 (hereinafter abbreviated as HZO) and BiFeO 3 (hereinafter referred to as BFO) ferroelectric thin film and Al 2 O 3 insulating layer
- HZO Hf 0.5 Zr 0.5 O 2
- BFO BiFeO 3
- FIG. 1 The schematic diagram of the structure is shown in FIG. 1, which mainly includes a first electrode layer 1, a first ferroelectric functional layer 2, an insulating layer 3, a second ferroelectric functional layer 4, and a second electrode layer 5 from bottom to top. Specific steps are as follows:
- Step 1 Preparation of the first electrode layer 1:
- SrRuO 3 is used as the lower electrode 1, and a layer of lower electrode 1 is grown on the single crystal SrTiO 3 substrate by the method of magnetron sputtering.
- Step 1-1 Substrate cleaning: first clean with acetone in an ultrasonic environment for 10 minutes, then use alcohol for 10 minutes in an ultrasonic environment, rinse with deionized water, and finally blow dry with a nitrogen gun;
- Step 1-2 Magnetron sputtering lower electrode 1: Use SrRuO 3 target, deposition temperature of 600°C, use Ar/O 2 mixture with Ar/O 2 ratio of 1:4, working pressure of 3Pa, sputtering power For 80W, 50nm SrRuO 3 bottom electrode was deposited.
- Step 2 Preparation of the first ferroelectric functional layer 2
- a 20nm BFO ferroelectric thin film is selected and deposited by means of laser pulse deposition (PLD).
- PLD laser pulse deposition
- the PLD deposition temperature is 700°C
- the target base distance is 78mm
- the O 2 partial pressure is 30mTorr
- the laser power is 50mJ
- the frequency is 10Hz
- 5000 pulses are deposited to obtain a 20nm BFO ferroelectric film.
- Step 3 Preparation of the first insulating layer 3
- Example chosen 2nmAl 2 O 3 film, resulting 2nm dense Al 2 O 3 film by atomic layer deposition techniques.
- the temperature of the ALD reaction chamber is 300°C.
- a TMA source is used to react with H 2 O to generate Al 2 O 3 , and a 20-cycle Al 2 O 3 layer is grown.
- Step 4 Preparation of the second ferroelectric functional layer 4
- a 5nm HZO ferroelectric thin film is selected, and an HZO ferroelectric thin film with a Hf/Zr ratio of 1:1 is obtained by an atomic layer deposition technique.
- the temperature of the ALD reaction chamber is 300°C
- the temperature of the TEMA-Hf source is 80°C
- the temperature of the TEMA-Zr source is 90°C.
- HfO 2 and ZrO 2 monoatomic layers are deposited alternately, 25 times.
- Step 5 Preparation of the second electrode layer 5:
- TiN is used as the upper electrode 5
- the upper electrode 5 pattern is prepared on the second ferroelectric functional layer 4 through a photolithography process
- the TiN upper electrode is grown by a magnetron sputtering method.
- Step 5-1 Photolithography: Prepare the upper electrode 5 pattern on the second ferroelectric functional layer 4 by a photolithography process, where the photolithography steps include homogenization, pre-baking, pre-exposure, post-baking, post-exposure, and development;
- Step 5-2 Sputtering: The experiment uses a TiN target, sputtering for 1200s to grow a 100nm upper electrode in an Ar atmosphere of 0.5 Pa at a sputtering power of 150W;
- Step 5-3 Peeling: Soak the film sample prepared in Step 5-2 with acetone, during which it is assisted by ultrasonic cleaning, and then washed with absolute ethanol and deionized water in turn, and finally dried with a nitrogen gun.
- Step 6 Annealing to crystallize the ferroelectric material
- rapid annealing in a nitrogen atmosphere is used to crystallize the first ferroelectric functional layer 2 and the second ferroelectric functional layer 4 to exhibit ferroelectricity.
- the specific setting of rapid annealing is that nitrogen is introduced into the annealing furnace, the annealing temperature is set to room temperature for 2 minutes, 1 minute from room temperature to 500°C, 500°C for 30 seconds, and 2 minutes from 500°C to room temperature.
- This embodiment provides a multi-value memory cell based on an asymmetric ferroelectric tunnel junction of Hf 0.5 Zr 0.5 O 2 (hereinafter abbreviated as HZO) ferroelectric thin film and Al 2 O 3 insulating layer at different annealing temperatures, and its structure is schematic diagram As shown in FIG. 1, it mainly includes a first electrode layer 1, a first ferroelectric functional layer 2, an insulating layer 3, a second ferroelectric functional layer 4, and a second electrode layer 5 from bottom to top. Specific steps are as follows:
- Step 1 Preparation of the first electrode layer 1:
- TiN is used as the bottom electrode 1
- a layer of bottom electrode 1 is grown on a single-sided polished SiO2 monocrystalline silicon substrate by magnetron sputtering.
- Step 1-1 Substrate cleaning: first clean with acetone in an ultrasonic environment for 10 minutes, then use alcohol for 10 minutes in an ultrasonic environment, rinse with deionized water, and finally blow dry with a nitrogen gun;
- Step 1-2 Magnetron Sputtering Bottom Electrode 1: Using a TiN target, under 150W DC sputtering power, 0.5Pa Ar gas is divided into medium sputtering for 1200s to grow a 100nm TiN bottom electrode.
- Step 2 Preparation of the first ferroelectric functional layer 2
- a 10nm HZO ferroelectric thin film is selected, and an HZO ferroelectric thin film with a Hf/Zr ratio of 1:1 is obtained by an atomic layer deposition technique.
- the temperature of the ALD reaction chamber is 300°C
- the temperature of the TEMA-Hf source is 80°C
- the temperature of the TEMA-Zr source is 90°C.
- HfO 2 and ZrO 2 monoatomic layers are deposited alternately, and deposited alternately 50 times.
- Step 3 Annealing to crystallize the material of the first ferroelectric functional layer 2
- rapid annealing in a nitrogen atmosphere is used to crystallize the first ferroelectric functional layer 2 to exhibit ferroelectricity.
- the specific setting of rapid annealing is that nitrogen is introduced into the annealing furnace, the annealing temperature is set to room temperature for 2 minutes, 1 minute from room temperature to 500°C, 500°C for 30 seconds, and 2 minutes from 500°C to room temperature.
- Step 3 Preparation of the first insulating layer 3
- Example chosen 2nmAl 2 O 3 film, resulting 2nm dense Al 2 O 3 film by atomic layer deposition techniques.
- the temperature of the ALD reaction chamber is 300°C.
- a TMA source is used to react with H 2 O to generate Al 2 O 3 , and a 20-cycle Al 2 O 3 layer is grown.
- Step 4 Preparation of the second ferroelectric functional layer 4
- a 5nm HZO ferroelectric thin film is selected, and an HZO ferroelectric thin film with a Hf/Zr ratio of 1:1 is obtained by an atomic layer deposition technique.
- the temperature of the ALD reaction chamber is 300°C
- the temperature of the TEMA-Hf source is 80°C
- the temperature of the TEMA-Zr source is 90°C.
- HfO 2 and ZrO 2 monoatomic layers are deposited alternately, 25 times.
- Step 5 Preparation of the second electrode layer 5:
- TiN is used as the upper electrode 5
- the upper electrode 5 pattern is prepared on the second ferroelectric functional layer 4 through a photolithography process
- the TiN upper electrode is grown by a magnetron sputtering method.
- Step 5-1 Photolithography: Prepare the upper electrode 5 pattern on the second ferroelectric functional layer 4 by a photolithography process, where the photolithography steps include homogenization, pre-baking, pre-exposure, post-baking, post-exposure, and development;
- Step 5-2 Sputtering: The experiment uses a TiN target, sputtering for 1200s to grow a 100nm upper electrode in an Ar atmosphere of 0.5 Pa at a sputtering power of 150W;
- Step 5-3 Peeling: Soak the film sample prepared in Step 5-2 with acetone, during which it is assisted by ultrasonic cleaning, and then washed with absolute ethanol and deionized water in turn, and finally dried with a nitrogen gun.
- Step 6 Annealing to crystallize the material of the second ferroelectric functional layer 4
- rapid annealing in a nitrogen atmosphere is used to crystallize the second ferroelectric functional layer 4, which exhibits ferroelectricity.
- the specific setting of rapid annealing is that nitrogen is introduced into the annealing furnace, the annealing temperature is set to room temperature for 2 minutes, 1 minute from room temperature to 400°C, 400°C for 30 seconds, and 2 minutes from 400°C to room temperature.
- Example 1 a modulation method of a multi-value memory cell based on an asymmetric ferroelectric tunnel junction of HZO ferroelectric film and Al2O3 insulating layer, because the thickness of the first ferroelectric function layer 2 is smaller than that of the second ferroelectric function Layer 4, so the coercive field of the second ferroelectric functional layer 4 is greater than the coercive field of the first ferroelectric functional layer 2, the modulation method includes the following two steps: "write” and "read”:
- the upper end 22 of the first ferroelectric functional layer 2 and the lower end 41 of the second ferroelectric functional layer 4 have positive charge accumulation
- the electron potential is reduced to form a similar barrier layer of the first ferroelectric functional layer 2 and a similar anti-blocking layer of the second ferroelectric functional layer 4.
- the state is marked as "01" by the direction of polarization, which is the state in Figure 3 2.
- the polarization of the first ferroelectric functional layer 2 is positive, and the polarization of the second ferroelectric functional layer 4 is negative, so the upper end 22 of the first ferroelectric functional layer 2 and the second ferroelectric functional layer 4
- the lower end 41 has a negative charge accumulation to increase the electron potential, forming a similar anti-blocking layer of the first ferroelectric functional layer 2 and a similar blocking layer of the second ferroelectric functional layer 4.
- the state is recorded as " 10", as shown in state 4 in Figure 3.
- FIG. 3 is a simulation diagram of the remanent polarization of the ferroelectric layer in different states of the multi-value memory cell of the asymmetric ferroelectric tunnel junction implemented according to the present invention.
- the restriction of the first ferroelectric functional layer 2 plays a dominant role in the current passing through the second electrode layer 5, as shown in state 1 and state 2 in Fig. 3 Since the tunneling barrier of the first ferroelectric functional layer 2 in state 1 is wider than that in state 2, state 1 is a high-impedance state, denoted as the Z1 state, and the resistance of state 2 is slightly lower than that of state 1. Recorded as Z2 state.
- state 3 is a high-resistance state, which is recorded as the Z3 state, while the resistance of state 4 is slightly lower than that of state 3, which is recorded as Z4 state.
- a suitable small positive voltage V5 is added between the second electrode layer 5 and the first electrode layer 1.
- the selection rule of the small positive voltage should ensure that the first ferroelectric functional layer with a small coercive field is not enough to make the coercive field smaller.
- the polarization direction of 2 changes, and then read the current of the top electrode, you can read the stored information.
- the specific resistance sizes corresponding to the four states are shown in Table 1. Wherein, the polarization direction described in Table 1 means downward from the second electrode layer 5 to the first electrode layer 1, and upward means from the first electrode layer 1 to the second electrode layer 5.
- Example 1 HZO films of different thicknesses were prepared to realize the adjustment of the coercive field of the first and second ferroelectric functional layers; in Example 2, HfO 2 films doped with different elements were used to realize the control of the first and second ferroelectric functional layers.
- the embodiment provides process feasibility. Test cases prove that when there are two ferroelectric functional layers, the multi-value memory cell of the asymmetric ferroelectric tunnel junction can modulate 4 logic storage states. Based on the description of Examples 1 to 4, when the ferroelectric functional layer is multilayered, the material preparation process can be adjusted to realize the adjustment of the coercive field size of different ferroelectric functional layers, thereby preparing memory cells with multiple tunneling resistance states. Those skilled in the art can prepare asymmetric ferroelectric tunnel junction multi-value memory cells and multi-value memories with multilayer ferroelectric functional layers based on the preparation methods and modulation methods implemented in 1 to 4.
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Abstract
本发明提供了非对称铁电功能层阵列、非对称铁电隧道结多值存储单元的制备方法,非对称铁电功能层阵列由N个铁电功能层和N-1个绝缘层交替堆叠形成,制备方法包括:提供电极层,在该电极层上表面生长N个平行于第一平面方向的铁电功能层,且相邻的铁电功能层之间通过绝缘层隔离,将该铁电功能层晶化,以使N个铁电功能层材料呈现铁电性能;N个铁电功能层的形成工艺期间的物理参数不同,以使N个铁电功能层呈现不同的矫顽场值。物理参数包括铁电功能层材料类型、铁电功能层材料掺杂方式、铁电功能层晶化条件以及铁电功能层材料的厚度。由此制备的存储单元可以实现多种不同的存储状态,从而大幅度提高存储密度以及单位存储容量。
Description
本发明属于微电子器件领域,特别是涉及一种非对称铁电功能层阵列、非对称铁电隧道结多值存储单元、存储器及其制备方法。
大数据时代的到来,对信息处理能力以及信息存储容量的需求不断提高,传统的冯·诺依曼计算机架构和存储器越来越难以满足需求。铁电材料因其擦写速度快、超低功耗、循环次数多、极化状态非易失等固有优势而被应用于存储领域,基于铁电材料的FRAM、FeFET以及FTJ等新型非易失性存储器受到了广泛的关注。其中,FTJ存储器通过铁电极化方向调制绝缘层界面势垒高度进而实现方向可切换的整流功能从而实现高低阻态的切换。FTJ存储器不仅具备铁电存储器擦写速度快、超低功耗、循环次数多、非易失性的固有优势,相较于FRAM和FeFET还具有尺寸更小,结构简单,非破坏性读出等优势。
经研究发现,不同于常规介质材料内部极化随外加电场线性变化,铁电材料内部极化与外加电场成非线性关系,并且由于取向极化的缘故,其存在两个稳定的极化状态,这为其作为存储器奠定了很好的基础。铪基材料具有十分优良的铁电性,以及与CMOS工艺兼容的优点也让基于铪基材料的铁电器件具有很好的发展前景。基于MFIM结构(即金属-铁电功能层-绝缘层-金属)的FTJ存储器,相较于MFM结构(即金属-铁电功能层-金属)FTJ器件,在铁电功能层与金属电极之间插入了一层绝缘隧穿层,很好地解决了金属电极所带来的介电屏蔽效应以及退极化问题。MFIM结构利用绝缘层作为隧穿层而非将铁电功能层作为隧穿层,降低了对于铁电功能层厚度的要求,使用较厚的铁电功能层也可以实现隧穿效应,从而很大程度上降低了制备FTJ存储器的工艺难度以及制备成本。
基于MFIM的存储器多被应用于二值存储器,其原理在于,通过外加电场使铁电功能层表现出稳定的相同方向的极化。在去掉外加电场之后,由于剩余极化强度不为0,会造成由极化电荷所产生的极化电场,该极化电场会抬升铁电功能层的能带能量或者降低铁电功能层的能带能量。当铁电功能层近绝缘层界面的能带能量较高时,电子从绝缘层一侧的金属隧穿则面临较高的FN隧穿势垒,读出 电流较小,器件处于高阻态;而当铁电功能层近绝缘层界面的能带能量较低时,电子则面临较低的FN隧穿势垒,读出电流较大,器件处于低阻态;从而实现“0”和“1”的逻辑存储。因此,基于MFIM的存储器只能被应用于二值存储器,难以很好的满足未来社会对对信息处理能力和信息存储容量的更高要求。
【发明内容】
针对现有技术的以上缺陷或改进需求,本发明提供了一种用于,可以具有多项高。
为实现上述目的,本发明一方面提供一种非对称铁电功能层阵列的制备方法,所述非对称铁电功能层阵列由N个铁电功能层和N-1个绝缘层交替堆叠形成,所述方法包括以下步骤:
提供电极层,在所述电极层上表面生长N个平行于第一平面方向的铁电功能层,且相邻的所述铁电功能层之间通过绝缘层隔离,包括:在所述电极层上表面形成第i铁电功能层;在所述第i铁电功能层上表面形成第j绝缘层;在所述第j绝缘层上表面形成第(i+1)铁电功能层;
将所述铁电功能层晶化,以使N个所述铁电功能层材料呈现铁电性能;
其中,N个所述铁电功能层的形成工艺期间的物理参数不同,以使N个所述铁电功能层呈现不同的矫顽场值;
其中,N为大于等于2的整数,i为所述铁电功能层沿垂直第一平面方向由下至上的序号,i=1,2,……N,j为所述绝缘层沿垂直第一平面方向由下至上的序号,j=1,2,……N-1。
进一步地,所述物理参数包括以下至少一项:铁电功能层材料类型、铁电功能层材料掺杂方式、铁电功能层晶化条件以及铁电功能层材料的厚度。
本发明第二方面提供一种非对称铁电隧道结的多值存储单元的制备方法,所述方法包括:
提供衬底,在所述衬底上表面形成第一电极层;
在所述第一电极层上表面形成非对称铁电功能层阵列,其包括:N个平行于第一平面方向的铁电功能层,且相邻的所述铁电功能层之间通过绝缘层隔离;
在所述非对称铁电功能层阵列上表面形成第二电极层;
其中,所述非对称铁电功能层阵列形成方法包括:
提供第一电极层,在所述第一电极层上表面生长N个平行于第一平面方向的铁电功能层,且相邻的所述铁电功能层之间通过绝缘层隔离,包括:在所述电极层上表面形成第i铁电功能层;在所述第i铁电功能层上表面形成第j绝缘层;在所述第j绝缘层上表面形成第(i+1)铁电功能层;
将所述铁电功能层晶化,以使N个所述铁电功能层材料呈现铁电性能;
其中,N个所述铁电功能层的形成工艺期间的物理参数不同,以使N个所述铁电功能层呈现不同的矫顽场值;
其中,N为大于等于2的整数,i为所述铁电功能层沿垂直第一平面方向由下至上的序号,i=1,2,……N,j为所述绝缘层沿垂直第一平面方向由下至上的序号,j=1,2,……N-1。
进一步地,所述物理参数包括以下至少一项:铁电功能层材料类型、铁电功能层材料掺杂方式、铁电功能层晶化条件以及铁电功能层材料的厚度。
进一步地,所述方法包括:
采用原子层沉积、物理气相沉积或者旋转涂抹的方法在所述第一电极层上表面交替生长N个的铁电功能层以及N-1个绝缘层。
采用物理气相沉积的方法在所述衬底上表面生长第一电极层;
采用物理气相沉积的方法在所述非对称铁电功能层阵列上表面形生长第二电极层。
进一步地,所述N个铁电功能层的制备材料选自掺杂或者未掺杂的HfO
2、Hf
xZr
1-xO
2、BiFeO
3、BaTiO
3、Pb(Zr
1-xTi
x)O
3、Sr
xBa
1-xO
3、聚偏氟乙烯中至少一种,且其厚度为2~20nm。
进一步地,所述N-1个绝缘层的制备材料选自Al、Si、Hf、Zr、Ta、Ti的氧化物中至少一种,且其厚度为0.5~3nm。
进一步地,所述第一、第二电极层的制备材料选自多晶硅、Al、TiN、TaN、W、Ni、Ta、SrRuO3、Nd:SrTiO3中至少一种,且二者厚度为10~200nm。
本发明第三方面提供一种非对称铁电隧道结的多值存储单元,使用如上述的制备方法制备而成;
其中,N个所述铁电功能层分别具有不同的矫顽场值,以使N个所述铁电功能层在激励作用下呈现出不同的极化差异。
本发明第四方面提供一种非对称铁电隧道结的多值存储单元的制备方法,其特征在于,所述方法包括:
提供衬底,采用物理气相沉积的方法在所述衬底上表面形成第一电极层;
采用原子层沉积、物理气相沉积或者旋转涂抹的方法在所述第一电极层上表面形成第一铁电功能层;
采用原子层沉积、物理气相沉积或者旋转涂抹的方法在所述第一铁电功能层上表面形成第一绝缘层;
采用原子层沉积、物理气相沉积或者旋转涂抹的方法在所述第一绝缘层上表面形成第二铁电功能层;
采用物理气相沉积的方法在所述第二铁电功能层上表面形成第二电极层;
将所述第一、第二铁电功能层晶化,以使第一、第二铁电功能层材料呈现铁电性能;
其中,第一、第二铁电功能层的形成工艺期间的物理参数不同,以使二者呈现不同的矫顽场值。
进一步地,所述物理参数包括以下至少一项:铁电功能层材料类型、铁电功能层材料掺杂方式、铁电功能层晶化条件以及铁电功能层材料的厚度。
进一步地,其中,
所述第一、第二铁电功能层的制备材料选自掺杂或者未掺杂的HfO2、Hf
xZr
1-xO
2、BiFeO
3、BaTiO
3、Pb(Zr
1-xTi
x)O
3、Sr
xBa
1-xO
3、聚偏氟乙烯中至少一种,且其厚度为2~20nm;
所述第一绝缘层的制备材料选自Al、Si、Hf、Zr、Ta、Ti的氧化物中至少一种,且其厚度为0.5~3nm;
所述第一、第二电极层的制备材料选自多晶硅、Al、TiN、TaN、W、Ni、Ta、SrRuO3、Nd:SrTiO3中至少一种,且二者厚度为10~200nm。
本发明第五方面,提供一种非对称铁电隧道结的多值存储单元,使用如上述的制备方法制备而成;
其中,所述第一铁电功能层的矫顽场值不同于第二铁电功能层,以使所述第一、第二铁电功能层在激励作用下呈现出不同的极化差异。
本发明第六方面提供一种非对称铁电隧道结的多值存储器,包括上述的非对 称铁电隧道结的多值存储单元。
总体而言,通过本发明所构思的以上技术方案与现有技术相比,具有以下有益效果:
(1)本发明所提供的基于非对称铁电隧道结的多值存储器,通过在金属电极之间插入多层铁电功能层和绝缘层的方法,增加了多个调制绝缘隧穿层势垒高度的变量。可以通过施加不同的大小及方向的脉冲调制多个铁电功能层的极化方向,从而调制隧穿层势垒的高低,实现了多种不同的存储状态。基于铁电极化翻转的调制方式具有速度快、功耗低的优势,从而制备的铁电材料存储器件,具有非易失、读取功耗低的特点;同时在一个存储单元中实现多种不同的存储状态,可以大幅度提高存储密度以及单位存储容量;
(2)本发明所提供的基于非对称铁电隧道结的多值存储器的制备方法,其制备工艺与CMOS工艺兼容,通过采用不同的掺杂方法,或不同的铁电材料,或对同一种铁电材料进行不同温度的退火或者采用同一种铁电材料但采用不同的厚度实现多层铁电功能层的矫顽场不同,方法简单,可操作性强;
(3)本发明所提供的基于非对称铁电隧道结的多值存储器的应用,利用该器件在一个存储单元中具有多种不同的存储状态,以及速度快、低功耗、非易失的优势,可以应用于低功耗的多值存储芯片、存内计算芯片等,在物联网、信息处理等领域具有极大的应用前景。
图1为按照本发明实现的非对称铁电隧道结的多值存储单元的结构示意图;
图2为按照本发明实现的优选的非对称铁电隧道结的多值存储单元的结构示意图;
图3为按照本发明实现实施例1的非对称铁电隧道结的多值存储单元在不同状态下铁电层的剩余极化仿真图;
在所有附图中,相同的附图标记用来表示相同的元件或结构,其中:第一电极层-1,非对称铁电功能层阵列-11,第二电极层-5,第一铁电功能层-2,第一绝缘层-3,第二铁电功能层。
为了使本发明的目的、技术方案及优点更加清楚明白,以下结合附图及实施 例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。此外,下面所描述的本发明各个实施方式中所涉及到的技术特征只要彼此之间未构成冲突就可以相互组合。
本领域的技术人员容易理解,以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。
众所周知,铁电材料本身在外加激励的作用下可以发生极化翻转,且内部极化状态与外激励成非线性关系,并且由于极化取向的缘故,其存在两个稳定的相反极化状态;由此产生的铁电材料的隧穿结(“金属-铁电功能层-绝缘层-金属”结构),其通过施加外激励使铁电功能层产生不同的极化状态,可调控铁电功能层与绝缘层界面隧穿势垒的高低从而调控可隧穿的电荷量,形成高低两种阻态。因此,本发明基于单层铁电隧穿结良好的存储特性提出一种非对称铁电隧道结的多值存储单元及其制备方法。
<非对称铁电隧道结的多值存储单元>
如图1所示,本发明第一方面提供一种非对称铁电隧道结的多值存储单元,沿纵向方向由下至上依次包括:第一电极层1、非对称铁电功能层阵列11、第二电极层5。
本发明中,非对称铁电功能层阵列11是由N个平行于横向平面的铁电功能层构成,且相邻两层所述铁电功能层之间通过绝缘层隔离,即由N个铁电功能层与N-1个绝缘层交错堆叠形成,整个铁电材料的隧穿结沿纵向平面方向由下至上为“金属-第一铁电功能层-第一绝缘层-第二铁电功能层-第二绝缘层-……-第N-1绝缘层-第N铁电功能层-金属”的结构。
本发明中,基于铁电隧穿结存储单元的特性提出一种多层结构的非对称铁电隧道结多值存储单元,其通过在两个金属电极之间插入N个平行于横向平面方向的铁电功能层,且这N个铁电功能层分别具有不同的矫顽场性能参数,从而增加了N-1调制变量。矫顽场是铁电材料在外加电场作用下极化状态发生翻转的临界场强,因此该非对称铁电功能层阵列11在不同的外激励条件下,N个铁电功能层会呈现出不同的极化方向;撤除外激励以后,该N个铁电功能层中也仍保持不同程度的剩余极化强度;随后再施加一定逻辑外激励时,由于N个铁电 功能层剩余极化方向以及强度各不相同,可以使得整个非对称铁电功能层阵列11呈现2
N个阻态,应用在一个存储单元中可以实现2
N种不同的存储状态。
如图2所示,根据一种具体的实施方式,当N为2时,非对称铁电功能层阵列11具有2个铁电功能层,如图2所示,该多值存储单元沿纵向方向由下至上依次包括:第一电极层1、第一铁电功能层2、第一绝缘层3、第二铁电功能层4、第二电极层5。其中第一铁电功能层2与第二铁电功能层3矫顽场大小不同,通过施加不同的大小及方向的外激励可以调制两个铁电功能层的极化大小和方向,从而改变整个材料的隧穿势垒,使非对称铁电功能层阵列11呈现4种不同的阻态,对应的4种状态可用以代表二进制数字系统中的“00”、“01”、“10”、“11”状态表示,在一个存储单元中实了现4种不同的存储状态,可以大幅度提高存储密度以及单位存储容量。
其中,铁电功能层主要输运机制为载流子的漂移扩散。即在外激励作用下,铁电材料中的电荷/载流子可越过一定势垒在纵向方向运动,产生不同数值的电流。
具体地,N个铁电功能层分别具有不同的矫顽场性能参数,因此该N个铁电功能层之间具有不同的物理参数差异:1)不同类型的材料;2)同一材料,掺杂方式不同;3)同一材料,晶化使用退火温度不同;4)同一材料,铁电功能层厚度不同;至少选择上述一项条件或者上述条件混合。更具体地,N个铁电功能层矫顽场差异越大,则调制不同阻态越容易,存储单元误读几率越小。
更具体地,使用不同类型的材料制备不同铁电功能层,具有铁电特性材料包括:含氧八面体、含氟八面体、含氢键的铁电体、铁电聚合物、铁电液晶、铪基铁电材料等,采用具有不同矫顽场的铁电材料即可。进一步地,铁电功能层的制备材料选自掺杂或者未掺杂的HfO
2、Hf
xZr
1-xO
2、BiFeO
3、BaTiO
3、Pb(Zr
1-xTi
x)O
3、Sr
xBa
1-xO
3、聚偏氟乙烯中至少一种,但不限于此。
更具体地,使用同一材料而掺杂方式不同制备不同铁电功能层,可选用基于掺杂HfO
2的铁电材料,通过调控HfO
2掺杂比例、掺杂元素等,使其具有不同矫顽场。
更具体地,使用同一材料而晶化使用退火温度不同制备不同铁电功能层,使用不同的晶化温度,使铁电材料具有不同的晶化程度或晶体类型,从而改变其矫 顽场性能。
更具体地,使用同一材料而铁电功能层厚度不同制备不同铁电功能层,其极化程度受厚度影响,厚度差别越大,其矫顽场性能差异越大。
具体地,N为大于等于2的整数,更具体地为2~4,最具体地为2。这是因为非对称铁电功能层阵列11的厚度不宜过高,否则电流过小难以读出,N越大则其铁电功能层越薄,铁电功能层的退极化场越大,极化状态难以保存,而且界面效应导致的应力、层间耦合以及相变会导致铁电功能层铁电性的退化,使其无法稳定地呈现出具有一定差异地2
N种阻态。且随着N值的增多,器件的操作也会更加复杂,不利于器件的实际应用。
具体地,非对称铁电功能层阵列11中每个铁电功能层厚度为2-20nm,更具体地为10nm。如果铁电功能层的厚度小于2nm,退极化场强过大,极化状态难以保存,同时铁电功能层材料在经过多次循环外激励后,材料晶格容易受损,其可开关的极化强度也会明显降低;随着铁电功能层厚度的增加,相同电压下通过铁电功能层的电荷量会变少,如果铁电功能层厚度大于20nm,通过铁电功能层的电荷量过少,使得电流太小而难以准确读出存储状态。
本发明中,绝缘层为可隧穿的绝缘层,其用于隔离两种不同矫顽场的铁电功能层。具体地,绝缘层结构致密,缺陷少,禁带宽,施加外激励时载流子/电荷只能通过直接隧穿的方式穿过,而难以通过其他方式流过。更具体地,施加外激励时,绝缘层的电子亲合能小于所有的铁电功能层,从而使铁电功能层中载流子/电荷不会自发迁移至绝缘层中。
如图2所示,根据一种具体的实施方式,第一电极层1和第二电极层5与第一、第二铁电功能层之间成肖特基接触,在一定的偏压下,注入电子可以越过肖特基势垒进入铁电功能层导带中,通过漂移扩散进行导电;第一绝缘层3的电子亲和能大于第一铁电功能层2和第二铁电功能层4,即第一绝缘层3的禁带宽度大于两个铁电功能层,电子无法通过漂移扩散通过第一绝缘层3进入第一或者第二铁电功能层。由于第一、第二铁电功能层的铁电极化使得第一绝缘层3能带弯曲,而第一绝缘层3又足够薄,这时电子就可以通过直接隧穿的方式通过第一绝缘层3进入第一或者第二铁电功能层,再通过漂移扩散进入第一或者第二电极层。
具体地,绝缘层的材料选自Al、Si、Hf、Zr、Ta、Ti的氧化物等绝缘性材料中至少一种,但不限于此。例如Al
2O
3、SiO
2中至少一种。
具体地,绝缘层的厚度小于5nm;更具体地,绝缘层的厚度为0.5nm~3nm,如果厚度大于3nm,则可隧穿载流子/电荷太小,导致读取电流差距太小,容易出现误读;如果厚度小于0.5nm,则未起到隔离作用。
具体地,第一电极层1和第二电极层5可以为与CMOS工艺兼容的材料,包括多晶硅、Al、TiN、TaN、W、Ni、Ta中至少一种,但不限于此;例如TiN、TaN等中至少一种。还可以为适合铁电材料生长的导电材料,例如适合钙钛矿结构铁电材料生长的SrRuO
3、Nd:SrTiO
3等材料中至少一种。
具体地,第一电极层1和第二电极层5厚度为10nm~200nm,更具体地,为100nm。
本发明中,非对称铁电隧道结的多值存储还包括衬底,其沿纵向方向由下至上依次包括:衬底、第一电极层1、非对称铁电功能层阵列11、第二电极层5。
本发明中,施加外激励为施加电能、热能、光能、电磁能等至少一种,具体地为施加电能,更具体地为施加外加电压。
<非对称铁电隧道结的多值存储器/芯片>
本发明第二方面提供一种非对称铁电隧道结的多值存储器、芯片,其包括上述非对称铁电隧道结的多值存储单元。
根据一种具体的实施方式,当N为2时,该非对称铁电功能层单元包括2个铁电功能层,因此可以在一个存储单元中实现4种不同的存储状态,使用该存储单元可以制备出具有4种存储状态的多值存储器、芯片,大幅度地提高存储密度以及单位存储容量;同时,该非对称铁电隧道结的多值存储器/芯片作为一种多值非易失存储器可以应用存内计算等存算一体芯片中。
<非对称铁电功能层阵列的制备方法>
本发明第三方面提供一种上述非对称铁电功能层阵列11的制备方法的制备方法,该方法包括以下步骤:
步骤1:提供第一电极层1,在所述第一电极层1上表面形成N个平行于第一平面方向的铁电功能层,相邻两层所述铁电功能层之间通过绝缘层隔离;
步骤2:将所述铁电功能层晶化,以使N个所述铁电功能层材料呈现铁电性 能;
本发明中,步骤1中,N为大于等于2的整数,即铁电功能层至少有两层,且相邻的两个铁电功能层之间存在一个绝缘层,即由N个铁电功能层与N-1个绝缘层交错堆叠形成非对称铁电功能层阵列11,则具体步骤如下:
在所述电极层上表面形成第i铁电功能层;
在所述第i铁电功能层上表面形成第j绝缘层;
在所述第j绝缘层上表面形成第(i+1)铁电功能层;
将所述铁电功能层晶化,以使N个所述铁电功能层材料呈现铁电性能;
具体地,i为所述铁电功能层沿垂直第一平面方向由下至上的序号,i=1,2,……N,j为所述绝缘层沿垂直第一平面方向由下至上的序号,j=1,2,……N-1。
本发明中,步骤1~2中,铁电功能层和绝缘层的生长方法包括:原子层沉积法(ALD)、物理气相沉积法(PVD)或者旋转涂抹法中至少一种,但不限于此。具体地,使用原子层沉积法(ALD)。
根据一种具体的实施方式,当N为2时,则该非对称铁电隧道结的多值存储单元制备方法包括如下步骤:
步骤1-1:提供第一电极层1,在所述第一电极层1上表面采用ALD或PVD或旋涂的方式生长第一铁电功能层2;
步骤1-2:在所述第一铁电功能层2上表面采用ALD或PVD的方式生长第一绝缘层3;
步骤1-3:在所述第一绝缘层3上表面采用ALD或PVD或旋涂的方式生长第二铁电功能层;
步骤2:将所述铁电功能层晶化,以使N个所述铁电功能层材料呈现铁电性能;
本发明中,在N个所述铁电功能层形成期间,所述第i铁电功能层的物理参数不同于所述第(i+1)铁电功能层的物理参数,以使N个所述铁电功能层之间呈现矫顽场的性能差异。
具体地,所述物理参数包括以下至少一项:铁电功能层材料类型、铁电功能层材料掺杂方式、铁电功能层晶化条件以及铁电功能层材料的厚度。
其中,如果铁电功能层材料选用的类型不同,则可以直接选用不同的铁电材 料采用原子层沉积法(ALD)、物理气相沉积法(PVD)或者旋转涂抹法中至少一种在第一电极表面沉积。
其中,如果铁电功能层材料选用同一类型,可以使用铁电功能层材料掺杂的比例和工艺调控不同铁电功能层的矫顽场值。具体地,使用原子层沉积技术制备Si:HfO
2铁电功能层和Al:HfO
2铁电功能层,沉积HfO
2过程中分别沉积Si和Al的原子层,通过控制沉积不同的原子层控制矫顽场值。此外,还可以使用铁电功能层材料的厚度调控不同铁电功能层的矫顽场值。具体地,使用原子层沉积技术制备Hf/Zr比例为1:1的HZO铁电功能层,交替沉积HfO
2和ZrO
2单原子层薄膜,通过控制交替沉积的厚度控制矫顽场值。最后,还可以使用铁电功能层晶化条件调控不同铁电功能层的矫顽场值。具体地,可以通过控制退火的最高温度或者退火的时间控制矫顽场值。
具体地,原子层沉积法是将铁电功能层、绝缘层的材料物质以单原子膜形式一层一层的镀在下层材料表面的方法,同时通过单原子镀膜的次数控制不同层的厚度,原子沉积反应腔的温度为200~400℃。
具体地,物理气相沉积法为磁控溅射法,通过控制溅射时间控制不同层的厚度。例如制备TiN电极时,溅射功率为100~200W,溅射时间为1000~1500s,惰性气体为Ar气,压强为0.2~0.8Pa;更具体地,溅射功率为150W,溅射时间为1200s,惰性气体为Ar气,压强为0.5Pa。
具体地,所述物理参数包括以下至少一项:铁电功能层材料掺杂方式、铁电功能层材料类型、铁电功能层晶化条件以及铁电功能层材料的厚度。
具体地,旋转涂抹法将轴旋转垂直于下层表面,同时把液态涂覆材料涂覆在下层表面,通过控制旋转涂抹的时间控制不同层的厚度。
<非对称铁电隧道结的多值存储单元制备方法>
本发明提供一种上述非对称铁电隧道结的多值存储单元的制备方法,该多值存储单元包括上述的
方法包括以下步骤:
步骤1:提供衬底,在所述衬底上表面形成第一电极层1;
步骤2:在所述第一电极层1上表面形成非对称铁电功能层阵列11,其包括:N个平行于第一平面方向的铁电功能层,相邻两层所述铁电功能层之间通过绝缘 层隔离;
步骤3:在第N铁电功能层上表面形成第二电极层5;
步骤4:将所述铁电功能层晶化,以使所述铁电功能层材料呈现铁电性能;
本发明中,步骤2中,N为大于等于2的整数,即铁电功能层至少有两层,且相邻的两个铁电功能层之间存在一个绝缘层,即由N个铁电功能层与N-1个绝缘层交错堆叠形成非对称铁电功能层阵列11,则具体步骤如下:
步骤2-1:在所述第一电极上表面形成第i铁电功能层;
步骤2-2:在所述第i铁电功能层上表面形成第j绝缘层;
步骤2-3:在所述第j绝缘层上表面形成第(i+1)铁电功能层;
具体地,i为所述铁电功能层沿垂直第一平面方向由下至上的序号,i=1,2,……N,j为所述绝缘层沿垂直第一平面方向由下至上的序号,j=1,2,……N-1。
本发明中,步骤1中,采用物理气相沉积法(PVD)的方式在衬底上表面沉积第一电极层1。具体地,衬底为单面抛光生长有SiO2的单晶硅,物理气相沉积法(PVD)为磁控溅射的方法。更具体地,先将衬底使用丙酮在超声环境下清洗5~20分钟,再使用酒精在超声环境下清洗5~20分钟,用去离子水冲洗,最后使用氮气枪吹干;使用磁控溅射的溅射功率为150W,溅射时间为1200s,惰性气体为Ar气,压强为0.5Pa。
本发明中,步骤2中,采用原子层沉积法(ALD)、物理气相沉积法(PVD)或者旋转涂抹法的方式沉积制备非对称铁电功能层阵列11。具体地,使用原子层沉积法(ALD)以单原子膜形式一层一层的镀在第一电极材料或者对应的铁电功能层、绝缘层的上表面,同时通过单原子镀膜的次数来控制不同层的厚度,原子沉积反应腔的温度为200~400℃。
本发明中,步骤3中,可以采用物理气相沉积法(PVD)的方式沉积制备第二电极层5。具体地,使用磁控溅射法;更具体地,首先在第N层铁电功能层上利用光刻在光刻胶上定义出第二电极层5图形,沉积第二电极层5材料,剥离形成第二电极层5图形,再去除光刻胶。具体地,使用磁控溅射;更具体地,首先在第N层铁电功能层上表面利用光刻在光刻胶上定义出第二电极层5图形,沉积第二电极层5材料,剥离形成第二电极层5图形。
本发明中,步骤4中,采用退火的方式使所沉积的铁电功能层结晶,生成铁 电相,表现出铁电性。具体地,采用氮气氛围快速退火的方式。
根据一种具体的实施方式,当N为2时,则该非对称铁电隧道结的多值存储单元制备方法包括如下步骤:
步骤1:提供衬底,在该衬底上表面采用PVD的方式在衬底上沉积第一电极;
步骤2-1:在该第一电极表面采用ALD或PVD或旋涂的方式生长第一铁电功能层2;
步骤2-2:在该第一铁电功能层2表面采用ALD或PVD的方式生长绝缘层;
步骤2-3:在该绝缘层表面采用PVD的方式生长第二铁电功能层;
步骤3:利用光刻在在第二铁电功能层表面光刻胶上定义出第二电极层5图形,沉积第二电极层5材料,剥离形成第二电极层5图形。
步骤4:采用退火的方式使所沉积第一、第二铁电功能层材料结晶,生成铁电相,表现出铁电性。
<非对称铁电隧道结的多值存储单元的调制方法>
为了使上述非对称铁电隧道结的多值存储单元具有多值存储的特性,本发明第四方面提供一种非对称铁电隧道结的多值存储单元的调制方法。
本发明中,非对称铁电隧道结的多值存储单元通过在两个金属电极之间插入N个平行于横向平面方向的铁电功能层,且这N个铁电功能层分别具有不同的矫顽场性能参数,相对于单层铁电存储单元而言增加了N-1调制变量。矫顽场是衡量不同铁电材料在相同外激励条件下的极化程度,因此该非对称铁电功能层阵列11通过在外激励的条件下,N个铁电功能层会呈现出不同的极化程度;通过撤除外激励以后,该N个铁电功能层中也仍存在不同程度的剩余极化电荷;随后再施加一定逻辑外激励时,由于N个铁电功能层剩余极化程度各不相同,可以使得整个非对称铁电功能层阵列11呈现2
N个阻态,应用在一个存储单元中可以实现2
N种不同的存储状态。
发明人给出了一种具体的实施方式,即当N为2时,并假定第二铁电功能层的矫顽场大于第一铁电功能层2,且第一、第二铁电功能层极化方向为顶电极到底电极时为正极化,反之为负极化,这样的假定仅为表述方便,本发明涵盖了其相反情形,主张了其相应权利。具体如下:
(一)写操作,即施加一定条件的外激励,使非对称铁电隧道结的多值存储 单元呈现出不同程度的剩余极化电荷:
(1)写“00”:保持第一电极层1接地,在第二电极层5加一个合适的正向大电压V1,使两层铁电功能层的极化都为正向极化,V1的大小可视材料的矫顽场而定,若该电压太小,则无法使两层铁电功能层的极化都为正,导致信息的存储过弱,容易出现误读和误写,若该电压太大,可能在第一、第二铁电功能层材料中形成导电丝从而失去其整流特性,也就不能继续调控隧穿势垒高度。当两层铁电功能层的极化方向一致为正时,由于铁电功能层整体可以看为该层的两端积聚不同电性的电荷,因此不同电性的电荷会扭曲附近的能带分布,使得每层铁电功能层的下端电子势能较低,理论上在两层铁电功能层种均形成类似反阻挡层,通过极化的方向记该状态为“00”。
(2)写“01”:保持第一电极层1接地,在第二电极层5加一个合适的正向大电压V1,使两层铁电功能层的极化都为正向极化,然后在顶电极加一个合适的反向小电压V2,使矫顽场较小的第一层铁电功能层反向极化,而矫顽场较大的第二铁电功能层极化方向不变,V2的大小视实际材料而定,若该电压太小,则无法使第一层铁电功能层发生反向极化翻转,造成信息写入失败,若该电压太大,则会使两层铁电功能层均发生反向极化翻转,造成信息的写入错误。当电压大小选取得当,进行上述操作后,第一层铁电功能层极化为负,第二铁电功能层极化为正,因此两层铁电功能层在近绝缘层处有正电荷积聚使电子势能降低,理论上形成第一层铁电功能层的类似阻挡层和第二铁电功能层的类似反阻挡层,通过极化的方向记该状态为“01”。
(3)写“11”:保持第一电极接地,在第二电极层5加一个合适的反向大电压V3,使两层铁电功能层的极化都为反向极化,V3的大小视材料的矫顽场而定,与V1的选取规则相同。当两层铁电功能层的极化方向一致为负时,两层铁电功能层的靠近第二电极层5的一端积聚正电荷,则在第一层铁电功能层和第二铁电功能层均形成类似阻挡层,通过极化的方向记该状态为“11”;
(4)写“10”。保持第一电极接地,在第二电极层5加一个合适的反向大电压V3,使两层铁电功能层的极化都为反向极化,然后在第二电极层5加一个合适的正向小电压V4,使矫顽场较小的第一层铁电功能层正向极化,而矫顽场较大的第二铁电功能层极化方向不变,V4的大小选取与V2的选取规则一致。当电压大 小选取得当,进行上述操作后,器件第一层铁电功能层极化为正,器件第二铁电功能层极化为负,因此两层铁电功能层在近绝缘层处有负电荷积聚使电子势能增大,理论上形成第一层铁电功能层的类似反阻挡层和第二铁电功能层的类似阻挡层,通过极化的方向记该状态为“10”。
(二)读操作,即施加一定条件外激励时,可以使得整个非对称铁电功能层阵列11呈现4个阻态,应用在一个存储单元中可以实现4种不同的存储状态。
读操作:保持第一电极层1接地,在第二电极层5加一个合适的正向小电压V5,该正向小电压大小的选取规则应保证不足以使矫顽场较小的第一铁电功能层2的极化方向发生变化,之后读取顶电极的电流大小,即可读出所存储信息。
通过下面的实施例可以更好地理解本发明的上述及其他优点,但是以下实施例并非用于限制本发明的范围。
实施例1
本实施例提供了一种基于Hf
0.5Zr
0.5O
2(以下简写为HZO)铁电薄膜以及Al
2O
3绝缘层的非对称铁电隧道结的多值存储单元,其结构示意图如图1所示,由下至上主要包括第一电极层1、第一铁电功能层2、绝缘层3、第二铁电功能层4、第二电极层5。具体步骤如下:
(一)第一电极层1的制备
步骤1:制备第一电极层1:实施例选用TiN作为下电极1,通过磁控溅射的方法,在单面抛光生长有SiO
2的单晶硅衬底上生长一层下电极1。
步骤1-1:衬底清洗:先使用丙酮在超声环境下清洗10分钟,再使用酒精在超声环境下清洗10分钟,用去离子水冲洗,最后使用氮气枪吹干;
步骤1-2:磁控溅射下电极1:使用TiN靶,在150W的直流溅射功率下,0.5Pa的Ar气分为中溅射1200s生长100nm的TiN底电极。
(二)非对称铁电功能层阵列11的材料沉积
步骤2:制备第一铁电功能层2
实施例选用10nm HZO铁电薄膜,通过原子层沉积技术得到Hf/Zr比例为1:1的HZO铁电薄膜。
ALD反应腔温度为300℃,TEMA-Hf源温度为80℃,TEMA-Zr源温度为90℃,在此条件下交替沉积HfO
2和ZrO
2单原子层薄膜,交替沉积50次。
步骤3:制备绝缘层3
实施例选用2nmAl
2O
3薄膜,通过原子层沉积技术得到2nm的致密Al
2O
3薄膜。
ALD反应腔温度为300℃,采用TMA源与H
2O反应生成Al
2O
3,生长20个cycle的Al
2O
3层。
步骤4:制备第二铁电功能层4
实施例选用5nm HZO铁电薄膜,通过原子层沉积技术得到Hf/Zr比例为1:1的HZO铁电薄膜。
ALD反应腔温度为300℃,TEMA-Hf源温度为80℃,TEMA-Zr源温度为90℃,在此条件下交替沉积HfO
2和ZrO
2单原子层薄膜,交替沉积25次。
(三)第二电极层5的制备
步骤5:制备第二电极层5:实施例选用TiN作为上电极5,通过光刻工艺在第二铁电功能层4上制备上电极5图形,通过磁控溅射的方法生长TiN上电极。
步骤5-1:光刻:通过光刻工艺在第二铁电功能层4上制备上电极5图形,其中光刻步骤包括匀胶、前烘、前曝、后烘、后曝、显影;
步骤5-2:溅射:实验使用TiN靶,在150W的溅射功率下,0.5Pa的Ar气氛围中溅射1200s生长100nm上电极;
步骤5-3:剥离:使用丙酮浸泡步骤5-2所制备出的薄膜样品,其间辅助以超声清洗,再依次用无水乙醇和去离子水清洗,最后用氮气枪吹干。
(四)非对称铁电功能层阵列11的材料晶化
步骤6:退火使铁电材料晶化
实施例采用氮气氛围快速退火的方式使第一铁电功能层2和第二铁电功能层4结晶,表现出铁电性。
快速退火具体设置为,在退火炉中通入氮气,退火温度设置为室温保温2min,1min从室温升高到500℃,500℃保持30s,2min从500℃降温到室温。
实施例2
本实施例提供了一种基于Si:HfO
2和Al:HfO
2铁电薄膜以及Al
2O
3绝缘层的非对称铁电隧道结的多值存储单元,其结构示意图如图1所示,由下至上主要包括下电极1、第一铁电功能层2、绝缘层3、第二铁电功能层4、上电极5。具体步骤如下:
(一)第一电极层1的制备
步骤1:制备第一电极层1:实施例选用TiN作为下电极1,通过磁控溅射的方法,在单面抛光生长有SiO
2的单晶硅衬底上生长一层下电极1。
步骤1-1:衬底清洗:先使用丙酮在超声环境下清洗10分钟,再使用酒精在超声环境下清洗10分钟,用去离子水冲洗,最后使用氮气枪吹干;
步骤1-2:磁控溅射下电极1:使用TiN靶,在150W的直流溅射功率下,0.5Pa的Ar气分为中溅射1200s生长100nm的TiN底电极。
(二)非对称铁电功能层阵列11的材料沉积
步骤2:制备第一铁电功能层2
实施例选用10nm Si:HfO
2铁电薄膜,通过原子层沉积技术得到Si含量为5%mol的Si:HfO
2铁电薄膜。
ALD反应腔温度为300℃,采用TEMA-Hf作为Hf源,4DMAS作为Si源,H
2O作为O源,在此条件下,首先生长19个cycle HfO
2层,然后生长1个cycle SiO
2层,如此重复生长5次,得到厚度为10nm的Si掺杂HfO
2薄膜。
步骤3:制备第一绝缘层3
实施例选用2nmAl
2O
3薄膜,通过原子层沉积技术得到2nm的致密Al
2O
3薄膜。
ALD反应腔温度为300℃,采用TMA源与H
2O反应生成Al
2O
3,生长20个cycle的Al
2O
3层。
步骤4:制备第二铁电功能层4
实施例选用10nm Al:HfO
2铁电薄膜,通过原子层沉积技术得到Al含量为6.25%mol的Al:HfO
2铁电薄膜。
ALD反应腔温度为300℃,采用TEMA-Hf作为Hf源,TMA作为Al源,H
2O作为O源,在此条件下,首先生长15个cycle HfO
2层,然后生长1个cycle Al
2O
3层,如此重复生长7次,得到厚度为10nm的Al掺杂HfO
2薄膜。
(三)第二电极层5的制备
步骤5:制备第二电极层5:实施例选用TiN作为上电极5,通过光刻工艺在第二铁电功能层4上制备上电极5图形,通过磁控溅射的方法生长TiN上电极。
步骤5-1:光刻:通过光刻工艺在第二铁电功能层4上制备上电极5图形, 其中光刻步骤包括匀胶、前烘、前曝、后烘、后曝、显影;
步骤5-2:溅射:实验使用TiN靶,在150W的溅射功率下,0.5Pa的Ar气氛围中溅射1200s生长100nm上电极;
步骤5-3:剥离:使用丙酮浸泡步骤5-2所制备出的薄膜样品,其间辅助以超声清洗,再依次用无水乙醇和去离子水清洗,最后用氮气枪吹干。
(四)非对称铁电功能层阵列11的材料晶化
步骤6:退火使铁电材料晶化
实施例采用氮气氛围快速退火的方式使第一铁电功能层2和第二铁电功能层4结晶,表现出铁电性。
快速退火具体设置为,在退火炉中通入氮气,退火温度设置为室温保温2min,1min从室温升高到800℃,800℃保持20s,2min从800℃降温到室温。
实施例3
本实施例提供了一种基于Hf
0.5Zr
0.5O
2(以下简写为HZO)和BiFeO
3(以下简称BFO)铁电薄膜以及Al
2O
3绝缘层的非对称铁电隧道结的多值存储单元,其结构示意图如图1所示,由下至上主要包括第一电极层1、第一铁电功能层2、绝缘层3、第二铁电功能层4、第二电极层5。具体步骤如下:
(一)第一电极层1的制备
步骤1:制备第一电极层1:实施例选用SrRuO
3作为下电极1,通过磁控溅射的方法,在单晶SrTiO
3衬底上生长一层下电极1。
步骤1-1:衬底清洗:先使用丙酮在超声环境下清洗10分钟,再使用酒精在超声环境下清洗10分钟,用去离子水冲洗,最后使用氮气枪吹干;
步骤1-2:磁控溅射下电极1:使用SrRuO
3靶,沉积温度为600℃,采用Ar/O
2比为1:4的Ar/O
2混合气,工作压强为3Pa,溅射功率为80W,沉积50nmSrRuO
3下电极。
(二)非对称铁电功能层阵列11的材料沉积
步骤2:制备第一铁电功能层2
实施例选用20nm BFO铁电薄膜,通过激光脉冲沉积(PLD)的方式进行沉积。
PLD沉积温度为700℃,靶基距为78mm,O
2分压为30mTorr,激光功率为 50mJ,频率为10Hz,沉积5000个脉冲,得到20nmBFO铁电薄膜。
步骤3:制备第一绝缘层3
实施例选用2nmAl
2O
3薄膜,通过原子层沉积技术得到2nm的致密Al
2O
3薄膜。
ALD反应腔温度为300℃,采用TMA源与H
2O反应生成Al
2O
3,生长20个cycle的Al
2O
3层。
步骤4:制备第二铁电功能层4
实施例选用5nm HZO铁电薄膜,通过原子层沉积技术得到Hf/Zr比例为1:1的HZO铁电薄膜。
ALD反应腔温度为300℃,TEMA-Hf源温度为80℃,TEMA-Zr源温度为90℃,在此条件下交替沉积HfO
2和ZrO
2单原子层薄膜,交替沉积25次。
(三)第二电极层5的制备
步骤5:制备第二电极层5:实施例选用TiN作为上电极5,通过光刻工艺在第二铁电功能层4上制备上电极5图形,通过磁控溅射的方法生长TiN上电极。
步骤5-1:光刻:通过光刻工艺在第二铁电功能层4上制备上电极5图形,其中光刻步骤包括匀胶、前烘、前曝、后烘、后曝、显影;
步骤5-2:溅射:实验使用TiN靶,在150W的溅射功率下,0.5Pa的Ar气氛围中溅射1200s生长100nm上电极;
步骤5-3:剥离:使用丙酮浸泡步骤5-2所制备出的薄膜样品,其间辅助以超声清洗,再依次用无水乙醇和去离子水清洗,最后用氮气枪吹干。
(四)非对称铁电功能层阵列11的材料晶化
步骤6:退火使铁电材料晶化
实施例采用氮气氛围快速退火的方式使第一铁电功能层2和第二铁电功能层4结晶,表现出铁电性。
快速退火具体设置为,在退火炉中通入氮气,退火温度设置为室温保温2min,1min从室温升高到500℃,500℃保持30s,2min从500℃降温到室温。
实施例4
本实施例提供了一种基于不同退火温度的Hf
0.5Zr
0.5O
2(以下简写为HZO)铁电薄膜以及Al
2O
3绝缘层的非对称铁电隧道结的多值存储单元,其结构示意图如图1所示,由下至上主要包括第一电极层1、第一铁电功能层2、绝缘层3、第 二铁电功能层4、第二电极层5。具体步骤如下:
(一)第一电极层1的制备
步骤1:制备第一电极层1:实施例选用TiN作为下电极1,通过磁控溅射的方法,在单面抛光生长有SiO2的单晶硅衬底上生长一层下电极1。
步骤1-1:衬底清洗:先使用丙酮在超声环境下清洗10分钟,再使用酒精在超声环境下清洗10分钟,用去离子水冲洗,最后使用氮气枪吹干;
步骤1-2:磁控溅射下电极1:使用TiN靶,在150W的直流溅射功率下,0.5Pa的Ar气分为中溅射1200s生长100nm的TiN底电极。
(二)非对称铁电功能层阵列11的材料沉积和退火
步骤2:制备第一铁电功能层2
实施例选用10nm HZO铁电薄膜,通过原子层沉积技术得到Hf/Zr比例为1:1的HZO铁电薄膜。
ALD反应腔温度为300℃,TEMA-Hf源温度为80℃,TEMA-Zr源温度为90℃,在此条件下交替沉积HfO
2和ZrO
2单原子层薄膜,交替沉积50次。
步骤3:退火使第一铁电功能层2材料晶化
实施例采用氮气氛围快速退火的方式使第一铁电功能层2结晶,表现出铁电性。
快速退火具体设置为,在退火炉中通入氮气,退火温度设置为室温保温2min,1min从室温升高到500℃,500℃保持30s,2min从500℃降温到室温。
步骤3:制备第一绝缘层3
实施例选用2nmAl
2O
3薄膜,通过原子层沉积技术得到2nm的致密Al
2O
3薄膜。
ALD反应腔温度为300℃,采用TMA源与H
2O反应生成Al
2O
3,生长20个cycle的Al
2O
3层。
步骤4:制备第二铁电功能层4
实施例选用5nm HZO铁电薄膜,通过原子层沉积技术得到Hf/Zr比例为1:1的HZO铁电薄膜。
ALD反应腔温度为300℃,TEMA-Hf源温度为80℃,TEMA-Zr源温度为90℃,在此条件下交替沉积HfO
2和ZrO
2单原子层薄膜,交替沉积25次。
(三)第二电极层5的制备
步骤5:制备第二电极层5:实施例选用TiN作为上电极5,通过光刻工艺在第二铁电功能层4上制备上电极5图形,通过磁控溅射的方法生长TiN上电极。
步骤5-1:光刻:通过光刻工艺在第二铁电功能层4上制备上电极5图形,其中光刻步骤包括匀胶、前烘、前曝、后烘、后曝、显影;
步骤5-2:溅射:实验使用TiN靶,在150W的溅射功率下,0.5Pa的Ar气氛围中溅射1200s生长100nm上电极;
步骤5-3:剥离:使用丙酮浸泡步骤5-2所制备出的薄膜样品,其间辅助以超声清洗,再依次用无水乙醇和去离子水清洗,最后用氮气枪吹干。
(四)第二铁电功能层4的材料晶化
步骤6:退火使第二铁电功能层4材料晶化
实施例采用氮气氛围快速退火的方式使第二铁电功能层4结晶,表现出铁电性。
快速退火具体设置为,在退火炉中通入氮气,退火温度设置为室温保温2min,1min从室温升高到400℃,400℃保持30s,2min从400℃降温到室温。
测试例:实施例1中一种基于HZO铁电薄膜以及Al2O3绝缘层的非对称铁电隧道结的多值存储单元的调制方法,由于第一铁电功能层2的厚度小于第二铁电功能层4,因此第二铁电功能层4的矫顽场大于第一铁电功能层2的矫顽场,则其调制方法包括以下“写”“读”两个步骤:
(一)“写”信息操作,具体如下:
规定从第二电极层5到第一电极层1的方向为正,正极化为“0”状态,负极化为“1”状态。根据需要存储的信息,选择以下四种操作中的一种:
(1)写“00”:给第二电极层5和第一电极层1之间施加一合适的正向大电压V1,使第一层铁电功能层2和第二铁电功能层4的的极化都为正向极化。第一、第二铁电功能层的极化方向一致为正,由于铁电功能层整体可以看为该层的两端积聚不同电性的电荷,因此不同电性的电荷会扭曲附近的能量分布,使得第一层铁电功能层2的下端21和第二铁电功能层4的下端41的电子势能较低,在第一、第二铁电功能层种均形成类似反阻挡层,通过极化的方向记该状态为“00”,为图3中状态1。
(2)写“01”:给第二电极层5和第一电极层1之间施加一合适的正向大电 压V1,使第一层铁电功能层2和第二铁电功能层4的的极化都为正向极化,然后在第二电极层5加一个合适的反向小电压V2,使矫顽场较小的第一层铁电功能层2反向极化,而矫顽场较大的第二铁电功能层4极化方向不变。第一层铁电功能层2极化为负,第二铁电功能层4极化为正,因此第一层铁电功能层2上端22和第二铁电功能层4下端41有正电荷积聚使电子势能降低,形成第一层铁电功能层2的类似阻挡层和第二铁电功能层4的类似反阻挡层,通过极化的方向记该状态为“01”,为图3中状态2。
(3)写“11”:给第二电极层5和第一电极层1之间施加一合适的反向大电压V3,使第一层铁电功能层2和第二铁电功能层4的极化都为反向极化。第一、第二铁电功能层的极化方向一致为负,第一层铁电功能层2上端22和第二铁电功能层4上端42积聚正电荷,则在第一层铁电功能层2和第二铁电功能层4均形成类似阻挡层,通过极化的方向记该状态为“11”,如图2中状态3。
(4)写“10”:给第二电极层5和第一电极层1之间施加一合适的反向大电压V3,使两层铁电功能层的极化都为反向极化,然后在第二电极层5加一个合适的正向小电压V4,使矫顽场较小的第一层铁电功能层2正向极化,而矫顽场较大的第二铁电功能层4极化方向不变。进行上述操作后,第一层铁电功能层2极化为正,第二铁电功能层4极化为负,因此第一层铁电功能层2的上端22和第二铁电功能层4的下端41有负电荷积聚使电子势能增大,形成第一层铁电功能层2的类似反阻挡层和第二铁电功能层4的类似阻挡层,通过极化的方向记该状态为“10”,如图3中状态4。
图3为按照本发明实现的非对称铁电隧道结的多值存储单元在不同状态下铁电层的剩余极化仿真图。
(二)“读”信息操作,具体如下:
当第二铁电功能层4形成类似反阻挡层时,此时第一层铁电功能层2的限制对通过第二电极层5的电流大小起主导作用,如图3中状态1和状态2,由于状态1的第一层铁电功能层2的隧穿势垒宽于状态2,因此相比之下状态1为高阻态,记为Z1态,而状态2电阻略低于状态1,记为Z2态。
当第二铁电功能层4形成类似阻挡层时,此时第二铁电功能层4的限制对通过第二电极层5的电流大小起主导作用,如图3中状态3和状态4,由于状态4 的第二铁电功能层4的隧穿势垒低于状态3,因此相比之下状态3为高阻态,记为Z3态,而状态4电阻略低于状态3,记为Z4态。
在第二电极层5和第一电极层1之间加一个合适的正向小电压V5,该正向小电压大小的选取规则应保证不足以使矫顽场较小的第一铁电功能层2的极化方向发生变化,之后读取顶电极的电流大小,即可读出所存储信息。具体四种状态对应电阻大小如表1所示。其中,表1所述极化方向向下是指从第二电极层5指向第一电极层1,向上是指从第一电极层1指向第二电极层5。
表1四种存储逻辑对应阻态参数
实施例1中采用制备不同厚度的HZO薄膜实现对第一、第二铁电功能层矫顽场大小的调控;实施例2中采用不同元素掺杂的HfO
2薄膜实现对第一、第二铁电功能层矫顽场大小的调控,其中两种不同元素掺杂的HfO
2薄膜的退火温度是一样的;实施例3直接采用两种不同的HZO和BFO铁电材料薄膜实现对第一、第二铁电功能层矫顽场大小的调控;实施例4采用相同HZO薄膜,而使用不同的退火温度实现对第一、第二铁电功能层矫顽场大小的调控。因此实施例提供了工艺上的可行性。通过测试例证明了有两种铁电功能层时,非对称铁电隧道结的多值存储单元可以调制出4种逻辑存储状态。基于实施例1~4说明,当铁电功能层为多层时,可以调节材料制备工艺实现不同铁电功能层矫顽场大小的调控,从而制备出具有多种隧穿阻态的存储单元。本领域技术人员是可以基于实施1~4制备方法和调制方法制备出具有多层铁电功能层的非对称铁电隧道结多值存储单元以及多值存储器。
本领域的技术人员容易理解,以上所述仅为本发明的实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。
Claims (14)
- 一种非对称铁电功能层阵列的制备方法,其特征在于,所述非对称铁电功能层阵列由N个铁电功能层和N-1个绝缘层交替堆叠形成,所述方法包括以下步骤:提供电极层,在所述电极层上表面生长N个平行于第一平面方向的铁电功能层,且相邻的所述铁电功能层之间通过绝缘层隔离,包括:在所述电极层上表面形成第i铁电功能层;在所述第i铁电功能层上表面形成第j绝缘层;在所述第j绝缘层上表面形成第(i+1)铁电功能层;将所述铁电功能层晶化,以使N个所述铁电功能层材料呈现铁电性能;其中,N个所述铁电功能层的形成工艺期间的物理参数不同,以使N个所述铁电功能层呈现不同的矫顽场值;其中,N为大于等于2的整数,i为所述铁电功能层沿垂直第一平面方向由下至上的序号,i=1,2,……N,j为所述绝缘层沿垂直第一平面方向由下至上的序号,j=1,2,……N-1。
- 根据权利要求1所述的制备方法,其特征在于,所述物理参数包括以下至少一项:铁电功能层材料类型、铁电功能层材料掺杂方式、铁电功能层晶化条件以及铁电功能层材料的厚度。
- 一种非对称铁电隧道结的多值存储单元的制备方法,其特征在于,所述方法包括:提供衬底,在所述衬底上表面形成第一电极层;在所述第一电极层上表面形成非对称铁电功能层阵列,其包括:N个平行于第一平面方向的铁电功能层,且相邻的所述铁电功能层之间通过绝缘层隔离;在所述非对称铁电功能层阵列上表面形成第二电极层;其中,所述非对称铁电功能层阵列形成方法包括:提供第一电极层,在所述第一电极层上表面生长N个平行于第一平面方向的铁电功能层,且相邻的所述铁电功能层之间通过绝缘层隔离,包括:在所述电极层上表面形成第i铁电功能层;在所述第i铁电功能层上表面形成第j绝缘层;在所述第j绝缘层上表面形成第(i+1)铁电功能层;将所述铁电功能层晶化,以使N个所述铁电功能层材料呈现铁电性能;其中,N个所述铁电功能层的形成工艺期间的物理参数不同,以使N个所述铁电功能层呈现不同的矫顽场值;其中,N为大于等于2的整数,i为所述铁电功能层沿垂直第一平面方向由下至上的序号,i=1,2,……N,j为所述绝缘层沿垂直第一平面方向由下至上的序号,j=1,2,……N-1。
- 根据权利要求3所述的制备方法,其特征在于,所述物理参数包括以下至少一项:铁电功能层材料类型、铁电功能层材料掺杂方式、铁电功能层晶化条件以及铁电功能层材料的厚度。
- 根据权利要求3所述的制备方法,其特征在于,进一步包括:采用原子层沉积、物理气相沉积或者旋转涂抹的方法在所述第一电极层上表面交替生长N个的铁电功能层以及N-1个绝缘层。采用物理气相沉积的方法在所述衬底上表面生长第一电极层;采用物理气相沉积的方法在所述非对称铁电功能层阵列上表面形生长第二电极层。
- 根据权利要求3所述的制备方法,其特征在于,所述铁电功能层的制备材料选自掺杂或者未掺杂的HfO 2、Hf xZr 1-xO 2、BiFeO 3、BaTiO 3、Pb(Zr 1-xTi x)O 3、Sr xBa 1-xO 3、聚偏氟乙烯中至少一种,且其厚度为2~20nm。
- 根据权利要求3所述的制备方法,其特征在于,所述绝缘层的制备材料选自Al、Si、Hf、Zr、Ta、Ti的氧化物中至少一种,且其厚度为0.5~3nm。
- 根据权利要求3所述的制备方法,其特征在于,所述第一、第二电极层的制备材料选自多晶硅、Al、TiN、TaN、W、Ni、Ta、SrRuO 3、Nd:SrTiO 3中至少一种,且二者厚度为10~200nm。
- 一种非对称铁电隧道结的多值存储单元,使用如权利要求3~8任一项所述的制备方法制备而成;其中,N个所述铁电功能层分别具有不同的矫顽场值,以使N个所述铁电功能层在激励作用下呈现出不同的极化差异。
- 一种非对称铁电隧道结的多值存储单元的制备方法,其特征在于,所述方法包括:提供衬底,采用物理气相沉积的方法在所述衬底上表面形成第一电极层;采用原子层沉积、物理气相沉积或者旋转涂抹的方法在所述第一电极层上表面形成第一铁电功能层;采用原子层沉积、物理气相沉积或者旋转涂抹的方法在所述第一铁电功能层上表面形成第一绝缘层;采用原子层沉积、物理气相沉积或者旋转涂抹的方法在所述第一绝缘层上表面形成第二铁电功能层;采用物理气相沉积的方法在所述第二铁电功能层上表面形成第二电极层;将所述第一、第二铁电功能层晶化,以使第一、第二铁电功能层材料呈现铁电性能;其中,第一、第二铁电功能层的形成工艺期间的物理参数不同,以使二者呈现不同的矫顽场值。
- 根据权利要求10所述的制备方法,其特征在于,所述物理参数包括以下至少一项:铁电功能层材料类型、铁电功能层材料掺杂方式、铁电功能层晶化条件以及铁电功能层材料的厚度。
- 根据权利要求10所述的制备方法,其特征在于,其中,所述第一、第二铁电功能层的制备材料选自掺杂或者未掺杂的HfO 2、Hf xZr 1-xO 2、BiFeO 3、BaTiO 3、Pb(Zr 1-xTi x)O 3、Sr xBa 1-xO 3、聚偏氟乙烯中至少一种,且其厚度为2~20nm;所述第一绝缘层的制备材料选自Al、Si、Hf、Zr、Ta、Ti的氧化物中至少一种,且其厚度为0.5~3nm;所述第一、第二电极层的制备材料选自多晶硅、Al、TiN、TaN、W、Ni、Ta、SrRuO 3、Nd:SrTiO 3中至少一种,且二者厚度为10~200nm。
- 一种非对称铁电隧道结的多值存储单元,使用如权利要求10~12任一项所述的制备方法制备而成;其中,所述第一铁电功能层的矫顽场值不同于第二铁电功能层,以使所述第一、第二铁电功能层在激励作用下呈现出不同的极化差异。
- 一种非对称铁电隧道结的多值存储器,包括权利要求9或者12所述的非对称铁电隧道结的多值存储单元。
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