558796 、發明說明（） 發明 σ右：^明疋有關於一種半導體元件的製造方法，且特別 於—種在晶圓上形成多種等效氧化層厚度之閑介電 層的方法。 :符合電子產品輕、薄、短小與講求速度的需求 伴的製造趨勢傾向於單—系統晶Θ (加魏〇1^ 一 p SQC)的製造，亦即將傳統分開在不同晶片上製造的 兀件整合在單一晶片上。例如將記憶體、邏輯運算電路以 及周邊輸入/輸出的積體電路做在同一晶圓上以增進整體 積體電路之效能，因為三者的操作電壓以及需求特性不 同，所以需要不同厚度的閘介電層以因應同一晶圓上不同 電路功能之需求。 對於位在吕己憶體區之電晶體而言，最重要的是如何避 免漏電流的發生，以降低再補充（refresh)頻率，才能提升 記憶體的操作效率。所以記憶體區之電晶體需要具有較厚 之等效氧化層厚度（Equivalent Oxide Thickness ; Ε〇τ)的閘 介電層。而對於位在邏輯電路區之電晶體而言，最重要的 是如何提升運算速率，至於漏電流對其運算影響不大。 以邏輯電路區之電晶體需要具有較薄之等效氧化層厚度= 閘介電層。而位於周邊輸入/輸出的積體電路需要承a 電功率最大，所以其所需之閘介電層的等效氧化層严户為 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐） ^^^1 I m (請先閲讀背面之注意事項再填寫本頁) 訂. 經濟部智慧財產局員工消費合作社印製 558796 五、發明説明（） 最厚。 .—般所使用的方法是先在基底上形成-定厚度的問氧 化層，再使用濕蝕刻（wet dip)的方式，來移除基底上特定 區域的閘氧化層，然後再讓基底整個纟面進行—次熱氧: 步驟’以在同-基底上形成不同厚度的閘氧化層。若、要 兩種以上不同厚度的閘氧化層，則需要再重複上述：步 驟。但是此方法十分耗時’至少要花費i _ 2小時，常成 為生產線的瓶頸。此外，位於閘氧化層被濕餘刻區域之淺 溝渠隔離(.Shallow Treneh IsolatiGn; STI)和主動區接壤的 角落部分，亦會被餘刻，常造成高電場與漏電流等問題。 此外，閘氧化層之漏電流將會隨著其厚度的減少而增加， 使得電路元件在等候（standby)時，會消耗較大的功率，而 使產品無法符合商業用途所需。 因此本發㈣目的就是在提供—種在晶圓上形成多種 化層厚度之閉介電層的方法，以解決淺溝渠隔離的 、、、口構被損傷之問題。 效氧：:=另一目的是在提供一種在晶圓上形成多種等 介電層的方法，以減少淺溝渠隔離結構 才貝傷所導致之漏電流。 員 訂 效氧再二的是在提供一種在晶圓上形成多種等 曰子又之閘介電層的方法，以減少閘介電層的漏電 製 _^iiTiii^NS)A4^(2iGx297_ 五、發明説明（） 流。 很葆本發明之上述目的， 等效氧化層厚度之閑氧化層的方法晶=成多種 J有厚度之開氧化層，閘氧化層至少具有；成 弟-區域、第三區域與第四區域。"⑽或、 四區域之閘氧化層的第-厚度至第:厚區:與第 離子於第-區域與第四區域之間氧化層子中度。再末，植入氮 之閘施例，減少第三區域與第— 亩丄: 厚度至第二厚度的方式有兩種。-種： 〜刀与度另—種為將第三區域與第四區域之開4化思 次熱氧化法形成—層新的閘氧化層： 厚::會略— :士所述’因為第一區域與第四區域 入鼠離子，所以其等效氧化層厚度會比具有相同厚= 應用本發明的方法，可在同-晶圓上至少形成四二且= =化㈣的閘氧化層。又因為去除間氧= 夕至取低，且虱離子是植入於閘氧化層中，所以習 知的問題皆可獲得圓滿的解決。 根據本發明之上述目的，提出另_ 種等效氧化層厚度之时電層的方法。首先，進行 五 經濟部智慧財產局員工消費合作社印製 558796 A7 B7 、發明説明（ 乂驟，植入氮離子於基底中。然後依序形成第_ 金屬氧化層於基底上，其中金屬氧化層的材: I為乳化給或氧化銘。接著，圖案化金屬氧化層與 異以暴路出部分之基底表面。然後’形成第二閘氧 將出之基底表面’再進行第二氮離子植入步驟， 將鼠離子植入於金屬氧化層與第二閘氧化層中。最後 :::::度以增加金屬一 依照本發明另一較佳實施例，其中上述之第一氮離子 植入步驟與第二氮離子植入步驟例如可使用遠距電製或去 耦合電漿來植入就離子。形成金屬氧化層的方法包括有機 金屬化學氣相沈積法或原子層化學氣相沈積法。 一因此由上述可知，本發明利用具有高介電常數之金屬 氧，層來有效地減少閘介電層之等效氧化層厚度，並利用 含氮電椠處理以及回火等製程來增加介電層的完整性，以 ^少漏電流的發生。如此，基底上有金屬氧化層的區域與 沒有金屬氧化層的區域之等效氧化層厚度就不一樣了。 _圖式之簡單說明 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 第1A - 1D圖是繪示依照本發明一較佳實施例之一種 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐）558796, description of the invention () Invention σ Right: ^ Ming has a method of manufacturing a semiconductor element, and in particular-a method of forming a leisure dielectric layer of multiple equivalent oxide layers on a wafer. : In line with the demand for light, thin, short, and speed-conscious electronic products, the manufacturing trend tends to be single-system crystal Θ (Jiawei 〇1 ^ -p SQC), which is also about to separate traditionally manufactured components on different wafers. Integrated on a single chip. For example, memory, logic operation circuits, and peripheral input / output integrated circuits are made on the same wafer to improve the performance of the integrated integrated circuit. Because the operating voltage and demand characteristics of the three are different, gates of different thicknesses are required. The electrical layer responds to the needs of different circuit functions on the same wafer. For the transistor located in Lu Jiyi's body region, the most important thing is how to avoid the occurrence of leakage current so as to reduce the refresh frequency so as to improve the operating efficiency of the memory. Therefore, the transistor in the memory region needs a gate dielectric layer having a relatively thick Equivalent Oxide Thickness (E0τ). For transistors located in the logic circuit area, the most important thing is how to increase the operation rate, as the leakage current has little effect on the operation. The transistor in the logic circuit area needs to have a thinner equivalent oxide layer thickness = gate dielectric layer. The integrated circuit located at the peripheral input / output needs to support a maximum electrical power, so the equivalent oxide layer of the required gate dielectric layer is strictly based on the Chinese paper standard (CNS) A4 specification (210X 297 mm). ) ^^^ 1 I m (Please read the precautions on the back before filling out this page) Order. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 558796 5. The description of the invention () is the thickest. Generally, the method used is to first form an interlayer oxide layer with a fixed thickness on the substrate, and then use wet dip to remove the gate oxide layer in a specific area on the substrate, and then let the entire substrate 纟Surface-subthermal oxygen: step 'to form gate oxide layers of different thicknesses on the same substrate. If two or more gate oxide layers with different thicknesses are needed, the above steps need to be repeated. But this method is very time-consuming, which takes at least 2 hours, which often becomes the bottleneck of the production line. In addition, the part of the gate where the oxide layer of the gate is isolated by shallow trenches (.Shallow Treneh IsolatiGn; STI) and the active area will also be left uncut, often causing problems such as high electric fields and leakage currents. In addition, the leakage current of the gate oxide layer will increase as the thickness of the gate oxide layer decreases, so that circuit components will consume a large amount of power when they are in standby, making the product unable to meet the needs of commercial use. Therefore, the purpose of this development is to provide a method for forming a closed dielectric layer with various thicknesses on a wafer to solve the problem of damage to the trench structure. Effective oxygen :: = Another purpose is to provide a method for forming multiple isoelectric layers on the wafer to reduce leakage current caused by shallow trench isolation structures. In order to reduce the leakage of the gate dielectric layer, it is necessary to provide a method for forming multiple gate dielectric layers on the wafer to reduce the leakage of the gate dielectric layer. ^ IiTiii ^ NS) A4 ^ (2iGx297_ V. The description of the invention () flow. It is very clear that the above purpose of the present invention, the equivalent oxide layer thickness of the free oxide layer method. Crystal = a variety of open oxide layers with thickness, the gate oxide layer has at least; Region and the fourth region. &Quot; Or, the fourth-thickness to the first-thickness of the gate oxide layer of the four-region: the oxide layer is moderate with the first ion between the first-region and the fourth region. Finally, the plant In the example of the nitrogen gate, there are two ways to reduce the third area and the first area: the thickness to the second thickness. There are two ways. Formed by the thermal oxidation method-a new gate oxide layer: thick :: 会 略-: As stated in the 'Because rat ions are introduced in the first region and the fourth region, the equivalent oxide layer thickness will be the same. = Applying the method of the present invention, a gate oxide layer of at least four two and = thallium oxide can be formed on the same-wafer. In addition to oxygen = low at night, and lice ions are implanted in the gate oxide layer, so conventional problems can be satisfactorily solved. According to the above purpose of the present invention, another _ equivalent oxide layer thickness is proposed The method of the time and electricity layer. First, print the 558796 A7 B7, the invention description (the step of implanting nitrogen ions into the substrate. The _ metal oxide layer is sequentially formed on the substrate. In which, the material of the metal oxide layer: I is emulsified or oxidized. Then, the patterned metal oxide layer and the surface of the substrate out of which the circuit breaks out. Then 'form the surface of the substrate where the second gate oxygen will come out'. The dinitrogen ion implantation step implants rat ions into the metal oxide layer and the second gate oxide layer. Finally: :::: degree to increase the metal-according to another preferred embodiment of the present invention, wherein the first The nitrogen ion implantation step and the second nitrogen ion implantation step can be implanted with ions using, for example, a remote electrode system or a decoupling plasma. Methods for forming a metal oxide layer include an organic metal chemical vapor deposition method or an atomic layer chemistry Phase deposition method. Therefore, it can be known from the above that the present invention effectively reduces the equivalent oxide thickness of the gate dielectric layer by using a metal oxygen layer having a high dielectric constant, and uses processes such as nitrogen-containing hafnium treatment and tempering. To increase the integrity of the dielectric layer to reduce the occurrence of leakage current. In this way, the equivalent oxide layer thickness of the area with a metal oxide layer on the substrate is different from the area without a metal oxide layer. _Schematic simplicity In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and the following detailed description is given in conjunction with the accompanying drawings: Figures 1A-1D are illustrations According to a preferred embodiment of the present invention, the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm)
、-=& (請先閲讀背面之注意事項再填寫本頁j 558796、-= &Amp; (Please read the notes on the back before filling in this page j 558796
五、發明説明（） 在晶圓上形成多種等致氧化層 .剖面圖。 閘"電層的製造流程 第2A - 2D圖是繪示依照本發明另一 種在晶圓上形成多種等效氧化厚卢 Λ 程剖面圖。 ^化層厂子度之閘介電層的製造流 屬式之標記説明 100、200 :基底 110 :淺溝渠隔離 120、120a、130、140、 閘氧化層 160 :光阻 170、210、250 :氮離子 230 :金屬氧化層 140a、150、150a、220、240 (請先閲讀背面之注意事項再填寫本頁) '一 發明之詳細說明 經濟部智慧財產局員工消費合作社印製 如上所述’因為習知以反覆執行生長閘氧化層與濕蝕 刻的方式來在基底上不同區域形成不同厚度的閘氧化層， 造成製造過程耗時以及淺溝渠隔離和主動區接壤的角落部 分會產生漏電流的問題。所以本發明提供在晶圓上形成多 種等效氧化層厚度之閘介電層的方法，以解決習知的問 題0 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 五、發明説明（） 貫施例一 請參照第1A - 1D圖，其绛+分 例之-種在晶圓上形成多種等效氧化明一較佳實施 製造流程剖面圖。 ㈢厗度之閘介電層的 請參照第1A圖，先在其庇，Λ no,淺溝土 中形成淺溝渠隔離 在此：i: 成方法為熟悉此技藝者所孰知， 在此不再贅述。然後在基底1〇〇 *''' 1 ,n 1CA ^ ^ 成閑氧化層 120、130、 40與150.，其形成方法較佳為熱氧化法。 μ參照第1B圖，接著減少閑氧 #豆& Ί 化層140、150的厚度， == 。此步驟可用方法至少有兩種。 八2直接使用錢刻法來去除閘氧化層140、15〇的部 二子二：刻劑例如可為約1重量百分比濃度之氫氟酸。 另一種為先將閘氧化層14〇、15〇 —八 ^ A全去除之，然後再進 ^-:人熱氧化法，使基底⑽表面形成問氧化層i術 與⑽，同時間氧化層120、13〇的厚度也會略微增加。 “凊參照第1C圖，用光阻160將閘氧化们3〇與14如 覆盍起來，然後植入氮離子170於閘氧化g m與1地 中、。植入氮離子170於閘氧化| 12〇與15〇a中的方法較 ^ ^ ^ ^ it ^ t (remote plasma)^ ^ ^ f t (decoupled plasma)，在低於攝氏wo度下進行。 睛參照第ID圖，在植入氮離子17〇的步驟之後，去 除光阻160。閘氧化層丨2〇與15〇a的表層12〇a與15⑽含 有氮離子如此可增加閘氧化層120、1 50a的整體介電係 本紙張尺度適用中國國家標準(CNS)A4規格(21〇χ297公釐) 558796 五、發明説明（） ::。亦=少其等效氧化層厚度。所以閘氧化層I〗。、"〇、 他、咖的等效氧化層厚度皆不同。 (請先閲讀背面之注意事項再塡寫本頁) 氮化 :層的:效氧化層厚度二二、3:二 始二過之閘氧化層的漏電流皆較原 ㈣Γ應^上述發明之方法，舉例來說mA圖中 第⑺ίΓ减層UG、13G、14G與15G的厚度為50埃’ 圖中閘减層14〇a、150a的厚度為2〇埃的話，則 在弟Π)圖之閘氧化層12〇的等效氧化層厚度可降至 埃’而閘氧化層15〇a的等效氧化層可降至15埃。所以在 :1D圖中，基底丨°°上形成有4。埃、5。埃、2。埃與15 由上述實施例一可知，可在同一晶圓上至少形成四種 ¾ 具有不同等效氧化層厚度的問氧化層。又因為去㈣氧化 層的步驟被減少至最低，所以淺溝渠隔離與主動區接壤之 角落不會被過度損傷’因此可減少漏電流與強電場的問 題。另外氮離子植入於閉氧化層之中，可以降低閑氧化声 之漏電流。 9 實施例 請參照第 2D圖，其繪示依照本發明另一較佳 實 本紙張尺度適用中國國家標準(CNS)A4規格(21〇X297公澄） 558796 五、發明説明（） 施例之一種在晶圓上形成 .的製造流程剖面圖。 4效魏層厚度之閘介電層 (請先閱讀背面之注意事項再場寫本頁) =照第Μ圖’先植入氮離子加於基底細中， 200表層的氧化速率。植η 乳化Α中之基底 、本^ . 植入虱離子210於基底200中的方 法，較佳為使用遠距電漿或去輕合電漿。 二：第2B圖’接著以熱氧化法，氧化基底表層220， =成厚度n閘氧化層勝閘氧化層咖的厚度約 -6埃。接著在閘氧化層22〇之上，沈積一層 介電常數之金屬氧化厣入砥& /、 ^ 匕層230。金屬氧化層“ο的厚度約為 25埃’·而形成方法例如可為有機金屬化學氣相沈積法(metal ^rgamc chemical vapor dep〇siti〇n ; m〇cvd)或原子層化學 氣相沈積法（at〇mic 丨咖 chemical vapor depositi〇n ; ALCVD)。然後利用微影蝕刻製程將部分之金屬氧化層 與閘氧化層220去除掉，以暴露出部分的基底表面，姓刻 的方法例如可為乾蝕刻法。 經濟部智慧財產局員工消費合作社印製 至屬氧化層230的材質為金屬氧化物，但是必須要具 備咼熱穩定性，例如可耐受高溫至約攝氏1〇〇〇度持續約3〇 秒’以免在後續熱製程中會擴散至位於其下之基底2〇〇， 與基底200的矽反應產生金屬矽化物，造成漏電流的問題。 因此較佳之選擇例如可為铃也兔二西熱 不^ 適合。 請芩照第2C圖，先以組成含有g|也銨（NJJ4〇H)、 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 558796 經濟部智慧財產局員工消費合作社印製 A7 '發明說明（） 2化氫(h2〇2)及去離子水等的RCA溶液或取溶液將暴 路出之基底200表面的殘餘氧化層去除乾淨。而位於全屬 =匕層23〇下方之閘氧化層22()因為有金屬氧化層23〇的 ^隻’所以不會㈣刻溶液㈣刻。然後以熱氧化法氧化 =出之基底·表面’形成問氧化層24〇,其較佳厚度 、·…-U)埃。在此因為原先基底表層被氮化的部分 破去除了，所以此步驟所生長出之閘氧化層240的厚 度較厚。· J予 請參照第2D圖’再—次全面植入氮離子25〇於暴露 出之金屬氧化層230與閘氧化層24()巾，以減少金屬氧化 層230、閘氧化層22〇肖24〇之漏電流。植入氮離子… 於金屬氧化層230與閘氧化層謂中的方法，較佳為 遠距電1¾去搞合電漿。然後在氦氣或氮氣下進行回火製 程丄以增加金屬氧化層23〇、閘氧化層22〇與閘氧化層· 的岔度’改善不同層之問接人而&卩上 』日又间接口面的狀況。此回火製程較佳 為在攝氏約_度下進行約1分鐘。如此，可增進後續製 造位於其上電路元件與組合出之積體電路的表現。 由上述實施例二可知，利用具有高介電f數之閣介電 層來有效地減少閘介電層之等效氧化層厚度，並利用含氮 電聚處理以及回火等製程來增加介電層的完整性，以減; 漏電流的發生。如此，具有高介電常數之間介電層沈積在 記憶體區’且高介電常數之問介電層回火時會在邏輯電路 區成長一層約7 - 1 0埃的薄氧化層。 10 (請先閲讀背面之注意事項再填寫本頁)V. Description of the invention () Sections of various isotropic oxide layers formed on the wafer. Gate " Manufacturing Process of Electrical Layers Figures 2A-2D are cross-sectional views showing another method for forming multiple equivalent oxide layers on a wafer according to the present invention. ^ Fabrication of gate dielectric layer of chemical layer factory Description of flow-based marking 100, 200: substrate 110: shallow trench isolation 120, 120a, 130, 140, gate oxide layer 160: photoresistor 170, 210, 250: nitrogen Ion 230: Metal oxide layers 140a, 150, 150a, 220, 240 (Please read the notes on the back before filling out this page) 'Detailed description of an invention printed as described above by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs' It is known that by repeatedly performing the growth of the gate oxide layer and the wet etching to form gate oxide layers of different thicknesses in different regions on the substrate, the time consuming manufacturing process and the corner portion bordering the shallow trench isolation and the active area will cause leakage current problems. Therefore, the present invention provides a method for forming a gate dielectric layer of various equivalent oxide thicknesses on a wafer to solve a conventional problem. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). 5. Invention Explanation () For the first embodiment, please refer to FIGS. 1A to 1D, and the 绛 + sub-example-a kind of cross-sectional view of a manufacturing process for forming a variety of equivalent oxides on a wafer. Please refer to Figure 1A for the dielectric layer of the gate, and first form a shallow trench isolation in the shallow ditch, Λ no, shallow trench here: i: The formation method is known to those skilled in this art, here is not More details. Then, the free oxide layers 120, 130, 40, and 150. are formed on the substrate 100 * '' '1, n1CA ^. The formation method is preferably a thermal oxidation method. μ Referring to FIG. 1B, the thickness of the free oxygen # 豆 & There are at least two methods available for this step. Eighty two directly use the money engraving method to remove the gate oxide layers 140 and 150. Second son two: the etching agent may be, for example, about 1 weight percent concentration of hydrofluoric acid. The other is to first remove the gate oxide layers 14 and 15-A ^ A, and then perform the ^-: personal thermal oxidation method to form an interlayer oxide layer on the surface of the substrate, and the oxide layer 120 at the same time. The thickness of 13 ° will also increase slightly. "凊 Refer to Figure 1C, cover the gate oxides 30 and 14 with photoresist 160, and then implant nitrogen ions 170 in the gate oxidation gm and 1 ground. Nitrogen ions 170 are implanted in the gate oxidation | 12 〇 Compared with the method in 15〇a, ^ ^ ^ ^ it ^ t (remote plasma) ^ ^ ft (decoupled plasma) is performed at a temperature lower than wo. Celsius. Referring to the ID chart, the implanted nitrogen ion 17 After the step of 〇, remove the photoresist 160. Gate oxide layer 20 and 15a The surface layers 12a and 15⑽ contain nitrogen ions. This can increase the overall dielectric system of the gate oxide layer 120 and 150a. This paper applies to China National Standard (CNS) A4 specification (21 × 297 mm) 558796 V. Description of the invention () ::. Also = less equivalent oxide thickness. Therefore, the gate oxide layer I. "," The equivalent oxide layer thickness is different. (Please read the precautions on the back before writing this page) Nitriding: layer: effective oxide layer thickness 22, 3: the leakage current of the gate oxide layer is more than The original method should be the method of the above invention. For example, the thickness of the UG, 13G, 14G, and 15G layers in the mA diagram is 50 angstroms. If the thickness of 150a is 20 angstroms, the equivalent oxide thickness of the gate oxide layer 120 in the figure can be reduced to angstrom ', and the equivalent oxide layer of the gate oxide layer 15a can be reduced to 15 angstroms. Therefore, in the 1D diagram, 4. Angstroms, 5. Angstroms, 2. Angstroms, and 15 are formed on the substrate. According to the first embodiment, at least four types can be formed on the same wafer, which have different equivalents. The thickness of the oxide layer is related to the oxide layer. Because the step of removing the plutonium oxide layer is minimized, the corners of the shallow trench isolation and the active area will not be damaged excessively, so the problems of leakage current and strong electric field can be reduced. In addition, nitrogen Ions implanted in the closed oxide layer can reduce the leakage current of idle oxidation sound. 9 For an example, please refer to FIG. 2D, which shows another preferred embodiment of the paper according to the present invention. The paper size is applicable to Chinese National Standard (CNS) A4. Specifications (21 × 297 Gongcheng) 558796 V. Description of the invention () Example of a cross-sectional view of a manufacturing process formed on a wafer. 4 gate dielectric layer with a thickness of 4 layers (please read the precautions on the back first) Field write this page) = according to Figure M 'first implanted nitrogen ions to the base In the bottom layer, the oxidation rate of the surface layer of 200. The method of planting η emulsifying the substrate in the substrate A, and implanting the lice ions 210 into the substrate 200, preferably using a long-range plasma or a de-lighting plasma. Figure 2B 'Next, the thermal oxidation method is used to oxidize the base surface layer 220 to a thickness of about -6 angstroms. The gate dielectric layer is then deposited on top of the gate oxide layer 22 and a dielectric constant metal is deposited. Oxidation of plutonium & /, ^ Dagger layer 230. The thickness of the metal oxide layer "ο is about 25 angstroms", and the formation method may be, for example, an organometallic chemical vapor deposition method (metal ^ rgamc chemical vapor dep0siti〇n; m〇cvd) or an atomic layer chemical vapor deposition method. (Atomic chemical vapor depositon; ALCVD). Then, a part of the metal oxide layer and the gate oxide layer 220 are removed by a lithography etching process to expose part of the substrate surface. The method of engraving can be, for example, Dry etching method. The material printed by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs to belong to the oxide layer 230 is a metal oxide, but it must have thermal stability, for example, it can withstand high temperatures to about 1,000 degrees Celsius for about 30 seconds' so as not to spread to the underlying substrate 200 in the subsequent thermal process, and react with the silicon of the substrate 200 to generate a metal silicide, causing a problem of leakage current. Therefore, a better choice can be, for example, Suzuki Rabbit II West heat is not suitable. Please refer to Figure 2C, and the composition contains g | ammonium (NJJ4〇H). The size of this paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm). 558796 Intellectual property of the Ministry of Economic Affairs Printed by the Consumer Cooperative Cooperative A7 'Invention Note (2) RCA solution such as hydrogen hydride (h2O2) and deionized water, or take the solution to remove the residual oxide layer on the surface of the substrate 200 that has been blown out. The gate oxide layer 22 () below the dagger layer 23 is not engraved with the solution because of the metal oxide layer 23 ′. Then, the oxide layer 24 is formed by oxidizing the substrate by the thermal oxidation method. 〇, its preferred thickness,... -U) Angstrom. Here, because the original surface layer of the substrate was nitrided and removed, the thickness of the gate oxide layer 240 grown in this step is thicker. Fig. 2D 'implants nitrogen ions 25 ° into the exposed metal oxide layer 230 and gate oxide layer 24 () again in order to reduce the leakage current of metal oxide layer 230 and gate oxide layer 22 × 24. The method of implanting nitrogen ions in the metal oxide layer 230 and the gate oxide layer is preferably a long-distance electric 1¾ to mix the plasma. Then, a tempering process is performed under helium or nitrogen to increase the metal oxide layer 23 〇, the gate oxide layer 22〇 and the gate oxide's bifurcation 'improves the connection between different layers and & 卩 上 』The condition of the interface between day and day. This tempering process is preferably carried out for about 1 minute at about _ degrees Celsius. In this way, the subsequent manufacturing of circuit components located thereon and integrated integrated circuits can be improved. It can be seen from the second embodiment that the equivalent dielectric layer thickness of the gate dielectric layer is effectively reduced by using a dielectric layer with a high dielectric f-number, and processes such as nitrogen-containing electropolymerization and tempering are used to increase the thickness. The integrity of the dielectric layer is reduced to reduce the occurrence of leakage currents. In this way, a dielectric layer with a high dielectric constant is deposited in the memory region, and the dielectric layer is tempered when the dielectric layer is tempered. The area grows a thin oxide layer of about 7-10 angstroms. 10 (Please read the notes on the back before filling this page)
558796 A7 B7 五、發明説明（） —558796 A7 B7 V. Description of the invention () —
(請先閲讀背面之注意事項再場寫本頁W 雖然本發明已以較佳實施例揭露如上，然其並非用以 •限f本發明’任何熟習此技藝者’在不脫離本發明之精神 =乾圍内，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。(Please read the notes on the back before writing this page. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention to 'anyone skilled in the art' without departing from the spirit of the present invention Within the fence, various modifications and retouchings can be made. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.
經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐)Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is sized for China National Standard (CNS) A4 (210X 297 mm)