CN100355085C - 半导体元件及其制造方法 - Google Patents

半导体元件及其制造方法 Download PDF

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CN100355085C
CN100355085C CNB008050295A CN00805029A CN100355085C CN 100355085 C CN100355085 C CN 100355085C CN B008050295 A CNB008050295 A CN B008050295A CN 00805029 A CN00805029 A CN 00805029A CN 100355085 C CN100355085 C CN 100355085C
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layer
tungsten
tungsten oxide
semiconductor element
oxide layer
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CN1364317A (zh
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M·施雷姆斯
D·德雷谢尔
H·乌策
H·图斯
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Infineon Technologies AG
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Abstract

按本发明制备具有由氧化钨(WOX)制的至少一个层的，必要时具有由氧化钨(WOX)制的一个已结构化层的一种半导体元件。按本发明的半导体元件的特征在于，氧化钨层(WOX)的相对介电常数(εr)大于50。

Description

半导体元件及其制造方法
技术领域
本发明涉及一种半导体元件及其制造方法。本发明尤其涉及具有场效应晶体管栅极电介层的和/或具有存储单元中的所谓“存储节点电介层”的一种半导体元件。
背景技术
为了保持或提高国际竞争力，不断降低用于实现某种电子功能所要花费的费用和因此持续地提高生产率是必要的。近年来生产率提高的保证在此曾是和仍然是CMOS工艺技术或DRAM工艺技术。这两种工艺技术在此通过结构缩小的进展达到生产率提高。
MOS晶体管的结构缩小的进展随之带来的却是，为了有效地控制晶体管必须采用越来越薄的电介层作为栅极电介层。如果像当今一般通常的那样，采用二氧化硅作为栅极电介层，在0.1μm工艺技术中的栅极电介层的层厚则必须要少于1.5nm。以足够的精度，可再现地制备这样薄的二氧化硅层却是很困难的。仅0.1nm的偏差意味着在层厚中的数量级为10％的波动。除此之外，在这样薄的二氧化硅层上导致通过二氧化硅层的高泄漏电流，因为通过量子力学的隧道效应载流子可以克服由二氧化硅层所生成的势垒。
在大规模集成存储器模块的发展上，尽管进展着的微型化仍必须保持或甚至于还必须改善一个单个存储单元的单元电容。为了达到此目的，同样采用越来越薄的电介层，通常的氧化硅层或氧化物-氮化物-氧化物层(ONO)，以及折叠的电容器电极(沟槽单元Trench-Zelle，堆栈式单元)。在减少存储器电介层的厚度时，却也导致通过电介层的泄漏电流(隧道电流)的明显提高。
因此曾建议，通过具有较高相对介电常数(εr)的材料代替通常的二氧化硅层或氧化物-氮化物-氧化物层。用这样的材料可以采用大于5nm的比较厚的层作为栅极电介层或存储器电介层，这些层在电气上却相当于显著小于5nm的一个二氧化硅层。可以较容易地控制这种层的厚度，并且显著地减小通过层的隧道电流。
例如曾建议氧化钛或五氧化钽，或由氧化物/氧化钛或氧化物/五氧化钽组成的层堆作为栅极电介层的材料。例如钛酸钡锶(BST，(Ba，Sr)TiO3)，钛锆酸铅(PZT，Pb(Zr，Ti)O3)，或镧掺杂的钛锆酸铅或钽酸锶铋(SBT，SrBi2Ta2O9)作为栅极电介层的材料得到采用。
可惜这些材料对于它们的新用途却具有一系列的缺点。因此通常采用CVD工艺用于制造由氧化钛或五氧化钽制的栅极电介层。如此制备的层却具有归因于在CVD法上所采用的工艺气体的杂质。这些杂质导致在层中的电荷和所谓的“陷阱”，这些电荷和“陷阱”又负面地影响晶体管的功能。此外这些层或层堆通常不产生介电常数(εr)的足够的提高。
在采用为存储器电介层的新材料时已证明，它们属于化学上很难或不能刻蚀的材料，在这些材料上甚至在采用“反应”气体时，刻蚀量绝大部分或几乎仅仅基于刻蚀的物理份额上。由于刻蚀的微小的或缺少的化学组分，应被结构化层的刻蚀量处于如掩模或底层(刻蚀停止层)的刻蚀量那样的同一数量级上，即对刻蚀掩模或底层的刻蚀的选择性一般是小的(约在0.3和3.0之间)。这带来的后果是，通过具有倾斜侧壁的掩模的侵蚀和在掩模上的不可避免的刻面形成[Facettenbildung](斜面，锲形)，只能保证结构化时微小的尺寸精确度。因此这种刻面化在结构化时限制最小可达到的结构尺寸，以及在要结构化层上的型面侧壁的可达到的陡度。
此外，为了制备BST层，PZT层或SBT层，复杂而昂贵的淀积方法，以及像铂或钌那样的难处理的壁垒层是必要的。除此之外，由于受缺乏热稳定性所限制，不能采用BST层于所谓的“深沟槽”电容器。
发明内容
因此本发明的任务之一在于提供一种半导体元件及其制造的一种方法，此方法避免或显著地减少所述的问题。由以下技术方案的半导体元件以及方法解决此任务。
根据本发明的一种具有由氧化钨制成的至少一个层的半导体元件，其特征在于，氧化钨层的相对介电常数大于50，并且采用所述氧化钨层作为存储器电介层，栅极电介层，隧道电介层或STI衬垫电介层。
根据本发明的一种用于制造具有氧化钨层的半导体元件的方法，具有以下步骤：a)准备一个含钨层；b)在含氧的环境中热氧化含钨层；c)在550至1100℃之间的一个温度下使由氧化钨制的层经受热处理，这样生成由具有大于50的相对介电常数的氧化钨制成的层。
根据本发明的一种用于制造具有氧化钨层的半导体元件的方法，具有以下步骤：a)准备半导体元件的一个表面；b)将氟化钨和水在气体状态下引到表面上，使得生成由氧化钨制成的层；c)由氧化钨制成的层经受温度为550至1100℃的热处理。
根据本发明的一种用于制造结构化氧化钨层的方法，具有以下步骤：a)准备一个氧化钨层；b)置放掩模到氧化钨层上；c)在氧化环境中，在高于130℃的一个温度下，按照掩模干刻蚀氧化钨层，其中氧化环境具有至少一种卤素化合物。
从本说明书的从属权利要求和所附的图中得出本发明的其它有利的实施形式，构成和特征。
按本发明的半导体元件具有这种优点，用氧化钨层(WOx)，例如x＝2-3，能以比较简单的方式产生很大的相对介电常数(εr)。除此之外，按本发明的半导体元件具有这种优点，可以将迄今在半导体技术中所采用的设备同样地应用于氧化钨层(WOx)的生成。不必采用专门适配的和因此昂贵的设备。用于生成氧化钨层(WOx)所采用的钨很难扩散入硅中，以至于在按本发明的半导体元件上仅产生微小的污染风险。氧化钨层(WOx)的应用却是不局限于硅工艺技术的，而是在与例如GaAs的另外的半导体的相关技术中也可以采用这些层。
氧化钨层(WOx)被优先采用为存储器电介层，栅极电介层，隧道电介层或STI衬垫(Liner)电介层。
此外，当氧化钨层的相对介电常数(εr)大于100，尤其是大于150时是优先的。
按本发明的一个其它的实施形式，半导体元件具有由一个含钨层和一个氧化钨层(WOx)组成的至少一个层堆，必要时具有由一个含钨层和一个氧化钨层(WOx)组成的一个已结构化的层堆。
此外，当半导体元件具有由一个氧化钨层(WOx)和至少一个壁垒层组成的至少一个层堆，必要时具有由一个氧化钨层(WOx)和至少一个壁垒层组成的一个已结构化的层堆时是优先的。
富钨层是优先由钨，硅化钨，或氮化钨形成的。
此外，当壁垒层是由氧化硅，氮化硅，氧氮化物，氮化钨或氮化钛形成时是优先的。
优先采用由钨，硅化钨或氮化钨制的层作为含钨层。
此外，当用CVD法或PVD法制备含钨层时是优先的。
此外，当在500至1200℃的温度下热氧化含钨层时是优先的。
按本发明的一个其它的实施形式，在热氧化之后在550至1100℃，优先700至1100℃之间的一个温度下，使由氧化钨(WOx)制的层经受热处理。优先在惰性气氛中进行热处理。
在此，当在惰性气氛中进行热处理时是尤其是优先的。
虽然氧化钨层可以比例如铁电层或铂层显著地较容易结构化。尽管如此氧化钨层属于那些层，在通常的结构化方法上基本上只能通过物理的刻蚀组分刻蚀这些层，并且这些层与此相应地相对于另外的层只具有微小的选择性。因此本发明的一个其它的任务在于说明用于制备已结构化的氧化钨层的一种方法。
按本发明的方法具有这种优点，基本上可以化学地，甚至没有物理的刻蚀组分地干刻蚀氧化钨层。与此相应地按本发明的方法具有相对于例如像硅或氧化硅那样的另外的材料的高度选择性。
优先按本发明的其中一种方法生成氧化钨层。
此外，当掩模是一种多晶硅掩模时是优先的。
除此之外，当刻蚀温度在200℃和300℃之间，尤其是约为250℃时是优先的。并且尤其是当氧化气氛中的卤素化合物的份额在1和10％之间时是优先的。
附图说明
以下借助附图详述本发明。所示的：
图1至4为按本发明方法的一种实施形式的示意图，和
图5至6为按本发明方法的一种其它实施形式的示意图。
具体实施方式
图1展示具有硅衬底1的硅晶片的剖视图。硅晶片的在图1中所展示的状态例如相当于，在已经生成了CMOS晶体管的阱和各个晶体管的(未展示的)绝缘之后，硅晶片在标准CMOS工艺中所具有的状态。
现在将约1至5nm厚的二氧化硅层2置放到硅衬底1的表面上作为壁垒层。例如可以通过热氧化生成此氧化层2。如果在附加地含有NO分子或N2O分子的气氛中进行热氧化，则可以制备氮化的二氧化硅层2。二氧化硅层具有一种极低的陷阱密度，这对于还应生成的晶体管的功能有积极的作用。
如在引言中已经提及的那样，准确检控如此薄的氧化层的厚度是困难的。然而由于此氧化层仅是用于制备真正的栅极电介层的一个准备阶段，可以接受氧化层2层厚的起伏，而这一点对于还应生成的晶体管的功能没有起负面的作用。
随后将一个含钨层3淀积到氧化层2上。此含钨层3可以是一个纯的钨层，一个氮化钨层或一个硅化钨层。例如通过溅射工艺(PVD法)或通过CVD法生成含钨的层3。
如果应采用CVD法，可以采用的一系列方法：
CVD W(在硅上，非选择地)
例如WF6+SiH4  →W+气体(晶核层)
例如WF6+H2    →W+气体(体层Bulkschicht)
CVD W(在硅上，对于氮化物，氧化物选择地)：
例如2 WF6 3 Si→2 W+3(SiF4)
(由R.V.Joshi及其他人，在J.Appl.Phys.71(3)1992年2月1日，pp.1428中说明了一种这样的方法。)
例如WF6+H2→W+气体
CVD WSix：
例如WF6+SiH2Cl2→WSix(例如x＝2-3)+气体
(同样R.V.Joshi及其他人，在J.Appl.Phys.71(3)1992年2月1日，pp.1428中说明。)
CVD WN(氮化钨，例如W2N)：
例如4WF6+N2+12H2(等离子体CVD)→4W2N+24(HF)
(例如在350-400℃的温度下)
如此生成的含钨层3的层厚约为10至20nm。图2中展示了由此产生的情况。
随后通过热氧化将含钨层3转变成氧化钨层3′。在氧气氛中(例如O2或H2O)在500至1200℃的一个温度下进行转变。在采用纯钨层或采用硅化钨层时，温度不应超过约600℃，或应实施所谓的“低热积聚(budget)”RTO(“快速热氧化”)，以便防止硅扩散入含钨的层3中，和防止含钨层3的氧化。
含钨层3的热氧化导致一种氧化钨层3′，此氧化钨层3′几乎不具有杂质，并且此氧化钨层3′具有大于50的相对介电常数(εr)。在此可以如比选择层和工艺参数，使得含钨层3完全转变成氧化钨层3′，或使得含钨层3的一个部分不被氧化。
通过在惰性气氛中约550至1100℃的一个温度下的随后的热处理，可以生成一种结晶相或烧结相(例如具有钭方晶或正方晶对称的相)的氧化钨层3′(WOx，例如x＝2-3)。直接紧接着氧化钨层3′的生成已经可以进行这种热处理。但是也可以在集成电路制造中的稍后的工艺步骤中才进行这种热处理。
图3中所展示的层堆很好地适用于MOS晶体管中的用途，因为如已提及的那样，二氧化硅层2(壁垒层)具有极低的陷阱密度。对于存储器电介层这一点不是绝对必要的，以至于对于这种用途也可以舍弃二氧化硅层2。富钨层3(例如氮化钨)的、在热氧化之后有时还剩余的部分，则承担(导电的)壁垒层的功能。以此方式用简单而费用有利的工艺控制是可以实现很大的电容的。图7中展示了在硅衬底1上由一个导电的氮化钨层2(壁垒层和下电极)、氧化钨层3′和一个导电的氮化钨层4(上电极)组成的相应的层堆。
随后在氧化钨层3′上生成导电的层4。图3中展示了由此产生的情况。按所采用的工艺不同，在导电层4之前却还可以淀积一个其它的壁垒层，例如(未展示的)氮化钨层。导电层4例如形成MOS晶体管的栅电极，并且通常由掺杂的多晶硅组成。
随后是光刻技术，此时结构化多晶硅层4，使得生成栅极导线5。栅极导线5又形成用于随后刻蚀氧化钨层3′的掩模。采用由CF4和O2组成的混合物作为刻蚀气体。刻蚀的温度约为250℃。在此通过高频输入或微波激励来激励刻蚀气体用于形成等离子体。CF4对O2的比例约为2％比98％。
释放出的氟和与此相连接的氧化钨与氟的反应是对于刻蚀本身负责的。在此形成挥发性的钨氟化合物。氧承担作为(多晶)硅的钝化剂的任务。通过氧形成SiO2，SiO2的结合能(没有采用附加的离子能)对于为了通过微量的氟份额来显著地刻蚀是太高的。因此氧化钨层的刻蚀对于(多晶)硅或对于氧化硅选择性很强。图4中展示了由此产生的情况。
然后可以按标准CMOS法继续进行制造晶体管的工艺，以便生成完整的晶体管。这些工艺本身是已知的，对其不必进一步详述。
图5展示具有硅衬底1的硅晶片的剖视图。硅晶片的、在图5中所展示的状态又相当于，硅晶片在标准CMOS工艺中在已经生成了CMOS晶体管的阱和各个晶体管的(未展示的)绝缘之后所具有的那种状态。
随后直接将氧化钨层3′置放到硅衬底1上。通过CVD法生成此氧化钨层3′。为此将气体状态下的氟化钨和水作为先导物引导到衬底表面上：
2WF6+4 H2O→(WOF4)+WO3+(HF)或
WF6+H2O+Si→W-O+(2HF)+(SiF4)
这导致约2至20nm厚的氧化钨层3′的析出。
通过在惰性气氛中约550至1100℃的一个温度下的随后的热处理，可以生成结晶相或烧结相(例如具有斜方晶或正方晶对称的相)的氧化钨层3′(WOx，例如x＝2-3)。直接紧接着氧化钨层3′的生成已经可以进行这种热处理。但是也可以在集成电路制造中的稍后的工艺步骤中才进行这种热处理。图5中展示了由此产生的情况。
随后在氧化钨层3′上生成导电层。按所采用的工艺不同在导电层之前却还可以析出一个其它的壁垒层，例如(未展示的)氮化钨层。然后又可以像已经在与图4的关联中所说明的那样，结构化导电层和氧化钨层3′。图6中展示了由此产生的情况。

Claims (21)

1.一种具有由氧化钨(3′)制成的至少一个层的半导体元件，其特征在于，氧化钨层(3′)的相对介电常数(εr)大于50，并且采用所述氧化钨层(3′)作为存储器电介层，栅极电介层，隧道电介层或STI衬垫电介层。
2.按照权利要求1的半导体元件，其特征在于，所述氧化钨层(3′)的相对介电常数(εr)大于100。
3.按照权利要求2的半导体元件，其特征在于，所述氧化钨层(3′)的相对介电常数(εr)大于150。
4.按照权利要求1的半导体元件，其特征在于，所述半导体元件具有由一个含钨层(3)和一个氧化钨层(3′)组成的至少一个层堆。
5.按照权利要求1的半导体元件，其特征在于，所述半导体元件具有由一个氧化钨层(3′)和至少一个势垒层(2)组成的至少一个层堆。
6.按照权利要求4的半导体元件，其特征在于，所述含钨层(3)由钨，硅化钨，或氮化钨形成。
7.按照权利要求5或6的半导体元件，其特征在于，所述势垒层(2)由氧化硅，氮化硅，氧氮化物，氮化钨或氮化钛形成。
8.一种用于制造具有氧化钨层的半导体元件的方法，具有以下步骤：
a)准备一个含钨层；
b)在含氧的环境中热氧化含钨层；
c)在550至1100℃之间的一个温度下使由氧化钨制的层经受热处理，这样生成由具有大于50的相对介电常数(εr)的氧化钨(WOX)制成的层。
9.按照权利要求8的方法，其特征在于，采用由钨，硅化钨，或氮化钨制的层作为所述含钨层。
10.按照权利要求8或9的方法，其特征在于，用CVD法或PVD法准备所述含钨层。
11.按照权利要求8的方法，其特征在于，在500至1200℃的温度下热氧化所述含钨层。
12.按权利要求8的方法，其特征在于，在惰性环境中进行热处理。
13.一种用于制造具有氧化钨层的半导体元件的方法，具有以下步骤：
a)准备半导体元件的一个表面；
b)将氟化钨和水在气体状态下引到表面上，使得生成由氧化钨(WOX)制成的层；
c)由氧化钨(WOx)制成的层经受温度为550至1100℃的热处理。
14.按照权利要求13的方法，其特征在于，在700至1100℃之间的一个温度中进行热处理。
15.按照权利要求13或14的方法，其特征在于，在惰性环境中进行热处理。
16.一种用于制造结构化氧化钨层的方法，具有以下步骤：
a)准备一个氧化钨层；
b)置放掩模到氧化钨层上；
c)在氧化环境中，在高于130℃的一个温度下，按照掩模干刻蚀氧化钨层，其中氧化环境具有至少一种卤素化合物。
17.按照权利要求16的方法，其特征在于，所述卤素化合物是CF4。
18.按照权利要求16的方法，其特征在于，
按照具有下述步骤的方法制造所述氧化钨层；
a1)准备一个含钨层，
a2)在含氧的环境中对所述含钨层进行热氧化，
a3)在550至1100℃之间的温度中将由氧化钨制成的层经受热处理，这样生成由具有大于50的相对介电常数(εr)的氧化钨(WOx)制的层。
19.按照权利要求16或17的方法，其特征在于，掩模是一种多晶硅掩模。
20.按照权利要求16的方法，其特征在于，刻蚀温度在200℃和300℃之间。
21.按照权利要求16的方法，其特征在于，氧化环境中的卤素化合物的份额在1和10％之间。
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