TWI803905B - 用於鐵電記憶體之無碳的疊層氧化鉿/氧化鋯膜 - Google Patents

用於鐵電記憶體之無碳的疊層氧化鉿/氧化鋯膜 Download PDF

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TWI803905B
TWI803905B TW110126237A TW110126237A TWI803905B TW I803905 B TWI803905 B TW I803905B TW 110126237 A TW110126237 A TW 110126237A TW 110126237 A TW110126237 A TW 110126237A TW I803905 B TWI803905 B TW I803905B
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hafnium oxide
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鄭君飛
湯瑪士 Ｈ 邦姆
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美商恩特葛瑞斯股份有限公司
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Abstract

提供無碳的(即，小於約0.1原子百分比之碳) Zr摻雜HfO 2膜，其中在原子百分比方面，Zr可達到與Hf相同之含量(即，1%至60%)。該Zr摻雜亦可藉由可用於鐵電記憶體(FeRAM)中之奈米疊層ZrO 2及HfO 2膜達成。該等疊層膜包含約5至10層之HfO 2及ZrO 2(即，交替)膜，其每一者可為例如約1至約2 nm之厚度，其中該等疊層膜之厚度總計為約5至10 nm。

Description

用於鐵電記憶體之無碳的疊層氧化鉿/氧化鋯膜
本發明屬微電子學領域。具體而言，其係關於包含二氧化鉿、二氧化鋯膜、二氧化鉿及二氧化鋯之混合組合物及電極之鐵電記憶體材料及結構之改良。
某些電子裝置具有在記憶體結構或單元中儲存及檢索資訊之能力。該等記憶體單元經組態以逐位元儲存資訊。舉例而言，記憶體單元可具有代表邏輯1及邏輯0之至少兩種狀態。如此儲存之資訊可藉由確定記憶體單元之狀態來讀取。該等單元可與一或多個邏輯電路一起整合於晶圓或晶片上。
一種類型之揮發性記憶體係允許高速及高容量資料儲存之DRAM結構。非揮發性記憶體結構之實例包括ROM、快閃結構、鐵電結構(例如，FeRAM及FeFET裝置)及MRAM結構。
在鐵電結構之情形中，該等可採用電容器(例如FeRAM)或電晶體(FeFET)之形式，其中資訊可儲存為結構內鐵電材料之某種極化狀態。鐵電材料及結構之一個實例利用過渡金屬氧化物，例如二氧化鉿與二氧化鋯之混合物。
包含氧化鉿及氧化鋯之介電膜通常使用原子層沉積及/或化學氣相沉積技術使用有機金屬鉿及鋯二烷基醯胺前體製備。參見例如「Atomic Layer Deposition of Hafnium and Zirconium Oxides using Metal Amide Precursors」, Dennis M. Hausmann等人， Chem. Mater. 2002, 14, 4350-4358。不幸地，該方法導致介電膜具有低含量之碳污染，此導致氧化鉿/氧化鋯介電膜中之洩漏及電荷阱缺陷。該等膜亦可在裝置製造之後續製程步驟期間產生碳，由此改變膜之性質。因此，業內需要製作該等介電膜之方法，該等介電膜不具有該等含量之碳且因此不具有其伴隨缺點。
概言之，本發明提供無碳的(即，小於約0.1原子百分比之碳) Zr摻雜HfO 2膜，其中在原子百分比方面，Zr可達到與Hf相同之含量(即，約1%至約60%，經由前體之共同引入，或約45%至約55%或約50%)。Zr摻雜亦可藉由可用於鐵電記憶體(FeRAM)中之奈米疊層ZrO 2及HfO 2膜(與Hf相比，1%至60% Zr)有效達成。疊層膜包含約5至10層之HfO 2及ZrO 2(即，交替)膜，其每一者可為例如約1至約2 nm之厚度，其中疊層膜之厚度總計為約5至20 nm。本發明之疊層膜預期展現用於基於MIM (金屬-絕緣體-金屬)及MIS (金屬-絕緣體-矽(或其他通道))結構之鐵電記憶體應用之優良鐵電及電性質。該等非揮發性記憶體通常提供高密度、低功率、快速切換、低成本及高耐久性。
本發明之疊層膜可使用ALD型熱沉積技術利用HfCl 4(或HfBr 4或HfI 4)及ZrCl 4(或ZrBr 4或ZrI 4)及氧化氣體(例如臭氧、氧、水、N 2O或電漿O 2)作為共反應物以分別沉積HfO 2及ZrO 2之高品質、無碳的膜來製備。
本發明亦提供用於使用HfCl 4、HfBr 4、HfI 4、ZrCl 4、ZrBr 4及ZrI 4以沉積具有小於約0.1原子百分比碳之氧化鉿及氧化鋯膜之方法。另外，該等膜亦可含有小於約0.1原子百分比之相應鹵素，例如氯、溴或碘。
在金屬-絕緣體-金屬(M-I-M)記憶體裝置實施例中，本發明之疊層氧化鉿/氧化鋯膜具有作為電極之頂部及底部層，該等層包含氮化鈦、釕、鉬、銥、鈷、鎢、鉑或銥及釕之導電氧化物中之至少一者。作為電極之頂部及底部層可為或不為相同材料。在金屬-絕緣體-半導體(M-I-S)記憶體裝置實施例中，疊層氧化鉿/氧化鋯膜可直接沉積於半導體及作為電極之頂部層上，該頂部層包含氮化鈦、釕、鉬、銥、鈷、鎢、鉑或銥及釕之導電氧化物中之至少一者。
在另一實施例中，本發明之疊層氧化鉿/氧化鋯膜進一步包含至少一個包含銥或氧化銥之外表面。在另一實施例中，本發明之疊層氧化鉿/氧化鋯膜進一步包含至少一個包含氮化鈦之外表面。
在一態樣中，本發明提供氧化鉿膜，基於該膜之總原子百分比，該膜具有摻雜於其中之約1至約60原子百分比之氧化鋯，其中該膜含有小於約0.1原子百分比之碳及小於約0.1原子百分比之鹵素。在其他實施例中，膜具有摻雜於其中之約45至55、或約50原子百分比之氧化鋯。
在第二態樣中，本發明提供包含氧化鉿及氧化鋯之交替膜之疊層膜，其中該疊層膜具有約5至約10 nm之厚度，且其中該疊層膜具有小於約0.1原子百分比之碳。
在一個實施例中，頂部及底部膜係氧化鉿。在另一實施例中，頂部及底部膜係氧化鋯。在另一實施例中，疊層膜進一步包含至少一種選自矽、鋁、釔及鑭之摻雜元素。
如上文在圖1中所說明，疊層膜(即，鐵電堆疊)可進一步在每一側上包含金屬層。在某些實施例中，該金屬層包含氮化鈦、釕、鉬、銥、鈷、鎢、鉑或者銥或釕之導電氧化物。
如上文在圖2中所說明，疊層膜可進一步在一側上包含金屬層或表面且在另一側上包含矽或含矽膜(例如Si 1-xGe x，其中x大於0但小於1且代表合金中每一元素之變化比例，為簡便起見在本文中稱為「SiGe」)。
在另一實施例中，本發明之疊層氧化鉿/氧化鋯膜進一步包含至少一個包含銥或氧化銥之外表面。
在另一實施例中，本發明之疊層氧化鉿/氧化鋯膜進一步包含至少一個外表面，該外表面包含氮化鈦、釕、鉬、銥、鈷、鎢、鉑或銥及釕之導電氧化物中之至少一者。在一個實施例中，至少一個外表面係氮化鈦。
在一個實施例中，本發明之疊層氧化鉿/氧化鋯膜具有包含銥及氧化銥中之至少一者之頂部層(即，膜)及/或氮化鈦、銥或氧化銥中之至少一者之底部層(即，膜)，在兩種情形中均在記憶體堆疊總成中作為電極。
具有小於約0.1原子百分比之碳之氧化鉿及氧化鋯膜可作為膜藉由利用氣相沉積(即，熱)製程沉積於基板(例如微電子裝置基板)上。
在某些實施例中，氣相沉積條件包含稱為化學氣相沉積、脈衝化學氣相沉積及原子層沉積之反應條件。在脈衝化學氣相沉積之情形中，在有或沒有中間(惰性氣體)吹掃步驟之情形中，可利用前體化合物與共反應物之一系列交替脈衝以使膜厚度積累至期望終點。
在某些實施例中，上文所描述應用前體化合物之脈衝時間(即，前體暴露於基板之持續時間)在介於約0.1與10秒之間之範圍內。在利用吹掃步驟時，持續時間為約1至4秒或1至2秒。在其他實施例中，共反應物之脈衝時間在1至60秒之範圍內。在其他實施例中，共反應物之脈衝時間在約1至約10秒之範圍內。
在一個實施例中，氣相沉積條件包含約250℃至約750℃之溫度及約1至約1000托(Torr)之壓力。在另一實施例中，氣相沉積條件包含約250℃至約650℃之溫度。
可採用四氯化鉿(或碘化鉿)及四氯化鋯(或碘化鋯)用於藉由任何適宜氣相沉積技術(例如CVD、數位(脈衝) CVD、ALD及脈衝電漿製程)形成含高純度二氧化鉿及二氧化鋯之膜。可利用該等氣相沉積製程以藉由利用約250℃至約550℃之沉積溫度形成厚度為約20埃至約2000埃之膜在微電子裝置上形成該等膜。
在本發明製程中，上述化合物可依任何適宜方式(例如在單晶圓CVD、ALD及/或PECVD或PEALD室中或在含有多個晶圓之爐中)與期望微電子裝置基板反應。
另一選擇，本發明之製程可作為ALD或類似ALD製程實施。如本文所用，術語「ALD或類似ALD」係指諸如以下之製程：(i) 將包括鉿或鋯前體化合物(I)及氧化氣體之每一反應物依序引入至反應器，例如單晶圓ALD反應器、半批式ALD反應器或批式爐ALD反應器，或(ii) 藉由移動或旋轉基板至反應器之不同區段將包括前體化合物及氧化氣體之每一反應物暴露於基板或微電子裝置表面且每一區段由惰性氣體簾隔開，即空間ALD反應器或卷對卷ALD反應器。
如上所述，氣相沉積製程進一步包含涉及將基板暴露於氧化氣體(例如O 2、O 3、N 2O、水蒸氣、醇或氧電漿)之步驟。在某些實施例中，氧化氣體進一步包含惰性載劑氣體，例如氬、氦、氮或其組合。
本文所揭示之沉積方法可涉及一或多種吹掃氣體。用於吹掃掉未消耗反應物及/或反應副產物之吹掃氣體係不與前體反應之惰性氣體。實例性吹掃氣體包括(但不限於)氬、氮、氦、氖、氫及其混合物。在某些實施例中，將吹掃氣體(例如氮或氬)以約10至約2000 sccm範圍內之流速供應至反應器達約0.1至1000秒，由此吹掃可留在反應器中之未反應材料及任何副產物。
將能量施加至前體化合物及氧化氣體中之至少一者以誘導反應並在微電子裝置基板上形成含二氧化鉿或二氧化鋯膜。該能量可由(但不限於)熱、脈衝熱、電漿、脈衝電漿、螺旋波電漿、高密度電漿、感應耦合電漿、X射線、電子束、光子、遠端電漿方法及其組合提供。在某些實施例中，可使用二次RF頻率源以改質基板表面處之電漿特徵。在其中沉積涉及電漿之實施例中，電漿生成製程可包含直接電漿生成製程，其中電漿直接在反應器中生成；或另一選擇遠端電漿生成製程，其中電漿係在反應區及基板之「遠端」生成，被供應至反應器中。
在一個實施例中，膜係使用原子層沉積技術利用例如ASM Pulsar® XP ALD反應器沉積。舉例而言，沉積製程可在以下條件下實施： HfCl 4(或ZrCl 4)安瓿溫度 = 170℃ H 2O安瓿溫度= 18-20℃ 壓力 = 2-3托 流速 = 400-600 sccm (100-200，藉助HfCl 4(或ZrCl 4)安瓿) 基板(即，室)溫度(T 基板) = 300℃ HfCl 4(或ZrCl 4)脈衝 = 0.5至1秒 H 2O脈衝 = 0.1至0.2秒
在原子層沉積方法之另一實例中，HfCl 4(或ZrCl 4)可在以下條件下沉積於300 mm裸矽晶圓上：
參數 HfCl 4 H 2O 室
溫度 185℃ 18℃ 300℃
壓力       約300托
流量(N 2) 20-100 sccm 50-100 sccm 1300 sccm
脈衝時間 0.1-1秒 0.5秒   
吹掃時間 3秒 3秒   
如上所述，在其他實施例中，利用此方法所形成之膜亦具有小於約0.1原子百分比之鹵素，例如碘、溴及氯。
因此，在另一態樣中，本發明提供使用HfCl 4、HfBr 4或HfI 4以在基板上沉積氧化鉿膜之方法，該膜具有小於約0.1原子百分比之碳，其包含在反應區中在氣相沉積條件下將基板交替暴露於(i) HfCl 4、HfBr 4或HfI 4及(ii) 氧化氣體。在一個實施例中，膜具有小於約0.1原子百分比之鹵素。
在另一態樣中，本發明提供使用ZrCl 4、ZrBr 4或ZrI 4以在基板上沉積氧化鋯膜之方法，該膜具有小於約0.1原子百分比之碳，其包含在反應區中在氣相沉積條件下將基板交替暴露於(i) ZrCl 4、ZrBr 4或ZrI 4及(ii) 氧化氣體。在另一實施例中，膜具有小於約0.1原子百分比之鹵素。
因為四氯化鉿(及四碘化鉿)及四氯化鋯(及四碘化鋯)在室溫下為固體，故可有利地利用諸如Entegris, Inc.出售之ProE-Vap® 100遞送系統之儲存及遞送裝置。亦參見美國專利第10,465,286號；第10,392,700號；第10,385,452號；第9,469,89號；及第9,004,462號，其以引用的方式併入本文中。因此，在氣相沉積製程中可利用包含諸如該等之雙重固體遞送系統之配置以藉由交替沉積二氧化鉿及二氧化鋯製備如上所述之疊層膜。
已特定參考本發明之某些實施例詳細闡述本發明，但應理解，可在本發明之精神及範圍內實現各種變化及修改。
圖1係經調適以形成用於記憶體應用(FeRAM)之M-I-M結構之本發明疊層結構之橫斷面繪示。 圖2係所採用以形成用於FeFET應用之M-I-S結構之本發明疊層結構之橫斷面繪示。 在本發明之疊層膜中，如圖1及圖2中所繪示，第一或「起始」膜可為氧化鉿或氧化鋯；同樣地，最終或「整理」膜可為氧化鉿或氧化鋯。在圖1及2中，氧化鉿繪示為起始膜且氧化鋯繪示為整理膜。 在圖1及2中，深黑色層指示金屬層，白色層指示氧化鉿層，灰色層(圖1中)代表氧化鋯層，且淺灰色(圖2中)層指示矽層或包含其他通道材料之層。

Claims (10)

  1. 一種氧化鉿膜，其基於該膜之總原子百分比具有摻雜於其中之約1至約60原子百分比之氧化鋯，其中該膜含有小於約0.1原子百分比之碳及小於約0.1原子百分比之鹵素，其中用以沉積氧化鉿之前體為HfCl4、HfBr4或HfI4，且用以沉積氧化鋯之前體為ZrCl4、ZrBr4或ZrI4。
  2. 如請求項1之膜，其中該膜具有摻雜於其中之約45至約55原子百分比之氧化鋯。
  3. 一種包含氧化鉿及氧化鋯之交替膜之疊層膜，其中該疊層膜具有約5至約10nm之厚度，且其中該疊層膜具有小於約0.1原子百分比之碳及小於約0.1原子百分比之鹵素，其中用以沉積氧化鉿之前體為HfCl4、HfBr4或HfI4，且用以沉積氧化鋯之前體為ZrCl4、ZrBr4或ZrI4。
  4. 如請求項3之疊層膜，其中頂部及底部膜係氧化鉿。
  5. 如請求項3之疊層膜，其中頂部及底部膜係氧化鋯。
  6. 如請求項3之疊層膜，其進一步包含至少一種選自矽、鋁、釔及鑭之摻雜元素。
  7. 如請求項3之疊層膜，其中該疊層膜進一步在每一側上包含金屬層。
  8. 如請求項3之疊層膜，其中該疊層膜進一步在一側上包含金屬層或表面且在另一側上包含矽或含矽膜。
  9. 一種使用HfCl4、HfBr4或HfI4以在基板上沉積氧化鉿膜之方法，該膜具有小於約0.1原子百分比之碳，該方法包含在反應區中在氣相沉積條件下將基板交替暴露於(i)HfCl4、HfBr4或HfI4及(ii)氧化氣體，其中該膜具有小於約0.1原子百分比之鹵素。
  10. 一種使用ZrCl4、ZrBr4或ZrI4以在基板上沉積氧化鋯膜之方法，該膜具有小於約0.1原子百分比之碳，該方法包含在反應區中在氣相沉積條件下將基板交替暴露於(i)ZrCl4、ZrBr4或ZrI4及(ii)氧化氣體，其中該膜具有小於約0.1原子百分比之鹵素。
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