TW434848B - Semiconductor chip device and the packaging method - Google Patents

Semiconductor chip device and the packaging method Download PDF

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Publication number
TW434848B
TW434848B TW089100578A TW89100578A TW434848B TW 434848 B TW434848 B TW 434848B TW 089100578 A TW089100578 A TW 089100578A TW 89100578 A TW89100578 A TW 89100578A TW 434848 B TW434848 B TW 434848B
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TW
Taiwan
Prior art keywords
pad
patent application
conductive
item
wafer
Prior art date
Application number
TW089100578A
Other languages
English (en)
Inventor
I-Ming Chen
Original Assignee
Chen I Ming
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chen I Ming filed Critical Chen I Ming
Priority to TW089100578A priority Critical patent/TW434848B/zh
Priority to US09/520,719 priority patent/US6239488B1/en
Priority to TW89100578A01 priority patent/TW466715B/zh
Priority to US09/564,989 priority patent/US6333561B1/en
Priority to DE2000127852 priority patent/DE10027852A1/de
Priority to JP2000217360A priority patent/JP3328643B2/ja
Priority to TW89100578A02 priority patent/TW495933B/zh
Priority to TW89100578A03 priority patent/TW466716B/zh
Priority to US09/725,431 priority patent/US6400016B2/en
Priority to TW89100578A04 priority patent/TW503534B/zh
Priority to JP2000400815A priority patent/JP3443567B2/ja
Priority to DE2001101948 priority patent/DE10101948B4/de
Priority to US09/765,793 priority patent/US6437448B1/en
Priority to US09/792,003 priority patent/US20020072148A1/en
Priority to DE2001110453 priority patent/DE10110453A1/de
Priority to DE2001117239 priority patent/DE10117239A1/de
Priority to US09/828,204 priority patent/US20010012644A1/en
Priority to JP2001110048A priority patent/JP2002141438A/ja
Priority to JP2001112806A priority patent/JP2002198464A/ja
Application granted granted Critical
Publication of TW434848B publication Critical patent/TW434848B/zh
Priority to US10/121,782 priority patent/US6602732B2/en

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43484¾ 五'發明說明（1) ------- / 裝置關於一種適於安裝i一基板之半導體晶片 _ θ ΰ 2 裝方法，該基板具有一晶片裝置安裝區域，於 該晶片裝置安缺^ 文瑕區域内係設有數個與該晶片裝置之銲 位置不對應的銲點。 吁蝥之 來越小，Lt 2程的發展，晶片之表面上的彈塾變得越 路電氣連接時離ί越益縮小’以致於在與外部電 響半導體製程i;:::易，進而影響生產良率，甚至影 ，並:本案發明人遂以其從事該行業之多年經驗 •-曰1#永精之精神，積極研究改良，遂有本發明『 千导體曰曰片裝置及其封裝方法』產生。 本發明之目沾Θ & # ω ^ Α 晶片裂置及其封種此解決上述問題的半導體 氺尨t !ΐ本發:月《一特穆支，一種半導體晶片I 4的封裝方 i β仏為半導體晶片裝置係適於安裝在一具有數個 銲點的基板上。該封裝方法包含如下之步驟：提供一半導 巧阳片’ e亥半導體晶片具有一銲墊安裝表面及數個設於該 知^安裝表面的銲墊，該等銲墊的位置係不對應於該基板 之銲點的位置，把一鋼板置於該晶片的銲墊安裝表面上， 該鋼板形成有數個用於暴露該晶片之對應之銲墊之一部份 及該晶片之銲墊安裝表面之預定部份的貫孔，在形成該鋼 板之各貫孔的孔壁與該晶片之銲墊安裝表面之間係形成一 導電體形成空間；及以導電金屬膠為材料利用印刷手段於 各導電體形成空間形成一導電體，各導電體具有一從該晶
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^之對應之銲墊延伸出來作為電路執跡的延伸部及办‘ 五、發明說明（2) 由r其之位置係與該基板之對應 直對應的電氣連接部。 根據本發明之另一特徵，一種半導體晶片裝 法係被提供。該半導體晶片裝置係適於安裝且右2 =銲點的基板上，裝方法包含如下之步驟：提 體晶片，該半導體晶片具有一銲墊安裝表面及數個、設於 忒銲墊安裝表面的銲墊，該等銲墊的位置係不對應於該其 板之銲點的位置；於該晶片的銲墊安裝表面上形成二層"$ 經化學沖洗的薄膜材料；把一光罩置於該薄膜材料上，該 光罩形成有數個貫孔；以化學沖洗手段於該薄膜材料上ς ^用於暴露該晶片之對應之銲墊之一部份及該晶片之銲墊 女裝表面之預定部份的導電體形成槽孔；及以導電金屬勝 為材料利用印刷手段於各導電體形成槽孔内形成—導電^ ’各導電體具有一從該晶片之對應之銲墊延伸出來作為電 路轨跡的延伸部及一位於該延伸部之自由端且其之位置係 與該基板之對應之銲點之位置對應的電氣連接部。 、 根據本發明的又另一特徵，一種半導體晶片裝置係被 提供。該半導體晶片裝置係適於安裝在一具有數個銲點的 基板上並且包含：一半導體晶片，該半導體晶片具有一銲 墊文裝表面及數個設於該銲勢安裝表面的鋅整，該等鮮塾 的位置係不對應於該基板之銲點的位置；及數個導電體， 各導電體具有一從該晶片之對應之銲墊延伸出來作為電路 軌跡的延伸部及一位於該延伸部之自由端並且係與該系統
第5頁 點對應的電 之又再一特 晶片裝置係 :一半導體 個設於該銲 於該基板之 形成於該晶 晶片之對應 定部份的導 形成於對應 片之對應之 該延伸部之 位置對應的 為達上述目 較佳實施例 係描螬本發 程的示意流 發明之形成 係描續'本發 圖；及 描繪本發明 瑕*連接部。 ’ ，，一種半導體曰曰曰片裝置.係被 一具有數個銲點的 導體晶片具有 的銲塑· ;一層 裝表面 部份及 孔；及 成槽孔 來作為 之位置 〇 採用的 說明如 片裴置 434i4^ 五、發明說明（3) 基板之對應之銲 根據本發明 提供。該半導體 基板上並且包含 墊安裝表面及數 的位置係不對應 該層薄膜材料係 成有用於暴露該 墊安裝表面之預 ，該等導電體係 體具有一從該晶 延伸部及一位於 之對應之銲點之 有關本發明 其功效，茲例舉 第一至七圖 實施例之封裝過 第八圖係本 第九和十圖 合之例子的示意 第十一圖係 通於安裝在 晶片，該半 &安裝表面 鮮點的位置 片的銲墊安 之銲墊之— 電體形成槽 的導電體形 銲墊延伸出 自由端且其 電氣連接部 的、特徵所 並配合圖式 明半導體晶 程圊； 保護層之遮板的示 明第一較佳實施例 銲 ，該等辑墊 薄膜材料， 上並且係形 s玄晶片之鮮 數個導電體 内，各導電 電路執跡的 係與該基板 技術手段及 下： 之第一較佳 意平面圖； 與一基板結 第二較佳實施例的示意剖視圖 =十二圖係描繪本發明第三較佳實施例的示意平面圖 ’其中’保護層係被移去；
五、發明說明（4) 第十三圖係描繪本發明第四較佳實施例的示意平面圖 ，其中，保護層係被移去； 第十四至十九圖係本發明第五較佳實施例之封裝過程 的示意流程圖。 元件標號對照表 1 半導體晶片 10 鐸塾安裝表面 11 銲墊 2 鋼板 20 貫孔 3 導電體 300 延伸部 3 0 1電氣連接部 91 導電銀膠 5 黏膠層 9 基板 90 銲點 91， 錫膏 6 導電金屬球 7 乾薄膜 70 導電體形成槽孔 8 光罩 80 貫孔 4 遮板 40 開孔 41 保護層 在本發明被詳細描述之前 3 應要注意的是在整個說明 當中，相同的元件係由相同的標號標示。 本發明之半導體晶片裝置係適於安裝至一基板9 (見 第九圖）上。該基板9 具有一晶片安裝區域。於該晶片安 裝區域内係設有數個銲點9 0。在本實施例中，該基板9 是 為一系統基板。 第一至七圖顯示本發明半導體晶片裝置之封裝方法的 第一較佳實施例。在第一圖中，一半導體晶片1係被顯示
^34g 4飞 i 五、發明說明（5) 具有一用於安裝銲墊11的銲墊安裝表面丨〇。該等銲墊u的/ 位置係不對應於該基板9之銲點9 〇的位置。 ! 然後’如第一至四圖所顯示般’ 一鋼板2係被置放於 該晶片1的安裝表面1 〇上。在本實施例中，該鋼板2是為 印刷網板。該鋼板2係形成有數個用於暴露對應之銲墊玉j 之一部份及該銲墊安裝表面1〇之預定部份的貫孔2〇。在形 成該鋼板2之各貫孔20的孔壁與該晶片1的銲墊安裝表面 1 0之間.係形成一導電體形成空間。 之後’如苐五和六圖所顯示般’係以導電金屬夥為材 料，利用印刷手段於該等導電體形成空間形成導電體3 。 在該鋼板2被移去後，經過加熱烤乾處理使該等導電體3 成為帶硬性的導電體3 。在本實施例中，該導電金屬膠是 為摻雜有銀的導電銀膠。然而，應要了解的是，該導電金 屬耀·也可以是為摻雜有如金、銅、鐵、銘、锡與錯等導電 金屬的導電金屬膠。各導電體3係由一從對應之^塾"延 伸出來作為電路軌跡的延伸部3 〇 〇和一位於該延伸部3 〇 〇 之自由端且其之位置係與該基板9之對應之銲點9 〇之位置 對應之作為導電觸點的電氣連接部3 〇 1 。 應要注忌的疋’該印刷手段可以是為絹網印刷手段、 移刷膠頭手段或鋼板印刷手段。 6月參閱第七和八圖所不，之後，一遮板4係置於該晶 片1的安裝表面1〇上。該遮板4形成有一用於昊霞访曰g 1、之物i與該晶Μ之安裝表面1〇之—部份；二片 以致於在形成該開孔40的孔壁與該安裝表面1 〇的一部份之
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五.、發明說明（6) 間形成-保護層形成空間。接著’如環氧樹脂 料係灌注入該保護層形成空間以形成—用於勝為材 之銲塾11與該晶之安裝表面10之一部份；保匕片1 在保護層41形成之後，該遮板4係被移去。 ° 請參閱第九圖所示’當本發明之半導體晶片袭置如 所述製成時，其係適於安裝至一基板9上。該等電氣連接 = 301係透過在該基板9之銲點9〇上之預先設置的導電銀 膠91來與該基板9之對應的銲點9〇電氣連接。應要注意的 $ ’在該基板9與該晶片1之間係可設有一用於在導電銀 夥9 1被加熱硬化之前防止該基板9與該晶片1之間之相對 移動的黏膠層5 。 凊參閱第十圖所示，該基板9之鮮點9 〇和該晶片之對 應之導電體3之電氣連接部3〇1之間的電氣連接亦可以透 過錫膏91達成。當錫膏91’被使用時，黏膠層係可被免 除。 應要注意的是，藉著控制鋼板之貫孔的尺寸，該等導 ，體之電氣連接部的高度係可受控制。請參閱第Η--圖所
示，其是為類似於第七圖之顯示本發明半導體晶片裝置之 第二較佳實施例的示意剖視圖。在本實施例中，該等導電 體之電氣連接部3 〇 1的高度係比第七圖所示之第一實施例 之導電體之電氣連接部的高度低。因此，在形成該等導電 體3之後’於每一導電體3的電氣連接部301上係設置有 導電金屬球6 。在本實施例中，該等導電金屬球6疋為 锡球。
五、發明說明（7) 請參閱第 以在該晶片1 請參閱第 以在該晶片1 第十四至 佳實施例的封 請參閱第 片1的銲墊安 光罩8 (見第 和十七圖所顯 薄膜7係形成 —部份及該晶 形成槽孔70， 圖，係以如導 成導電體3及 片1 之銲墊11 41。 當然，在 形成如第Η—
十二圖所示 之銲塾安裝 十三圖所示 之輝墊安裝 十九圖顯示 裝過程。 十四圖所示 装·表面1 〇上 十五圖）係 示般。接著 有數個用於 片1 之銲塾 如第十八圖 電銀膠般的 以如環氧樹 和該晶片I ’該晶片1之銲墊11的位置係可 表面1 0的兩侧。 ，該晶片1之銲墊1 1的位置亦可 表面10的四周。 本發明半導體晶片裝置之第五較 感光乾薄 。然後 覆蓋於 ，經過 暴露該 安裝表 所顯示 材料於 月旨般的 之安裝 ，一形 該乾薄 化學沖 晶片1 面1 0之 般。其 各導電 材料形 表面1 0 膜7係形 成有數個 臈7上， 洗處理， 之對應之 預定部份 後，請參 體形成槽 成一用於 之—部份 成於該晶 貫孔8 0的 如第十六 該感光乾 銲墊11之 的導電體 閱第十九 孔70内形 覆蓋該晶 的保護層 可。 綜上所述 』，確能藉上 功效，且申請 之新穎、進步 本實施例中，導電 圖所顯示般，之後 ’本發明之『半導 述所揭露之構造、 前未見於刊物亦未 等要件。 體3之電氣連接部亦可以 於其上設置導電金屬球即 體晶片裝置及其封裝方法 裝置’達到預期之目的與 公開使用，符合發明專利
第10頁 4 3484¾ 五、發明說明（8) /;惟，上述所揭之圖式及說明，僅為本發明之實施例而 已Λ，非為限定本發明之實施例；大凡熟悉該項技藝之人仕 ，其所依本發明之特徵範疇，所作之其他等效變化或修飾 ，皆應涵蓋在以下本案之申請專利範圍内。
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Claims (1)

  1. 43414¾ 六、申請專利範圍 1..一種半導體 適於安裝在 之步驟： 提供一 表面及數個 置係不對應 把一鋼 成有數個用 片之銲墊安 各貫孔的孔 電體形成空 以導電 空間形成一 銲塾延伸出 之自由端且 應的電氣連 2. 如申請專利 的步驟之後 於各導 3. 如申請專利 導電金屬球 4. 如申請專利 導電體的步 銅、鐵、錫 半導體晶 設於該銲 於該基板 板置於該 於暴露該 裝表面之 壁與該晶 間；及 金屬膠為 導電體， 來作為電 其之位置 接部。 範圍第1 ,更包含 電體之電 範圍第2 的步戰中 範圍第1 驟中，該 和錯等導 墊安裝 之銲點 晶片的 晶片之 預定部 片之銲 材料利 各導電 路轨跡 係與該 項所述 如下之 氣連接 項所述 ，該等 項所述 導電金 電金屬 半導體晶片具有—銲墊安裝 表面的銲塾，該等銲墊的位 的位置； 銲塾安裝表面上，該鋼板形 對應之銲墊之一部份及該晶 份的貫孔’在形成該鋼板之 塾女裝表面之間係形成一導 用印刷手段於各導電體形成 體具有一從該晶片之對應之 的延伸部及一位於該延伸部 基板之對應之銲點之位置對 之封裝方法，在形成導電體 步驟： 部設置一導電金屬球。 之封裝方法，其中’在形成 導電金屬球是為錫球。 之封裝方法，其中，在形成 屬膠是為摻雜有金、銀、 材料中之一種的導電金屬
    第12頁 a 六 5. 6. Ί, 、申請專利範圍 ! ' 膠。 ^ 如申請專利範圍第1 導電體的步驟之後， 以膠質材料形成 之安裝表面之一部份 如申請專利範圍第5 保護層的步驟中，該 »-·種半導體晶片裝置 適於安裝在一具有數 之步驟. 提供一半導體晶 表面及數個設於該銲 置係不對應於該基板 於該晶片的銲墊 的薄臈材料； 把一光罩置於該 ； 以化學沖洗手段 片之對應之銲墊之一 定部份的導電體形成 以導電金屬膠為 槽孔内形成一導電體 之銲墊延伸出來作為 部之自由端且其之位 項所述之封震方法， 、 *句含如在·形成 更包3如下之步驟： 一用於覆蓋辞曰y 的保護層 曰片之辉墊和該晶片 法，其中，在形成 夕負材枓為環乳樹脂。 的封裝方法，該半導體晶片裝置俜 個銲點的基板上1方法包 片玄半導體晶片具有一銲墊安裝 墊安裝表面的銲墊，該等銲墊的位 之銲點的位置； 女裝表面上形成一層可經化學沖洗 薄膜材料上，該光罩形成有數個貫 於該薄膜材料上形成用於暴露該晶 部份及該晶片之銲墊安裝表面之預 槽孔；及 材料利用印刷手段於各導電體形成 ’各導電體具有一從該晶片之對應 電路轨跡的延伸部及一位於該延伸 置係與該基板之對應之銲點之位置 Η
    六、申請專利範圍 對A的電氣連接部。 在·形成導電髏 8 *如申請專利範圍第7項所述之封裝方法 的步驟之後，吏包含如下之步驟： 於各導電體之電氣連接部設1—導電金屬 9.如申請專利範圍第8項所述之封裝方法，其中，。 > 成 導電金屬球的步驟中，該等導電金屬球是為錫球在形 1 〇 .如申請專利範圍第7項所述之封襞方法，其中\ 形 成導電體的步驟中，該導電金屬膠是為摻&有金、 銀、銅、鐵、錫和船等導電金屬材料中之—種的導電 金屬膠。 11 ·如申請專利範園第7項所述之封裝方法，其中，在衫 成該薄膜材料的步驟中，該薄膜材料是為感光乾薄 膜。 ' 1 2.如申請專利範圍第7項所述之封裝方法，其中，在形 成導電體的步驟之後，更包含如下之步驟： 以膠質材料形成一用於覆蓋該晶片之銲墊和該薄 膜材料之一部份的保護廣。 1 3.如申請專利範圍第丨2項戶斤述之封裝方法，其中，在形 成保護層的步驟中，該#質材料為環氧樹脂。 14. 一種半導體晶片裝置，其德適於安裝在一具有數個銲 點的基板上，該半導體晶片裝置包含： 一半導體晶片，該半導體晶片具有一銲墊安裝表 面及數個設於該銲墊安装表面的銲墊，該等銲墊的位 置係不對應於該基板之銲辨的位置；及
    434B4% 六、申請專利範is ' ' 7 ' ~ ~ 數個導電體，各¥電體具有一從該晶片之對應之 鲜塾延伸出來作為電路軌跡的延伸部及—位於該延伸 部之自由端且其之位置係與該基板之對應之銲點之位 置對應的電氣連接部β 15_如申請專利範圍第14項所述之裝置，吏包含數個導電 金屬球’該等導電金屬球係設置於對應之導電體的電 氣連接部上。 1 6.如申請專利範圍第1 5項所述之裝置’其中，該等導電 金屬球疋為錫球。 1 7.如申請專利範園第丨4項所述之裝置’其中，該等導電 體係由導電金屬膠形成。 18·如申請專利範圍第η項所述之裝置’其中，該導電金 屬膠是為摻雜有金、銀、銅、鐵、錫和鉛等導電金屬 材料中之一種的導電金屬膠。 19.如申請專利範圍第14項所述之裝置’更包含一用於覆 蓋該晶片之銲墊與該晶片之安裝表面之—部份的保護 層 〇 2 0.如申請專利範圍第1 9項所述之裂置’其中，該保護層 係由環氧樹脂形成》 21. —種半導體晶片裝置，其係適於安裝在—具有數個銲 點的基板上，該半導體晶片裝，包含： 一半導體晶片，該半導體晶片3具有—銲墊安裝表 面及數個設於該銲墊安装表面的知整’該等銲墊的位 置係不對應於該基板之銲•點的& £ ’
    434B 4¾ : 六、申請專利範圍 "7 一 一層薄“材料”該層 鮮墊安冑表面上並且係形 之銲墊之一部份及該晶月 的導電體形成槽孔；及 數個導電體，該等導 形成槽孔内’各導電體具 延伸出來作為電路軌跡的 自由端且其之位置係與該 應的電氣連接部。 2 2.如申請專利範圍第2丨項所 金屬球’該等導電金屬球 氣連接部上。 23.如申請專利範圍第22項所 金屬球是為錫球。 2 4.如申凊專利範圍第21項所 體係由導電金屬膠形成。 25. 如申請專利範圍第24項所 屬膠是為摻雜有金、銀、 材料中之一種的導電金屬 26. 如申請專利範圍第2 1項所 料是為感光乾薄膜。 27. 如申請專利範圍第21項所 羞該晶片之鲜塾和該薄膜 28·如申請專利範圍第27項所 薄 膜 材 料 係 形 成 於 該 晶 片 的 成 有 用 於 暴 露 該 晶 片 之 對 應 之 銲 墊 安 裝 表 面 之 預 定 部 份 電 體 係 形 成 於 對 應 的 導 電 體 有 —— 從 該 晶 片 之 對 應 之 銲 塾 延 伸 部 及 一 位 於 該 延 伸 部 之 基板 之 對 應 之 銲 點 之位 置 對 述 之 裝 置 > 更 包 含 數個 導 電 係 設 置 於 對 之 導 電 體 的 電 述 之 裝 置 J 其 中 3 該 等 導 電 述 之 裝 置 ΐ 其 中 » 該 等 導 電 述 之 裝 置 9 其 中 該 導 電 金 銅 、 鐵 、 錫 和 鉛 等 導 電 金 屬 膠 〇 述 之 裝 置 ) 其 中 該 薄 m 材 述 之 裝 置 更 包 含 一 用 於 覆 村 料 之 — 部 份 的 保 護 層 〇 述 之 裝 置 J 其 中 ί 該 保 護 層
    第16頁 六、申請專利範圍 係由環氧樹脂形成。 Ι_ΒΒ1Ι 第17頁 〇
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US09/520,719 US6239488B1 (en) 2000-01-14 2000-03-08 Method for mounting a semiconductor chip on a substrate, and semiconductor device adapted for mounting on a substrate
TW89100578A01 TW466715B (en) 2000-01-14 2000-03-15 Semiconductor chip device and its packaging method
US09/564,989 US6333561B1 (en) 2000-01-14 2000-05-05 Method for mounting a semiconductor chip on a substrate, and semiconductor device adapted for mounting on a substrate
DE2000127852 DE10027852A1 (de) 2000-01-14 2000-06-06 Verfahren zum Anordnen eines Halbleiterchips auf einem Substrat und zum Anordnen auf einem Substrat geeignetes Halbleiterbaelement
JP2000217360A JP3328643B2 (ja) 2000-01-14 2000-07-18 半導体チップを基板に実装する方法及び基板への実装に適した半導体デバイス
TW89100578A02 TW495933B (en) 2000-01-14 2000-09-29 Semiconductor chip device and encapsulation method thereof
TW89100578A03 TW466716B (en) 2000-01-14 2000-10-21 Semiconductor chip device and its packaging method
US09/725,431 US6400016B2 (en) 2000-01-14 2000-11-29 Method for mounting a semiconductor chip on a substrate and semiconductor device adapted for mounting on a substrate
TW89100578A04 TW503534B (en) 2000-01-14 2000-12-08 Semiconductor chip device and the packaging method thereof
JP2000400815A JP3443567B2 (ja) 2000-01-14 2000-12-28 基板に半導体チップを実装する方法および基板に実装するのに適した半導体デバイス
DE2001101948 DE10101948B4 (de) 2000-01-14 2001-01-17 Verfahren zum Anordnen eines Halbleiterchips auf einem Substrat und auf einem Substrat montierbarer Halbleiterbaustein
US09/765,793 US6437448B1 (en) 2000-01-14 2001-01-18 Semiconductor device adapted for mounting on a substrate
US09/792,003 US20020072148A1 (en) 2000-01-14 2001-02-23 Method for mounting a semiconductor chip on a substrate, and semiconductor device adapted for mounting on a substrate
DE2001110453 DE10110453A1 (de) 2000-01-14 2001-03-05 Verfahren zum Montieren eines Halbleiterchips auf einem Substrat und auf einem Substrat montierbarer Halbleiterbaustein
DE2001117239 DE10117239A1 (de) 2000-01-14 2001-04-06 Verfahren zum Anordnen eines Halbleiterchips auf einem Substrat, und zum Anordnen auf einem Substrat angepaßte Halbleitervorrichtung
US09/828,204 US20010012644A1 (en) 2000-01-14 2001-04-09 Method for mounting a semiconductor chip on a substrate, and semiconductor device adapted for mounting on a substrate
JP2001110048A JP2002141438A (ja) 2000-01-14 2001-04-09 半導体チップを基板に実装する方法および基板に実装するのに適した半導体装置
JP2001112806A JP2002198464A (ja) 2000-01-14 2001-04-11 半導体チップを基板上に実装する方法、および基板上に実装するのに適した半導体装置
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7215017B2 (en) 2003-05-02 2007-05-08 Yu-Nung Shen Wafer level package, wafer level packaging procedure for making wafer level package

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6707159B1 (en) * 1999-02-18 2004-03-16 Rohm Co., Ltd. Semiconductor chip and production process therefor
US6400016B2 (en) * 2000-01-14 2002-06-04 I-Ming Chen Method for mounting a semiconductor chip on a substrate and semiconductor device adapted for mounting on a substrate
US6437448B1 (en) * 2000-01-14 2002-08-20 I-Ming Chen Semiconductor device adapted for mounting on a substrate
TW434848B (en) * 2000-01-14 2001-05-16 Chen I Ming Semiconductor chip device and the packaging method
US7057292B1 (en) 2000-05-19 2006-06-06 Flipchip International, Llc Solder bar for high power flip chips
TW494548B (en) * 2000-08-25 2002-07-11 I-Ming Chen Semiconductor chip device and its package method
US20020170897A1 (en) * 2001-05-21 2002-11-21 Hall Frank L. Methods for preparing ball grid array substrates via use of a laser
JP2003100801A (ja) * 2001-09-25 2003-04-04 Mitsubishi Electric Corp 半導体装置
US7102217B2 (en) 2003-04-09 2006-09-05 Micron Technology, Inc. Interposer substrates with reinforced interconnect slots, and semiconductor die packages including same
US7565141B2 (en) * 2003-10-08 2009-07-21 Macaluso Anthony G Over the air provisioning of mobile device settings
JP4972280B2 (ja) * 2004-12-09 2012-07-11 ローム株式会社 半導体装置
US20060186535A1 (en) * 2005-02-23 2006-08-24 Visteon Global Technologies, Inc. Semi-conductor die mount assembly
US7927976B2 (en) * 2008-07-23 2011-04-19 Semprius, Inc. Reinforced composite stamp for dry transfer printing of semiconductor elements
US8506867B2 (en) * 2008-11-19 2013-08-13 Semprius, Inc. Printing semiconductor elements by shear-assisted elastomeric stamp transfer
TW201023314A (en) * 2008-12-02 2010-06-16 Aflash Technology Co Ltd Semiconductor chip packaging structure
US8261660B2 (en) * 2009-07-22 2012-09-11 Semprius, Inc. Vacuum coupled tool apparatus for dry transfer printing semiconductor elements
US8916969B2 (en) * 2011-07-29 2014-12-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, packaging methods and structures
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9583420B2 (en) 2015-01-23 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufactures
US9281297B2 (en) 2014-03-07 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Solution for reducing poor contact in info packages
US9293442B2 (en) 2014-03-07 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US9449947B2 (en) 2014-07-01 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package for thermal dissipation
JP5944979B1 (ja) 2014-12-26 2016-07-05 千住金属工業株式会社 はんだ転写シート、はんだバンプ及びはんだ転写シートを用いたはんだプリコート方法
DE102016109950B3 (de) 2016-05-30 2017-09-28 X-Fab Semiconductor Foundries Ag Integrierte Schaltung mit einem - durch einen Überführungsdruck aufgebrachten - Bauelement und Verfahren zur Herstellung der integrierten Schaltung

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08236586A (ja) * 1994-12-29 1996-09-13 Nitto Denko Corp 半導体装置及びその製造方法
US5661086A (en) * 1995-03-28 1997-08-26 Mitsui High-Tec, Inc. Process for manufacturing a plurality of strip lead frame semiconductor devices
JP3060896B2 (ja) * 1995-05-26 2000-07-10 日本電気株式会社 バンプ電極の構造
DE19541039B4 (de) * 1995-11-03 2006-03-16 Assa Abloy Identification Technology Group Ab Chip-Modul sowie Verfahren zu dessen Herstellung
US5677567A (en) * 1996-06-17 1997-10-14 Micron Technology, Inc. Leads between chips assembly
US5902686A (en) * 1996-11-21 1999-05-11 Mcnc Methods for forming an intermetallic region between a solder bump and an under bump metallurgy layer and related structures
JP3611948B2 (ja) * 1997-05-16 2005-01-19 日本テキサス・インスツルメンツ株式会社 半導体装置及びその製造方法
US5923234A (en) * 1997-10-27 1999-07-13 Lockheed Martin Corp. Hermetic feedthrough using three-via transmission lines
JP3042613B2 (ja) * 1997-11-27 2000-05-15 日本電気株式会社 半導体装置およびその製造方法
DE19800566A1 (de) * 1998-01-09 1999-07-15 Siemens Ag Verfahren zum Herstellen eines Halbleiterbauelementes und ein derart hergestelltes Halbleiterbauelement
US6075712A (en) * 1999-01-08 2000-06-13 Intel Corporation Flip-chip having electrical contact pads on the backside of the chip
US6011314A (en) * 1999-02-01 2000-01-04 Hewlett-Packard Company Redistribution layer and under bump material structure for converting periphery conductive pads to an array of solder bumps
TW434848B (en) * 2000-01-14 2001-05-16 Chen I Ming Semiconductor chip device and the packaging method
TW494548B (en) * 2000-08-25 2002-07-11 I-Ming Chen Semiconductor chip device and its package method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7215017B2 (en) 2003-05-02 2007-05-08 Yu-Nung Shen Wafer level package, wafer level packaging procedure for making wafer level package

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