TW495933B - Semiconductor chip device and encapsulation method thereof - Google Patents

Semiconductor chip device and encapsulation method thereof Download PDF

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Publication number
TW495933B
TW495933B TW89100578A02A TW495933B TW 495933 B TW495933 B TW 495933B TW 89100578A02 A TW89100578A02 A TW 89100578A02A TW 495933 B TW495933 B TW 495933B
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conductive
semiconductor wafer
scope
contact
item
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I-Ming Chen
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I-Ming Chen
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  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

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495933 五、發明說明（1) 本發明係有關於一種半導體晶片裝置及其封裝方法追 加二，更特別地，係有關於第8 9 1 0 0 5 78號發明專利申請案 之追加案者。 前揭本案之母案主要係鑑於晶片之表面上的銲墊隨著 半導體製程的發展而會變得越來越小，且銲墊間的距離亦 會越益縮小，以致於在與外部電路電氣連接時變得非常不 易，進而影響生產良率，甚至影響半導體製程繼續的發展 ，故本案發明人即研發出母案『半導體晶片裝置及其封裝 方法』。如今，本案發明人就封裝方法的製程，提出與母 案不同之其他可行的方式。 彳 有鑑於此，本案發明人遂以其從事該行業之多年經驗 u ，並本著精益求精之精神，積極研究改良，遂有本發明『 半導體晶片裝置及其封裝方法追加二』產生。 本發明之目的是為提供一種半導體晶片裝置及其封裝 方法追加二。 根據本發明之一特徵，一種半導體晶片裝置的封裝方. 法追加二，該半導體晶片裝置係適於安裝在一具有數個銲 墊的基板上，該方法包含如下之步驟：提供一半導體晶元 ，該半導體晶元具有一設置有數個銲墊的銲墊安裝表面且 於每一銲墊上形成一導電觸點；形成一感光薄膜層於該晶 胃 〆 ·......... - ---- 元的銲墊安裝表面上；把一覆蓋該感光薄膜層之f應於該 晶元之銲墊之部份的光罩置放於該感光薄膜層上並且對該 感光薄膜層進行曝光處理；在移去該光罩之後以化學沖洗 手段把該感光薄膜層之被該光罩覆蓋的部份沖洗去除，以
五、發明說明（2) 巧點被暴露;及以導 婀、_上形成有導電體，各導恭雕舲為材料，於該感光 二：電氣連接的觸點連接部、】：係具有—與對應之導電 乍為電路軌跡的延伸部、和一 /、觸點連接部電氣連接且 之位置係與該基板之對應之銲％ : f延伸部之自由端且其 之位置對應的電氣連接部 根據本發明的另一 方法追加二該半導體曰曰“ ；導體晶片裝置的封裝 辞塾的基板上，該方法包含^係適於安裝在-具有數個 70，該半導體晶元具有—机 ，步驟：提供一半導體晶 且於每-鮮墊上形成_導數個銲塾的銲墊安裝表面 ，於該晶元的銲墊安梦本^ /、、，及以導電金屬膠為材料 具有-與對應之導電以有導電體，各導電體係 點連接部電氣連接且作為# 的觸點連接部、一與觸 延伸部之自由端且其I。”跡的延伸部、和-位於該 置對應的電氣連接部。 $吳5亥基板之對應之銲點之位 根據本發明的又另一 一 二，其係適於安步為 / ，一種半導體晶片裝置追加 晶片裝置追加二：個銲墊的基板上，該半導體 -設置有數個銲墊的銲墊J:::把該半導體晶元具有 導電觸點；一感光每β ι表面及形成於每一銲墊上的 的銲墊安裝表面上\對=感光薄膜層係形成於該晶元 用以暴露對應之導電觸點；：該等導電觸點形成有數個 薄膜層上的導電冑，各導^Ί右及數個形成於該感光 '私to仏具有一與對應之導電觸點 第5頁 495933 五、發明說明（3) — 電氣連接的觸點連接部、一與觸點連接部電氣連 電路軌跡的延伸部、和一位於該延伸部之自由％且且作為 置係與該基板之對應之銲點之位置對應的電氣連 f之位 根據本發明的再另一特徵，一種半導體晶片 #。 二，其係適於安裝在一具有數個銲墊的基板上，广置追加 裝置追加二包含：一半導體晶元，該半導體晶元f半導體 置有數個銲墊的銲墊安裝表面及形成於每—銲“有一設 角:點；&形成於該晶元之銲墊安裝表面上的數j的導電 ^ 係具有一與對應之導電觸點電氣連接的=電體， 和-位於該延伸部之自由…之的延伸部、 之鮮點之位置對應的電氣連接部。 “亥基板之對應 有關本發明為逵 其功效，茲例舉較佳者^ 2的、特徵所採用的技術手段及 弟一至五圖是為 口圖式況明如下： 曰曰片t置之封農方法的示 〖.較佳貫施例之半導體 壯第C圖是為描繪本發明第二二i — 裝置的示意剖視圖；& 一乂佳實施例之半導體晶片 曰K ^ ^至八圖是為描繪本發明第—& 曰曰片衣置之封裝方法之 f二較佳實施例之半導體 第九圖是為# ^ ^的不思剖視圖； 衣置的不意剖視圖； 季乂佳戶'轭例之半導體晶片 弟十圖是為描繪本發 裝置的示意剖視圖·，及& 車父佳實施例之半導體晶片
495933
五、發明說明（4) 第十一圖是為描繪本發明第六較佳實施例之半導體晶 片裝置的示意剖視圖。 元件標號對照表 1 日日元 10 知塾安裝表面 1 1 銲墊 2 導電觸點 3 感光薄膜層 4 光罩 5 導電體 5 0 〇觸點連接部 501延伸部 502電氣連接部 6 連接觸點 3 0 暴露孔
在本發明被詳細描述之前，應要注意的是，在整個說 明當中，相同的元件係由相同的標號標示。 本發明之半導體晶片裝置係適於安裝至一基板（圖中 未示）上。遠基板係與母案中所述的基板類似，其係具有 一晶片安裝區域，且於該晶片安裝區域内係設有數個銲點 凊參閱第一圖所示 ^ 半導體晶元1首先被提供。
半導體晶兀1具有一設置有數個銲墊11 (圖式中僅顯示 们）的如墊女裝表面1 〇。該等銲墊11的位置係不對應於 基板之銲點的位置。接著，藉由習知技術，於每一銲墊 上形成=如導電金屬球般的導電觸點2 。 兮曰L 著的::Ϊ :圖所顯示般，-感光薄膜層3係形成 = 安|表面10上。然後，請參閱第：圖所 的：L感光薄膜層3之對應於該等導電觸二2一 Ξ; 的先罩4係、置放於該感光薄 觸點2之π 、層3上。然後，對該感光 495933 五、發明說明（5) _____ 膜層3進行曝光處理以致於該感光 4覆蓋的部份會硬化。 、、θ d之未被該光罩 請參閱第四圖所示，該感光 的部份然後係以習知技術沖洗去•二：被該光罩覆蓋 對應之導電觸點2的暴露孔3 〇。 形成用以暴露 接著，如第五圖所示般，係以 該感光薄膜層3上形成有導電體5 。在ί屬私為材料，於 電金屬膠可以是為摻雜有金、銀、隹本貫施例中，該導 導電金屬材料中之一種的邕帝^二銅、鐵、錫和鋁般等等 一與對應之導電觸點2電氣^接_私。各導電體5係具有 觸點連接部5 0 0電氣連接且：觸點連接部500、一與 和一位於該延伸部5〇1之自:％路軌跡的延伸部501 、 對應之銲點之位置對應 且其之位置係與該基板之 電體5係經由加執妹=_兒虱連接部5 0 2 。其後，該等導 …、；乾處理而帶締以 守 應要注意的是，在本告〃更性。 以與與母案雷同的印 二施例中，由於該等導電體5係 接著，在各導带卿ς 形成，於此恕不再贅述。 技術形成一如導電入^的兒氣連接部5 0 2上，係以習知 請參閱第六_所示，1 連接觸點6 。 例的示意剖視圖。在I告二疋為描繪本發明第二較佳實施 5的形成時以與導命轉貝％例中，連接觸點6係於導電體 請參閱第七d相同的材質-體地形成。 實施例之封裝方法的=立不’其是為描繪本發明第三較佳 ，在移去光罩之後，、I二纠視圖。與第一較佳實施例不同 ，稭由控制沖洗時間，感光薄膜層3之
胃8頁 4^5933 五、發明說明（6) 被該光罩覆蓋 對應之導電觸 對該感光薄膜 例般，係以導 有導電體5 ， &導電錫球般 請參閱第 ^的示意剖視 使’籍由控制 2々係僅被沖 3 <項端部份 #行曝光處 金屬膠為材料 接觸點6 。 請參閱第 句的示意剖視 $ %成於該晶 ^ 請參閱第 %例的示意剖 直接形成於該 、 综上所述 追力Π〜 ，石左 ^-』 ，々隹 目的與功效， Μ I利之新穎 的部份 點2 之 層3 進 電金屬 及於各 的連接 九圖所 圖。與 沖洗時 洗去除 暴露的 理。接 ，於該 係僅被沖洗去 頂端部份暴露 行曝光處理。 膠為材料，於 導電體5的電 觸點6 。 示’其是為描 第二較佳實施 間’感光薄膜 一部份，以形 暴露孔3 0。然 措’如第二較 感光薄膜層3 除一部份，以形成僅將 的暴露孔30。然後，再 接著，如第一較佳實施 該感光薄膜層3上形成 氣連接部5 0 2上形成一 繪本發明第四較佳實施 例不同，在移去光罩之 層3之被該光罩覆蓋的 成僅將對應之導電觸點 後，再對該感光薄膜層 佳實施例般，係以導電 上形成有導電體5和二 十圖所示’其是為描繪本發明第五較佳每a 圖。與第一較佳實施例不同’導電體5二知 元1的鲜塾安裝表面1〇上。 - '、直 十一圖所示，其是為描繪本發明第六較 視圖。與第二較佳實施例不同，導電體5 ^ 晶元1的銲墊安裝表面1 0上。 ilx ，本發明之『半導體晶片裝置及其封裝 能藉上述所揭露之構造、裝置，诖 ’ 咬到預期$ 且申請前未見於刊物亦未公開使用，#人& 、進步等要件。 付3發
第9頁 495933 五、發明說明（7) 惟，上述所揭之圖式及說明，僅為本發明之實施例而 已，非為限定本發明之實施例；大凡熟悉該項技藝之人仕 ，其所依本發明之特徵範疇，所作之其他等效變化或修飾 ，皆應涵蓋在以下本案之申請專利範圍内。

Claims (1)

  1. 495933 六、申請專利範圍 1 · 一種半導體晶片裝置的封裝方法追加 該半導體晶片 該方法包 裝置係適於安裝在一具有數個銲墊的基板上’ 含如下之步驟： 一# ψ #數 提供一半導體晶元’該半導體晶元具有 …帝 個銲墊的鋒墊安裝表面且於每一鮮墊上形成導私觸點 ，該等銲墊的位置係不對應於該基板之銲點的位置·， 、形成一感光薄膜層於該晶元的銲墊安裝表面上， 把—覆t感光薄膜層&對應於該等導電觸點之部 份的光罩置；於該感光薄膜層上並且對該感光薄胰層進 行曝光處理； 在移去該光罩之後以化學沖洗手段把該感光薄膜層 之被該光罩覆蓋之部份中的至少一部份沖洗去除，以致 於導電觸點被暴露；及 — 以導電金屬膠為材料，於該感光薄膜層上形成有導 電體’各導電體係具有一與對應之導電觸點電氣連接的 觸7連接部、一與觸點連接部電氣連接且作為電路軌跡 的延伸部、和一位於該延伸部之自由端且其之位置係與 5玄基板之對應之銲點之位置對應的電氣連接部。 2·如=請專利範圍第1項所述之封裝方法追加二，在形成 導電體的步驟之後，更包含如下之步驟： $各導電體的電氣連接部上，形成一連接觸點。 3 ·如申請專利範圍第2項所述之封裝方法追加二，其中， 在形成連接觸點的步驟中，該等連接觸點是為導電鍚球
    •如申請專利範圍第2項所述之封裝方法追加二，其中， 在形成連接觸點的步驟中，導電觸點係於導電體的彤 時以與導電體相同的材質〆體地形成。 ^ •如申請專利範圍第1項所述之封裝方法追加二，其中， 在提供半導體晶元的步驊中，該等導電觸點是為導電锡
    士申W專利範圍第1項所述之封農方法追加二，其中 在形成導電體的步驟中，導電金屬膠可以是為摻雜有 % 、銀、銅、鐵、錫和鋁般等等導電金屬材料中之一種 導電金屬膠。 7 ·如申请專利範圍第1項所述之封裝方法追加二，其中， 在該化學沖洗步驟中，係藉由控制沖洗時間使感光薄膜 層之被該光罩覆蓋的部份係僅被沖洗去除一部份，以形 成僅將對應之導電觸點之頂端部份暴露的暴露孔，且其 中’在該化學沖洗步驟之後，該方法更包含再對該感光 薄膜層進行曝光處理的步驟。 8· —種半導體晶片裳置的封裝方法追加二，該半導體晶片 裝置係適於安裝在一具有數個銲墊的基板上，該方法包 含如下之步驟：
    提七、半導體晶元，該半導體晶元具有一設置有數 個銲塾1銲塾安裝表面且於每—_墊上形成—導電觸點 ’。亥等銲墊的位置係不對應於該基板之銲點的位置；及 以導電金屬膠為材料，於該曰曰曰元的鮮墊安裝表面上 形成有導電體，I導電體係具有一與對應之導電觸點電
    、第12頁
    …申請專利範圍
    氣連接的觸點連接部、一 電路軌跡的延伸部、和一 &置係與該基板之對應之 與觸點連接部電氣連接且作為 位於该延伸部之自由端且其之 銲點之位置對應的電氣連接部 •如申請專利範圍第8項所述之封裝方法追加二，在形成 導電體的步驟之後，更包含如下之步驟： 在各導電體的電氣速接部上，形成一連接觸點。 I 0 ·如申請專利範圍第9項所述之封裝方法追加二，其中 4 ’在形成連接觸點的步騍中’該等連接觸點是為導電 锡球。 II ·如申請專利範圍第9項所述之封裴方法追加二，其中 ’在形成連接觸點的步雜中’導電觸點係於導電體的 形成時以與導電體相同的材質一.體地形成。 1 2·如申請專利範圍第8項所述之封裝方法追加二，其中 ’在提供半導體晶元的少驟中’該等導電觸點是為導 電錫球。
    1 3·如申請專利範圍第8項所述之封裝方法追加二，其中 ’在形成導電體的步驟中’導電金屬膠可以是為摻雜 有金、銀、鋼、鐵、錫和紹般等等導電金屬材料中之 一種的導電金屬膠。 14· 一種半導體晶片裝置追加二’其係適於安裝在一具有 數個銲墊的基板上，該半導體晶片裝置追加二包含： 一半導體晶元，該半導體晶元具有一設置有數個 銲墊的銲墊安裝表面及形成於每一銲墊上的導電觸點
    第13頁 495933 日修正/史補无 申請專利範圍 ’該等銲墊的位置係不對應於該基板之銲點的位置； 一感光薄膜層’該感光薄膜層係形成於該晶元的 銲墊安裝表面上，並且對應於該等導電觸點形成有數 们用以至少暴路對應之導電觸點之頂端部份的暴露孔 ;及 ~ 數個形成於該感光薄膜層上的導電體，各導電體 係具有一與對應之導電觸點電氣連接的觸點連接部^ 一與觸點連接部電氣連接且作為電路執跡的延伸^、 和一位於該延伸部之自由端且其之位置係與該基板之 對應之銲點之位置對應的電氣連接部。 i 1 5·如申請專利範圍第i 4項所述之半導體晶片裳置追加二 ’更包含形成於各導電體之電氣連接部上的連接觸點 〇 1 6.如申請專利範圍第丨5項所述之半導體晶片裝置追加二 其中：该等連接觸點是為導電錫球。 •如申睛專利範圍第1 5項所述之半導體晶片裝置追加二 ’其中，導電觸點係以與導電體相同的材質一體地形 成。 、 18.如申請專利範圍第14項所述之半導體晶片裝置追加二 其中’该等導電觸點是為導電錫球。 1 9·如申請專利範圍第1 4項所述之半導體晶片裝置追加二 ’其中，導電體係由導電金屬膠形成。 2 〇 ·如申請專利範圍第1 9項所述之半導體晶片裝置追加二 ’其中，導電金屬膠可以是為摻雜有金、銀、銅、鐵
    第14頁 495933 六、申請專利範圍 、錫和鋁般等等導電金屬材料中之一種的導電金屬膠 〇 21· —種半導體晶片裝置追加二，其係適於安裝在一具有 數個銲墊的基板上，該半導體晶片裝置追加二包含： 一半導體晶元，該半導體晶元具有一設置有數個 銲墊的銲墊安裝表面及形成於每一銲墊上的導電觸點 ，該等銲墊的位置係不對應於該基板之銲點的位置； 及 形成於該晶元之録墊安裝表面上的數個導電體， 各導電體係具有一與對應之導電觸點電氣連接的觸點 連接部、一與觸點連接部電氣連接且作為電路軌跡、 延伸部、和一位於該延伸部之自由端且其之彳立置係2 該基板之對應之銲點之位置對應的電氣連接部。'人 22·如申請專利範圍第21項所述之半導體晶片骏置追加一 ，更包含形成於各導電體之電氣連接部上的連接觸= 〇 2 3 ·如申請專利範圍第2 2項所述之半導體晶片裝置追加一 ，其中，該等連接觸點是為導電錫球。 — 2 4 ·如申凊專利範圍第2 2項所述之半導體曰曰片裝置追力σ 一 ，其中，導電觸點係以與導電體相同的材質一體地& 成。 25·如申請專利範圍第21項所述之半導體晶片裝置追加二 ’其中，該等導電觸點是為導電錫球。 2 6 ·如申請專利範圍第2 1項所述之半導體晶片装置追加一
    第15頁 495933 六、申請專利範圍 ，其中，導電體係由導電金屬膠形成。 2 7.如申請專利範圍第2 6項所述之半導體晶片裝置追加二 ，其中，導電金屬膠可以是為摻雜有金、銀、銅、鐵 、錫和鋁般等等導電金屬材料中之一種的導電金屬膠
    第16頁
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