TW200812027A - Flip-chip attach structure and method - Google Patents

Flip-chip attach structure and method Download PDF

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Publication number
TW200812027A
TW200812027A TW95130892A TW95130892A TW200812027A TW 200812027 A TW200812027 A TW 200812027A TW 95130892 A TW95130892 A TW 95130892A TW 95130892 A TW95130892 A TW 95130892A TW 200812027 A TW200812027 A TW 200812027A
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TW
Taiwan
Prior art keywords
copper
substrate
layer
chip bonding
flip chip
Prior art date
Application number
TW95130892A
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Chinese (zh)
Inventor
Wen-Cheng Kao
Original Assignee
Int Semiconductor Tech Ltd
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Publication date
Application filed by Int Semiconductor Tech Ltd filed Critical Int Semiconductor Tech Ltd
Priority to TW95130892A priority Critical patent/TW200812027A/en
Publication of TW200812027A publication Critical patent/TW200812027A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

Abstract

A flip-chip attach structure mainly includes a substrate and a chip. A substrate has a copper circuit layer and a solder resistor, the copper circuit layer has a plurality of copper contacts, the solder resistor is located over the copper circuit layer and the copper contacts are exposed. A plurality of gold bumps of the chip are connected to the contacts of the substrate to electrically connect the substrate and the chip. The gold bumps bond to the copper contacts by introducing a thermosonic bonding machine to avoid the fail the connecting between the gold bumps and the copper contacts.

Description

200812027 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種覆晶接合構造，特別係有關於一 種金凸塊直接鍵結於銅接點之覆晶接合構造。 【先前技術】 由於覆晶封裝技術具有電性佳、尺寸小、散熱佳及高 功能等優點，因此覆晶技術廣泛應用於電子產業中。 如第1圖所示，習知覆晶接合構造1 00係包含一基板 110、一晶片120以及一底膠13〇。該基板110之一上表面 111係形成有一銅線路層112, 一錫層113係形成於該銅線 路層112並完全覆蓋該銅線路層丨丨2以避免該銅線路層 112因氧化而產生一氧化層（圖未繪出），在該錫層ιΐ3上 係形成有一阻銲層114，該阻銲層114係顯露部分該錫層 113，該晶片120之一主動面121上之複數個金凸塊122 係藉由該錫層113與該基板110之該銅線路層112電性連 接，然而在超音波壓銲之過程中常因該錫層113之潤滑特 性會使得該些金凸塊122與該鋼線路層112之摩擦力降 低，而導致该些金凸塊i 22無法順利鍵結於該銅線路芦 112。 曰 【發明内容】 本發明之主要目的係在於提供一種覆晶接合構造及 其方法，一基板係具有一銅線路層及一阻銲層，該阻銲層 係位於該銅線路層上並顯露該銅線路層之複數個銅接 點，該晶片之複數個金凸塊係以超音波壓銲機壓銲接合至 5 200812027 該基板之該些銅接點，利用超音波μ銲接合該些金凸塊與 該些銅接點係可使該些金凸塊直接鍵結於該些銅接點，因 此可避免該些金凸塊與該些銅接點電性連接失敗。 :據本發明之一種覆晶接合構造主要包含一基板以 及ΒΒ片。3亥基板係具有一銅線路層及一阻銲層，該銅線 路層係具有複數個銅接點，該阻銲層係位於該銅線路層上 並顯露該些銅接點，該晶片係以超音波壓銲接合於該基 板，該晶片係具有複數個金凸塊，該些金凸塊係直接鍵結 於該些銅接點。 【實施方式】 請參閱第2圖，依據本發明之第一具體實施例係揭示 一種覆晶接合構造200,其係包含一基板21〇以及一晶片 220。該基板之一上表面211係具有一銅線路層及一 阻如層2 13，该基板2 1 〇係選自於可撓性電路基板、玻璃 基板、硬質印刷電路板與陶瓷基板之其中之一。該銅線路 層212係具有複數個銅接點212a，在本實施例中，該些銅 接點212a係為銅線路層212之凸塊接墊，該阻銲層213 係位於該銅線路層212上並顯露該些銅接點212a，此外， 该基板2 1 0係可另包含有一錫層2丨4，該錫層2丨4係形成 於该銅線路層2 12與該阻銲層2 1 3之間並顯露該些銅接點 212a，該阻銲層213係可顯露部分該錫層214，或者，請 參閱第3圖’在另一實施例中，該阻銲層2丨3係可完全覆 蓋該錫層214。請再參閱第2或3圖，該晶片220之一主 動面221係具有複數個金凸塊222，藉由一超音波壓銲機 6 200812027 (圖未繪出）將該晶片220壓銲接合至該基板21 0，以使 該晶片220之該些金凸塊222係直接鍵結該基板210之該 些銅接點212a，以避免該些金凸塊222與該些銅接點212a 電性連接失敗，該些銅接點2 12a與該些金凸塊222係藉 由超音波壓銲鍵結，該超音波壓銲機所產生之能量可使該 些金凸塊222直接鍵結於該些銅接點212a。該覆晶接合構 造200係另包含有一底膠23〇，該底膠23〇係形成於該晶 片220與該基板2 1 〇之間並覆蓋部份該阻銲層2丨3以保護 該些金凸塊222。 凊參閱第4A至4G圖，其係為本發明之第一具體實施 例之接合方法，首先，請參閱第4 A圖，提供一基板2丨〇， 該基板210之一上表面211係具有一銅線路層2 i2，該銅 線路層212係圖案化一銅層所形成，如以蝕刻方法圖案化 該銅層，該銅線路層212係具有複數個銅接點2i2a，該些 銅接點212a係為銅線路層212之凸塊接墊，之後，請參 閱第4B圖，形成一光阻層24〇於該基板21〇之該上表面 211並圖案化該光阻層24〇,經圖案化步驟之該光阻層24〇 係覆蓋該些銅接點212a。接著，請參閱第4c圖，可形成 一錫層214於該銅線路層212之上。之後，請參閱第扣 圖，移除該光阻層24〇,該錫層214係形成於該銅線路層 212上並顯露該些銅接點212a，該錫層214係可以電鍍等 方式开乂成#著，明參閱第4E圖’形成一阻銲層：㈠於 該銅線路層212上，該阻銲層213係顯露部分該錫層214 與該些銅接點212a，該阻鮮層213係以印刷方式形成。之 7 200812027 後，請參閱第4F圖，提供一晶片220，其係具有複數個金 凸塊222，接著，請參閱第4G圖，利用超音波壓銲機1〇 壓銲接合該晶片220至該基板210，該晶片220之該些金 凸塊222係直接鍵結於該些銅接點2丨2a，以電性連接該基 板210與該晶片220。最後，形成一底膠230於該晶片22〇 與該基板210之間並覆蓋部分該阻銲層213即可得如第2 圖所示之覆晶接合構造200。 本發明之保護範圍當視後附之申請專利範圍所界定 者為準，任何熟知此項技藝者，在不脫離本發明之精神和 範圍内所作之任何變化與修改，均屬於本發明之保護範 圍。 【圖式簡單說明】 第1 圖·習知覆晶接合構造之截面示意圖。 第2 圖·依據本發明之第一具體實施例，一種覆晶 接合構造之截面示意圖。 第3 圖·依據本發明之第二具體實施例，一種覆晶 接合構造之截面示意圖。 第4A至4G圖：依據本發明之第一具體實施例，該覆晶接 合方法之截面示意圖。 【主要元件符號說明】 10 超音波壓銲機 1〇〇 覆晶接合構造 110 基板 113 錫層 111 上表面 i i 2 銅線路層 114 阻銲層 120晶片 8 200812027 121 主動面 122 金凸塊 130 底膠 200 覆晶接合構造 210 基板 211 上表面 212 銅線路層 212a 銅接點 213 阻銲層 214 錫層 220 晶片 221 主動面 222 金凸塊 230 底膠 240 光阻 9200812027 IX. INSTRUCTIONS OF THE INVENTION: TECHNICAL FIELD The present invention relates to a flip chip bonding structure, and more particularly to a flip chip bonding structure in which a gold bump is directly bonded to a copper contact. [Prior Art] Since the flip chip packaging technology has the advantages of good electrical properties, small size, good heat dissipation, and high function, flip chip technology is widely used in the electronics industry. As shown in Fig. 1, a conventional flip chip bonding structure 100 includes a substrate 110, a wafer 120, and a primer 13A. A copper circuit layer 112 is formed on one surface 111 of the substrate 110. A tin layer 113 is formed on the copper circuit layer 112 and completely covers the copper circuit layer 2 to prevent the copper circuit layer 112 from being oxidized. An oxide layer (not shown) is formed on the tin layer ι 3 to form a solder resist layer 114. The solder resist layer 114 exposes a portion of the tin layer 113. The plurality of gold bumps on the active surface 121 of the wafer 120 The block 122 is electrically connected to the copper circuit layer 112 of the substrate 110 by the tin layer 113. However, in the process of ultrasonic pressure welding, the gold bumps 122 are often caused by the lubricating properties of the tin layer 113. The frictional force of the steel circuit layer 112 is lowered, and the gold bumps i 22 cannot be smoothly bonded to the copper wire reeds 112. SUMMARY OF THE INVENTION The main object of the present invention is to provide a flip chip bonding structure and a method thereof, a substrate having a copper wiring layer and a solder resist layer, the solder resist layer being on the copper wiring layer and exposing the a plurality of copper bumps of the copper circuit layer, wherein the plurality of gold bumps of the wafer are pressure-welded by an ultrasonic welding machine to the copper contacts of the substrate of 200820082, and the gold bumps are welded by ultrasonic ultrasonic welding The blocks and the copper contacts enable the gold bumps to be directly bonded to the copper contacts, thereby preventing the gold bumps from failing to electrically connect the copper contacts. A flip chip bonding structure according to the present invention mainly comprises a substrate and a die. The 3H substrate has a copper circuit layer and a solder resist layer, the copper circuit layer having a plurality of copper contacts, the solder resist layer being on the copper circuit layer and exposing the copper contacts, the wafer is Ultrasonic pressure welding is applied to the substrate, and the wafer has a plurality of gold bumps directly bonded to the copper contacts. [Embodiment] Referring to Figure 2, a flip-chip bonding structure 200 comprising a substrate 21A and a wafer 220 is disclosed in accordance with a first embodiment of the present invention. One of the upper surfaces 211 of the substrate has a copper circuit layer and a resistive layer 2 13, which is selected from one of a flexible circuit substrate, a glass substrate, a hard printed circuit board and a ceramic substrate. . The copper circuit layer 212 has a plurality of copper contacts 212a. In the embodiment, the copper contacts 212a are bump pads of the copper circuit layer 212, and the solder resist layer 213 is located on the copper circuit layer 212. The copper contacts 212a are exposed and exposed. Further, the substrate 210 may further include a tin layer 2?4, and the tin layer 2?4 is formed on the copper circuit layer 212 and the solder resist layer 2 The copper contacts 212a are exposed between the three, and the solder resist layer 213 can expose a portion of the tin layer 214. Alternatively, please refer to FIG. 3. In another embodiment, the solder resist layer 2丨3 can be The tin layer 214 is completely covered. Referring to FIG. 2 or 3, one active surface 221 of the wafer 220 has a plurality of gold bumps 222, and the wafer 220 is pressure-bonded to the ultrasonic wave soldering machine 6 200812027 (not shown). The substrate 21 0 is such that the gold bumps 222 of the wafer 220 directly bond the copper contacts 212a of the substrate 210 to prevent the gold bumps 222 from being electrically connected to the copper contacts 212a. In the case of failure, the copper contacts 2 12a and the gold bumps 222 are bonded by ultrasonic welding, and the energy generated by the ultrasonic welding machine can directly bond the gold bumps 222 to the gold bumps 222. Copper contact 212a. The flip chip bonding structure 200 further includes a primer 23 形成 formed between the wafer 220 and the substrate 2 1 并 and covering a portion of the solder resist layer 2 丨 3 to protect the gold Bump 222. 4A to 4G, which are the bonding methods of the first embodiment of the present invention. First, referring to FIG. 4A, a substrate 2 is provided, and an upper surface 211 of the substrate 210 has a a copper circuit layer 2 i2, the copper circuit layer 212 is formed by patterning a copper layer, such as an etching method, the copper circuit layer 212 has a plurality of copper contacts 2i2a, the copper contacts 212a The bump pad of the copper circuit layer 212 is formed. Then, referring to FIG. 4B, a photoresist layer 24 is formed on the upper surface 211 of the substrate 21 and the photoresist layer 24 is patterned and patterned. The photoresist layer 24 of the step covers the copper contacts 212a. Next, referring to FIG. 4c, a tin layer 214 may be formed over the copper wiring layer 212. Then, referring to the figure, the photoresist layer 24 is removed. The tin layer 214 is formed on the copper circuit layer 212 and exposes the copper contacts 212a. The tin layer 214 can be plated or the like. Referring to FIG. 4E, a solder resist layer is formed: (1) on the copper circuit layer 212, the solder resist layer 213 exposes a portion of the tin layer 214 and the copper contacts 212a, and the solder resist layer 213 It is formed by printing. After 200812027, referring to FIG. 4F, a wafer 220 is provided having a plurality of gold bumps 222. Next, referring to FIG. 4G, the wafer 220 is soldered by the ultrasonic welding machine 1 to the same. The substrate 210, the gold bumps 222 of the wafer 220 are directly bonded to the copper contacts 2丨2a to electrically connect the substrate 210 and the wafer 220. Finally, a primer 230 is formed between the wafer 22 and the substrate 210 to cover a portion of the solder resist layer 213 to obtain a flip chip bonding structure 200 as shown in FIG. The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. . BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional flip chip bonding structure. Fig. 2 is a schematic cross-sectional view showing a flip chip bonding structure in accordance with a first embodiment of the present invention. Fig. 3 is a schematic cross-sectional view showing a flip chip bonding structure in accordance with a second embodiment of the present invention. 4A to 4G are schematic cross-sectional views showing the flip chip bonding method in accordance with the first embodiment of the present invention. [Main component symbol description] 10 Ultrasonic welding machine 1〇〇 flip chip bonding structure 110 Substrate 113 Tin layer 111 Upper surface ii 2 Copper wiring layer 114 Solder mask layer 120 Wafer 8 200812027 121 Active surface 122 Gold bump 130 Primer 200 flip chip bonding structure 210 substrate 211 upper surface 212 copper wiring layer 212a copper contact 213 solder resist layer 214 tin layer 220 wafer 221 active surface 222 gold bump 230 primer 240 photoresist 9

Claims (1)

200812027 十、申請專利範圍： 1、 一種覆晶接合構造，包含： 一基板，其係具有—銅線路層及-阻銲層，該銅線路 層係具有複數個銅接點，該阻銲層係位於該銅線路層 上並顯露該些銅接點；以及 日日片，其係具有複數個金凸塊，該些金凸塊係直接 鍵結於該些銅接點。 2、 T申請專利範圍第"員所述之覆晶接合構造，其中該 晶片係利用超音波壓銲機壓銲接合於該基板。 3、 如申請專利範圍第"員所述之覆晶接合構造，其中該 基板係另包含有一錫層，該錫層係形成於該銅線路層 與該阻銲層之間並顯露該些銅接點。 4、 如申請專利範圍第！項所述之覆晶接合構造，其中該 基板係選自於可撓性電路基板、玻璃基板、硬質印刷 電路板與陶瓷基板之其中之一。 5、 如申請專利範圍第丨項所述之覆晶接合構造，其另包 含有一底膠，該底膠係形成於該晶片與該基板之間。 6、 一種覆晶接合方法，包含： 提供一基板，該基板係具有一銅線路層及一阻銲層， 該銅線路層係具有複數個銅接點，該阻銲層係位於該 銅線路層上並顯露該些銅接點； 提供一晶片’其係具有複數個金凸塊；以及 利用超音波壓銲接合該晶片與該基板，該晶片之該些 金凸塊係直接鍵結該些銅接點，以電性連接該晶片與 10 200812027 該基板。 7、 如申請專利範圍第6項所述之覆晶接合方法 銅線路層係圖案化一銅層所形成。 8、 t申請專利範圍第6項所述之覆晶接合方法 ' 乂成光阻層於該基板並圖案化該光 蓋該些銅接點。 9、 如申請專利範圍第6項所述之覆晶接合方法 含有.形成一錫層於該銅線路層並移除該光 中《玄錫層係顯露該些鋼接點。 10、如中請專利範㈣6項所述之覆晶接合方法 阻銲層係以印刷方式形成。 "'如申請專利範圍第6項所述之覆晶接合方法 錫層係以電鍍方式形成。 U、如申請專利範圍第6項所述之覆晶接合方法 含有：形成一底膠於該晶片與該基板之間。 ’其中該 ’其另包 阻層以覆 ’其另包 阻層，其 ，其中該 ，其中該 ，其另包 11200812027 X. Patent Application Range: 1. A flip chip bonding structure comprising: a substrate having a copper circuit layer and a solder resist layer, the copper circuit layer having a plurality of copper contacts, the solder resist layer Located on the copper circuit layer and exposing the copper contacts; and a Japanese wafer having a plurality of gold bumps directly bonded to the copper contacts. 2. The flip-chip bonding structure described in the Patent Application No. 2, wherein the wafer is pressure bonded to the substrate by an ultrasonic welding machine. 3. The flip chip bonding structure of claim 2, wherein the substrate further comprises a tin layer formed between the copper circuit layer and the solder resist layer and exposing the copper contact. 4, such as the scope of application for patents! The flip chip bonding structure according to the item, wherein the substrate is selected from the group consisting of a flexible circuit substrate, a glass substrate, a hard printed circuit board, and a ceramic substrate. 5. The flip chip bonding structure of claim 2, further comprising a primer, the primer being formed between the wafer and the substrate. 6. A flip chip bonding method, comprising: providing a substrate having a copper circuit layer and a solder resist layer, the copper circuit layer having a plurality of copper contacts, the solder resist layer being located on the copper circuit layer And exposing the copper contacts; providing a wafer having a plurality of gold bumps; and ultrasonically bonding the wafer and the substrate, the gold bumps of the wafer directly bonding the copper A contact is electrically connected to the wafer with the substrate of 10 200812027. 7. The flip chip bonding method according to claim 6, wherein the copper wiring layer is formed by patterning a copper layer. 8. The method of flip chip bonding described in claim 6 of the patent application is as follows: forming a photoresist layer on the substrate and patterning the light to cover the copper contacts. 9. The flip chip bonding method of claim 6, wherein forming a tin layer on the copper wiring layer and removing the light "the tin-tin layer reveals the steel contacts. 10. The flip chip bonding method described in the sixth paragraph of the patent specification (4) is formed by printing. "'The flip chip bonding method as described in claim 6 is formed by electroplating. U. The flip chip bonding method of claim 6, comprising: forming a primer between the wafer and the substrate. 'where the other of the barrier layers is covered to cover the other barrier layer, which, where the
TW95130892A 2006-08-22 2006-08-22 Flip-chip attach structure and method TW200812027A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI463585B (en) * 2012-01-03 2014-12-01 Chipbond Technology Corp Semiconductor package and method thereof
TWI631684B (en) * 2017-09-05 2018-08-01 恆勁科技股份有限公司 Medium substrate and the manufacture thereof
TWI769337B (en) * 2017-11-08 2022-07-01 日商日亞化學工業股份有限公司 Light emitting device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI463585B (en) * 2012-01-03 2014-12-01 Chipbond Technology Corp Semiconductor package and method thereof
TWI631684B (en) * 2017-09-05 2018-08-01 恆勁科技股份有限公司 Medium substrate and the manufacture thereof
TWI769337B (en) * 2017-11-08 2022-07-01 日商日亞化學工業股份有限公司 Light emitting device

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