KR101618878B1 - Non solder bonding method and PCB by the same - Google Patents

Non solder bonding method and PCB by the same Download PDF

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Publication number
KR101618878B1
KR101618878B1 KR1020090122474A KR20090122474A KR101618878B1 KR 101618878 B1 KR101618878 B1 KR 101618878B1 KR 1020090122474 A KR1020090122474 A KR 1020090122474A KR 20090122474 A KR20090122474 A KR 20090122474A KR 101618878 B1 KR101618878 B1 KR 101618878B1
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KR
South Korea
Prior art keywords
circuit pattern
electronic device
external terminal
circuit board
printed circuit
Prior art date
Application number
KR1020090122474A
Other languages
Korean (ko)
Other versions
KR20110065806A (en
Inventor
백지흠
Original Assignee
엘지이노텍 주식회사
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Priority to KR1020090122474A priority Critical patent/KR101618878B1/en
Publication of KR20110065806A publication Critical patent/KR20110065806A/en
Application granted granted Critical
Publication of KR101618878B1 publication Critical patent/KR101618878B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

Solder type electronic element package, and more particularly to a method of bonding an external terminal of an electronic device chip on a circuit pattern of a printed circuit board on which a functional hole is formed by a resistance welding method .

According to the present invention, it is possible to solve the disadvantages of productivity due to the frequent and frequent occurrence of joint errors, which is brought about by solder bonding for bonding a semiconductor or an LED to a printed circuit board, thereby providing a functional hole in the printed circuit board, The device chip and the circuit pattern can be directly bonded by resistance welding to improve the reliability and realize an eco-friendly effect.

Package for electronic device, external terminal, resistance welding, functional hole

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a printed circuit board having a non-

The present invention relates to a method of bonding an electronic device package onto a printed circuit board and a structure of a printed circuit board having the electronic device package.

Semiconductor chips have become increasingly compact, multifunctional, high-performance, and large-capacity, and packaging technology has become increasingly important as a key technology that ultimately determines the device's electrical performance, reliability, productivity, and miniaturization of electronic systems . Packaging technology refers to a series of processes that ultimately commercialize individual chips made in a wafer process. In recent years, a ball grid array (BGA), a chip scale package (CSP) having almost the same size as a chip size, another stacked chip on a chip, Technologies such as a multi-chip module (MCM) in which a plurality of semiconductor chips are arranged in one package are emerging.

In particular, a semiconductor or LED chip is subjected to a process of bonding a chip and a package portion on a printed circuit board (PCB, FPCB). In this case, a method of reflowing the solder ball is generally used as a bonding method. That is, a solder process is performed to connect individual packages to the printed circuit board.

Referring to FIG. 1, there is shown a conceptual diagram for illustrating a process of bonding a chip for an electronic device to a printed circuit board by a solder ball method according to the related art.

More specifically, referring to FIG. 1, a conventional semiconductor package substrate according to a flip chip bonding method will be described. A circuit pattern 20 is formed on an insulating substrate 10 The chip 70 is mounted via the solder resist 50 and the die attach epoxy 60 which mounts the chip sequentially and the chip 70 is mounted on the circuit pattern 20 and the wire 80, And has a structure in which a molding 90 for protecting the chip and the wire is formed. In general, such a semiconductor package substrate is provided with a solder ball 30 at a lower portion of the substrate as an intermediary for bonding to a board. The solder ball 30 is electrically connected to the circuit pattern 20 of the substrate and the solder ball pads 31 To be electrically conductive. That is, the printed circuit board 1 forms a board having the circuit pattern 3 formed on the insulating substrate 2, and the circuit pattern 3 and the solder ball 30 of the above- . However, since such a solder bonding method uses a lead-based material, it is an environmentally unfavorable material. Since the solder bonding method requires individual bonding, productivity is greatly deteriorated. Furthermore, even if the solder bonding method is implemented by a process of automation or a process of automation, the problem of high defect rate due to high error rate occurs.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and it is an object of the present invention to solve the disadvantages of productivity caused by frequent bonding error and soldering bonding of a semiconductor or LED to a printed circuit board A functional hole is provided in the printed circuit board to bond the electronic device chip and the circuit pattern through direct resistance welding, thereby improving reliability. In addition, a bonding method capable of realizing an eco-friendly effect and a printed circuit board .

As a means for solving the above-mentioned problems, the present invention provides a method of manufacturing a semiconductor device, comprising: forming a functional hole through an upper surface and a lower surface of the insulating layer; Forming a circuit pattern covering the upper portion of the functional hole on the insulating layer; Disposing an electronic device chip on the insulating layer, and aligning an external terminal of the electronic device chip and the functional hole; And bonding the upper surface of the circuit pattern covering the upper portion of the functional hole to the lower surface of the external terminal by resistance welding.

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In particular, the resistance welding may be performed by any one of a spot welding method, an ultrasonic welding method, and a friction welding method.

When a circuit pattern is formed on the printed circuit board, the circuit pattern surface may be plated with a single layer or multiple layers using any one of Cu, Ni, Pd, Au, Sn, Ag and Co, Processing can be performed.

The electronic device chip according to the present invention is an LED or a semiconductor chip.

The printed circuit board formed according to the bonding method described above can be formed to have the following structure.

Specifically, specifically, a printed circuit board having an insulating layer including functional holes penetrating the top and bottom surfaces and a circuit pattern covering the top of the functional hole on the insulating layer; An electronic device chip having an external terminal to be bonded to an upper surface of the circuit pattern; Wherein a region of the circuit pattern vertically overlapped with the functional hole has a shape corresponding to the welding electrode and protrudes so that an upper surface thereof directly contacts a lower surface of the external terminal.

Particularly, in this case, the circuit pattern may be formed of a single layer or a multilayer plating layer using any one of Cu, Ni, Pd, Au, Sn, Ag and Co, or a binary or ternary alloy thereof on the circuit pattern surface .

According to the present invention, it is possible to solve the disadvantages of productivity due to the frequent and frequent occurrence of joint errors, which is brought about by solder bonding for bonding a semiconductor or an LED to a printed circuit board, thereby providing a functional hole in the printed circuit board, The device chip and the circuit pattern can be directly bonded by resistance welding to improve the reliability and realize an eco-friendly effect.

Hereinafter, the configuration and operation according to the present invention will be described in detail with reference to the accompanying drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description with reference to the accompanying drawings, the same reference numerals denote the same elements regardless of the reference numerals, and redundant description thereof will be omitted.

The bonding process according to the present invention is characterized in that the external terminals of the electronic device chip are bonded on the circuit pattern of the printed circuit board on which the functional hole is formed, by resistance welding.

2A is a flowchart and a process diagram illustrating a bonding process according to the present invention and a structure of a printed circuit board manufactured thereby.

Referring to the drawings, the method includes mounting and bonding a package on which a chip 131 for an electronic device is mounted on a circuit pattern 110 formed on a printed circuit board 100. In this case, the package in which the electronic device chip is mounted is a concept including a semiconductor package or an LED package. The electronic device chip having the external connection terminal 120, Is a concept that encompasses a package.

Specifically, the printed circuit board to which the electronic device package according to the present invention is bonded has a functional hole (H) in which a region where a circuit pattern is formed is opened. In particular, the functional hole (H) provides a space through which welding equipment can be introduced so that the outer terminal (120) of the electronic device package and the circuit pattern can be bonded by resistance welding.

The resistance welding according to the present invention can be performed by spot welding, ultrasonic welding, friction welding, or the like. However, as a preferred embodiment of the present invention, .

As shown in the drawing, the external terminals 120 formed on the upper portion of the functional hole and the spot welders 140 and 141 at the upper and lower portions of the circuit pattern 110 approach and pressurize, Heat is generated and bonded using this heat. Therefore, in the present invention, it is essential that a passageway accessible from upper and lower parts is formed in a region to be joined, and the functional hole H provides a functional space in which such a device can be accessed. In the conventional solder bonding, such a structure is unnecessary and the solder ball is reflowed on the pad to which the solder ball is to be attached. Thus, the resistance welding method as in the present invention can not be applied.

Figures 2b and 2c show the overall process flow diagram and process diagram according to the present invention.

First, in step S 1, in the bonding method according to the present invention, the functional hole H is processed on the printed circuit board 100 formed of an insulating layer. Various machining methods such as punching, mechanical drilling, and laser machining can be applied.

Thereafter, a metal layer 110 for forming a circuit is laminated on the upper surface of the printed circuit board 100, and then a circuit pattern 111 is formed by patterning the metal layer. The formation of the circuit pattern is generally performed by applying a photoresist, exposing, developing, or etching, followed by peeling off the photoresist. The metal layer 110 may be made of Cu as it is, or gold plating or tin plating may be performed to serve as a circuit on the surface. Further, a single layer or multilayer plating layer may be further formed on the circuit pattern surface using any one of Cu, Ni, Pd, Au, Sn, Ag and Co, or a binary or ternary alloy thereof so as to improve conductivity and bonding .

Thereafter, in step S 3, the package having the electronic element chip mounted therein is placed, and the external terminal 120 provided in the package is electrically connected to the area of the circuit pattern corresponding to the upper surface of the functional hole H of the printed circuit board (A). ≪ / RTI >

After that, the spot welding devices 140 and 141 are approached at the upper and lower portions of the external terminal 120 and the circuit pattern 111 that are formed, and resistance welding is performed by flowing current. As described above, various methods can be applied to the resistance welding method. In particular, the resistance welding method is implemented by the spot welding method. In the spot welding method described above, both ends of the overlapped external terminals and the circuit pattern are pressed with an appropriately formed electrode, and when electric current is applied to them, the electrical resistance of the contact surface is large, and heat is generated. The resistance of the contact surface soon disappears, but the temperature of the material rises due to this heat generation, so that the resistance of the base material itself increases and the temperature rises further. And the welding is performed by applying strong pressure thereto.

The foregoing detailed description of the invention has been presented for specific embodiments. However, various modifications are possible within the scope of the present invention. The technical idea of the present invention should not be limited to the embodiments of the present invention but should be determined by the equivalents of the claims and the claims.

1 is a conceptual view showing a process of solder bonding a conventional electronic device package to a printed circuit board.

2A is a conceptual diagram illustrating a non-solder bonding method according to the present invention.

FIGS. 2B and 2C illustrate an overall flowchart and a process diagram of a bonding process according to the present invention.

Claims (8)

Forming functional holes in the insulating layer through upper and lower surfaces of the insulating layer; Forming a circuit pattern covering the upper portion of the functional hole on the insulating layer; Disposing an electronic device chip on the insulating layer, and aligning an external terminal of the electronic device chip and the functional hole; And bonding the upper surface of the circuit pattern covering the upper portion of the functional hole and the lower surface of the external terminal by resistance welding. The method according to claim 1, Wherein a region of the circuit pattern, which is vertically overlapped with the functional hole, Wherein the upper surface is in direct contact with a lower surface of the external terminal, the upper surface of the external terminal being in contact with the welding electrode for resistance welding. delete The method according to claim 1, Wherein the resistance welding is performed by any one of a spot welding method, an ultrasonic welding method, and a friction welding method. The method according to claim 1, The step of forming the circuit pattern may include: Forming a single-layer or multi-layer plating process on the circuit pattern surface by using any one of Cu, Ni, Pd, Au, Sn, Ag and Co or a binary or ternary alloy thereof, A method of bonding a package. The method according to claim 1, Wherein the electronic device chip comprises an LED or a semiconductor chip. A printed circuit board on which an insulating layer including functional holes penetrating the top and bottom surfaces and a circuit pattern covering the top of the functional holes are formed on the insulating layer; An electronic device chip having an external terminal to be bonded to an upper surface of the circuit pattern; / RTI > Wherein a region of the circuit pattern, which is vertically overlapped with the functional hole, And has a shape corresponding to the welding electrode and protrudes so that the upper surface thereof is in direct contact with the lower surface of the external terminal A printed circuit board having a package for a non-solder type electronic device. The method of claim 7, Wherein the circuit pattern has a single layer or multiple layers of plating layers formed on the circuit pattern surface using any one of Cu, Ni, Pd, Au, Sn, Ag and Co or a binary or ternary alloy thereof. A printed circuit board comprising a package for an electronic device.
KR1020090122474A 2009-12-10 2009-12-10 Non solder bonding method and PCB by the same KR101618878B1 (en)

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KR20110065806A KR20110065806A (en) 2011-06-16
KR101618878B1 true KR101618878B1 (en) 2016-05-10

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102164171B1 (en) 2019-04-26 2020-10-13 (주)엘프스 self-assembled conductive bonding paste for mini LED chip bonding, mini LED chip-circuit board bondig module comprising the same and manufacturing method thereof
KR20200125439A (en) 2019-04-26 2020-11-04 ㈜ 엘프스 self-assembled conductive bonding paste for micro LED chip bonding, mini LED chip-circuit board bondig module comprising the same and manufacturing method thereof
KR102355782B1 (en) 2020-09-25 2022-02-07 (주)엘프스 self-assembled conductive bonding compound for LED chip bonding having excellent adhesion, LED chip-circuit board bonding module comprising the same and manufacturing method thereof
KR102355781B1 (en) 2020-09-25 2022-02-07 (주)엘프스 self-assembled conductive bonding compound for LED chip bonding having excellent self-assembly, LED chip-circuit board bonding module comprising the same and manufacturing method thereof
KR20220041545A (en) 2020-09-25 2022-04-01 ㈜ 엘프스 self-assembled conductive bonding compound for LED chip bonding having excellent electrical properties, LED chip-circuit board bonding module comprising the same and manufacturing method thereof
KR20220041546A (en) 2020-09-25 2022-04-01 ㈜ 엘프스 self-assembled conductive bonding compound for LED chip bonding having excellent printability, LED chip-circuit board bonding module comprising the same and manufacturing method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007335632A (en) 2006-06-15 2007-12-27 Toyota Industries Corp Semiconductor device
JP2008059898A (en) * 2006-08-31 2008-03-13 Diamond Electric Mfg Co Ltd Plating structure of conductive terminal, and ignition device of internal combustion engine using it

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007335632A (en) 2006-06-15 2007-12-27 Toyota Industries Corp Semiconductor device
JP2008059898A (en) * 2006-08-31 2008-03-13 Diamond Electric Mfg Co Ltd Plating structure of conductive terminal, and ignition device of internal combustion engine using it

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102164171B1 (en) 2019-04-26 2020-10-13 (주)엘프스 self-assembled conductive bonding paste for mini LED chip bonding, mini LED chip-circuit board bondig module comprising the same and manufacturing method thereof
KR20200125439A (en) 2019-04-26 2020-11-04 ㈜ 엘프스 self-assembled conductive bonding paste for micro LED chip bonding, mini LED chip-circuit board bondig module comprising the same and manufacturing method thereof
KR102355782B1 (en) 2020-09-25 2022-02-07 (주)엘프스 self-assembled conductive bonding compound for LED chip bonding having excellent adhesion, LED chip-circuit board bonding module comprising the same and manufacturing method thereof
KR102355781B1 (en) 2020-09-25 2022-02-07 (주)엘프스 self-assembled conductive bonding compound for LED chip bonding having excellent self-assembly, LED chip-circuit board bonding module comprising the same and manufacturing method thereof
KR20220041545A (en) 2020-09-25 2022-04-01 ㈜ 엘프스 self-assembled conductive bonding compound for LED chip bonding having excellent electrical properties, LED chip-circuit board bonding module comprising the same and manufacturing method thereof
KR20220041546A (en) 2020-09-25 2022-04-01 ㈜ 엘프스 self-assembled conductive bonding compound for LED chip bonding having excellent printability, LED chip-circuit board bonding module comprising the same and manufacturing method thereof

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Publication number Publication date
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