TWI463585B - Semiconductor package and method thereof - Google Patents
Semiconductor package and method thereof Download PDFInfo
- Publication number
- TWI463585B TWI463585B TW101100127A TW101100127A TWI463585B TW I463585 B TWI463585 B TW I463585B TW 101100127 A TW101100127 A TW 101100127A TW 101100127 A TW101100127 A TW 101100127A TW I463585 B TWI463585 B TW I463585B
- Authority
- TW
- Taiwan
- Prior art keywords
- copper
- semiconductor package
- free
- substrate
- bonding
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Description
本發明係有關於一種半導體封裝方法，特別係有關於一種可防止銅離子游離之半導體封裝方法。
The present invention relates to a semiconductor packaging method, and more particularly to a semiconductor packaging method capable of preventing copper ions from being released.
目前電子產品之體積越來越輕薄，因此相對內部之電路布局必須越來越趨向微細間距發展，但電路間之微細間距容易導致短路之情形發生。
At present, the volume of electronic products is becoming thinner and lighter, so the relative internal circuit layout must be more and more developed toward fine pitch, but the fine pitch between circuits is likely to cause a short circuit.
本發明之主要目的係在於提供一種半導體封裝方法，其包含提供一基板，該基板係具有一上表面及複數個設置於該上表面之連接墊，各該連接墊係具有一第一接合表面；覆晶結合一晶片於該基板，該晶片係具有一主動面及複數個設置於該主動面之含銅凸塊，該主動面係朝向該基板之該上表面且該些含銅凸塊係直接接合於該些連接墊，各該含銅凸塊係具有一第二接合表面及一環壁；以及形成一防游離膠體於該基板及該晶片之間，該防游離膠體係具有複數個防游離材，該些防游離材係包覆該些含銅凸塊之該些環壁。由於該防游離膠體所具有之該些防游離材係包覆該些含銅凸塊，因此當該些含銅凸塊中之銅離子產生游離時，該些防游離材係可即時捕捉游離之銅離子以防止短路之情形發生。
The main purpose of the present invention is to provide a semiconductor package method, comprising: providing a substrate having an upper surface and a plurality of connection pads disposed on the upper surface, each of the connection pads having a first bonding surface; The flip chip is combined with a wafer on the substrate, the wafer has an active surface and a plurality of copper-containing bumps disposed on the active surface, the active surface facing the upper surface of the substrate and the copper-containing bumps are directly Bonding the connection pads, each of the copper-containing bumps has a second bonding surface and a ring wall; and forming an anti-free colloid between the substrate and the wafer, the anti-free glue system having a plurality of anti-free materials The anti-free materials cover the ring walls of the copper-containing bumps. Since the anti-free material has the anti-free material coating the copper-containing bumps, when the copper ions in the copper-containing bumps are free, the anti-free materials can instantly capture the free particles. Copper ions occur to prevent short circuits.
請參閱第1A至1C圖，其係本發明之一較佳實施例，一種半導體封裝方法係包含下列步驟：首先，請參閱第1A圖，提供一基板110，該基板110係具有一上表面111及複數個設置於該上表面111之連接墊112，各該連接墊112係具有一第一接合表面113及一側壁114，在本實施例中，各該連接墊112之該第一接合表面113係具有一第一區113a及一位於第一區113a外側之第二區113b；接著，請參閱第1B圖，覆晶結合一晶片120於該基板110，該晶片120係具有一主動面121及複數個設置於該主動面121之含銅凸塊122，各該含銅凸塊122係具有一第二接合表面122a及一環壁122b，該主動面121係朝向該基板110之該上表面111且該些含銅凸塊122係直接接合於該些連接墊112，在本實施例中，該些含銅凸塊122之材質係選自於銅/鎳或銅/鎳/金其中之一，且各該連接墊112之該第一接合表面113的各該第一區113a係對應於各該含銅凸塊122之該第二接合表面122a，且各該第一接合表面113及各該第二接合表面122a係為共平面；最後，請參閱第1C圖，形成一防游離膠體130於該基板110及該晶片120之間，在本實施例中，該防游離膠體130係更延伸形成於該晶片120之一側面123，該防游離膠體130係具有複數個防游離材131，該些防游離材131係包覆該些含銅凸塊122之該些環壁122b及該些連接墊112之該些側壁114，較佳地，該些防游離材131係更覆蓋該些第一接合表面113之該些第二區113b以形成一半導體封裝結構100，該些防游離材131之材質係為有機保焊劑，且該有機保焊劑之材質係選自於咪唑化合物或咪唑衍生物其中之一，在本實施例中，該咪唑衍生物係可為苯基聯三連唑、苯基咪唑、替代性苯基咪唑或芳香族羥基咪唑或其混合體其中之一，該咪唑化合物可為苯基聯三連唑、苯基咪唑、替代性苯基咪唑或芳香族羥基咪唑或其混合體其中之一。
由於該防游離膠體130所具有之該些防游離材131係包覆該些含銅凸塊122，因此當該些含銅凸塊122中之銅離子產生游離時，該些防游離材131係可即時捕捉游離之銅離子以防止短路之情形發生。
接著，請再參閱第1C圖，其係本發明之一較佳實施例之一種半導體封裝結構100，包含有一基板110、一晶片120以及一防游離膠體130，該基板110係具有一上表面111及複數個設置於該上表面111之連接墊112，各該連接墊112係具有一第一接合表面113及一側壁114，且各該連接墊112之該第一接合表面113係具有一第一區113a及一位於第一區113a外側之第二區113b，該晶片120係覆晶結合於該基板110，該晶片120係具有一主動面121及複數個設置於該主動面121之含銅凸塊122，該主動面121係朝向該基板110之該上表面111且該些含銅凸塊122係直接接合於該些連接墊112，各該含銅凸塊122係具有一第二接合表面122a及一環壁122b，各該連接墊112之該第一接合表面113的各該第一區113a係對應於各該含銅凸塊122之該第二接合表面122a，且各該第一接合表面113及各該第二接合表面122a係為共平面，該防游離膠體130係形成於該基板110及該晶片120之間，且該防游離膠體130係更延伸形成於該晶片120之一側面123，該防游離膠體130係具有複數個防游離材131，該些防游離材131係包覆該些含銅凸塊122之該些環壁122b及該些連接墊112之該些側壁114，且該些防游離材131係更覆蓋該些連接墊112之該些第一接合表面113的該些第二區113b。
本發明之保護範圍當視後附之申請專利範圍所界定者為準，任何熟知此項技藝者，在不脫離本發明之精神和範圍內所作之任何變化與修改，均屬於本發明之保護範圍。
Referring to FIGS. 1A to 1C, which are a preferred embodiment of the present invention, a semiconductor package method includes the following steps: First, referring to FIG. 1A, a substrate 110 having an upper surface 111 is provided. And a plurality of connection pads 112 disposed on the upper surface 111. Each of the connection pads 112 has a first bonding surface 113 and a sidewall 114. In this embodiment, the first bonding surface 113 of each of the connection pads 112 The first region 113a and the second region 113b located outside the first region 113a; then, referring to FIG. 1B, the wafer 120 is bonded to the substrate 110, and the wafer 120 has an active surface 121 and a plurality of copper-containing bumps 122 disposed on the active surface 121, each of the copper-containing bumps 122 having a second bonding surface 122a and a ring wall 122b facing the upper surface 111 of the substrate 110 and The copper-containing bumps 122 are directly bonded to the connection pads 112. In this embodiment, the copper-containing bumps 122 are selected from one of copper/nickel or copper/nickel/gold. Each of the first regions 113a of the first joint surface 113 of each of the connection pads 112 corresponds to The second bonding surface 122a of each of the copper-containing bumps 122, and each of the first bonding surface 113 and each of the second bonding surfaces 122a are coplanar; finally, please refer to FIG. 1C to form an anti-free colloid 130. Between the substrate 110 and the wafer 120, in the embodiment, the anti-free colloid 130 is further extended on one side 123 of the wafer 120, and the anti-free colloid 130 has a plurality of anti-free materials 131. The anti-free material 131 covers the ring walls 122b of the copper-containing bumps 122 and the sidewalls 114 of the connecting pads 112. Preferably, the anti-free materials 131 cover the first portions. The second regions 113b of the bonding surface 113 are formed to form a semiconductor package structure 100. The materials of the anti-free materials 131 are organic solder resists, and the material of the organic solder resist is selected from an imidazole compound or an imidazole derivative. In one embodiment, the imidazole derivative may be one of phenyl bis-triazole, phenylimidazole, substituted phenylimidazole or aromatic hydroxyimidazole or a mixture thereof, and the imidazole compound may be Phenyl bis-triazole, phenylimidazole, alternative phenyl One of imidazole or aromatic hydroxyimidazole or a mixture thereof.
Since the anti-free material 131 of the anti-free colloid 130 covers the copper-containing bumps 122, when the copper ions in the copper-containing bumps 122 are free, the anti-free materials 131 are Instantly capture free copper ions to prevent short circuits.
Next, referring to FIG. 1C, a semiconductor package structure 100 according to a preferred embodiment of the present invention includes a substrate 110, a wafer 120, and an anti-free colloid 130 having an upper surface 111. And a plurality of connection pads 112 disposed on the upper surface 111, each of the connection pads 112 has a first bonding surface 113 and a sidewall 114, and the first bonding surface 113 of each of the connection pads 112 has a first The substrate 113a and the second region 113b located outside the first region 113a are bonded to the substrate 110. The wafer 120 has an active surface 121 and a plurality of copper bumps disposed on the active surface 121. In the block 122, the active surface 121 faces the upper surface 111 of the substrate 110, and the copper-containing bumps 122 are directly bonded to the connecting pads 112. Each of the copper-containing bumps 122 has a second bonding surface 122a. Each of the first regions 113a of the first bonding surface 113 of each of the connection pads 112 corresponds to the second bonding surface 122a of each of the copper-containing bumps 122, and each of the first bonding surfaces 113 And each of the second joint surfaces 122a is coplanar, the anti-tour The anti-free colloid 130 is formed on the side surface 123 of the wafer 120, and the anti-free colloid 130 is formed on the side surface 123 of the wafer 120. The anti-free colloid 130 has a plurality of anti-free materials 131. The anti-free material 131 covers the ring walls 122b of the copper-containing bumps 122 and the sidewalls 114 of the connection pads 112, and the anti-free material 131 further covers the connection pads 112. The second regions 113b of the first bonding surfaces 113.
The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .
100．．．半導體封裝結構100. . . Semiconductor package structure
110．．．基板110. . . Substrate
111．．．上表面111. . . Upper surface
112．．．連接墊112. . . Connection pad
113．．．第一接合表面113. . . First joint surface
113a．．．第一區113a. . . First district
113b．．．第二區113b. . . Second district
114．．．側壁114. . . Side wall
120．．．晶片120. . . Wafer
121．．．主動面121. . . Active surface
122．．．含銅凸塊122. . . Copper bump
122a．．．第二接合表面122a. . . Second joint surface
122b．．．環壁122b. . . Ring wall
123．．．側面123. . . side
130．．．防游離膠體130. . . Anti-free colloid
131．．．防游離材131. . . Anti-free material
第1A至1C圖：依據本發明之一較佳實施例，一種半導體封裝方法之截面示意圖。
1A to 1C are schematic cross-sectional views showing a semiconductor package method in accordance with a preferred embodiment of the present invention.
100．．．半導體封裝結構100. . . Semiconductor package structure
110．．．基板110. . . Substrate
111．．．上表面111. . . Upper surface
113．．．第一接合表面113. . . First joint surface
113a．．．第一區113a. . . First district
113b．．．第二區113b. . . Second district
114．．．側壁114. . . Side wall
120．．．晶片120. . . Wafer
121．．．主動面121. . . Active surface
122．．．含銅凸塊122. . . Copper bump
122a．．．第二接合表面122a. . . Second joint surface
122b．．．環壁122b. . . Ring wall
123．．．側面123. . . side
130．．．防游離膠體130. . . Anti-free colloid
131．．．防游離材131. . . Anti-free material
Claims (18)
提供一基板，該基板係具有一上表面及複數個設置於該上表面之連接墊，各該連接墊係具有一第一接合表面；
覆晶結合一晶片於該基板，該晶片係具有一主動面及複數個設置於該主動面之含銅凸塊，該主動面係朝向該基板之該上表面且該些含銅凸塊係直接接合於該些連接墊，各該含銅凸塊係具有一第二接合表面及一環壁；以及
形成一防游離膠體於該基板及該晶片之間，該防游離膠體係具有複數個防游離材，該些防游離材係包覆該些含銅凸塊之該些環壁。A semiconductor packaging method comprising at least:
Providing a substrate having an upper surface and a plurality of connecting pads disposed on the upper surface, each of the connecting pads having a first bonding surface;
The flip chip is combined with a wafer on the substrate, the wafer has an active surface and a plurality of copper-containing bumps disposed on the active surface, the active surface facing the upper surface of the substrate and the copper-containing bumps are directly Bonding the connection pads, each of the copper-containing bumps has a second bonding surface and a ring wall; and forming an anti-free colloid between the substrate and the wafer, the anti-free glue system having a plurality of anti-free materials The anti-free materials cover the ring walls of the copper-containing bumps.
一基板，其係具有一上表面及複數個設置於該上表面之連接墊，各該連接墊係具有一第一接合表面；
一晶片，其係覆晶結合於該基板，該晶片係具有一主動面及複數個設置於該主動面之含銅凸塊，該主動面係朝向該基板之該上表面且該些含銅凸塊係直接接合於該些連接墊，各該含銅凸塊係具有一第二接合表面及一環壁；以及
一防游離膠體，其係形成於該基板及該晶片之間，該防游離膠體係具有複數個防游離材，該些防游離材係包覆該些含銅凸塊之該些環壁。A semiconductor package structure comprising at least:
a substrate having an upper surface and a plurality of connecting pads disposed on the upper surface, each of the connecting pads having a first bonding surface;
a wafer bonded to the substrate, the wafer having an active surface and a plurality of copper bumps disposed on the active surface, the active surface facing the upper surface of the substrate and the copper-containing bumps The block is directly bonded to the connection pads, each of the copper-containing bumps has a second bonding surface and a ring wall; and an anti-free gel is formed between the substrate and the wafer, the anti-free glue system The utility model has a plurality of anti-free materials, and the anti-free materials cover the ring walls of the copper-containing bumps.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101100127A TWI463585B (en) | 2012-01-03 | 2012-01-03 | Semiconductor package and method thereof |
| JP2012138154A JP2013140936A (en) | 2012-01-03 | 2012-06-19 | Semiconductor package manufacturing method and semiconductor package |
| KR1020120083792A KR101419329B1 (en) | 2012-01-03 | 2012-07-31 | Semiconductor packaging method and semiconductor package structure |
| SG2012069548A SG191463A1 (en) | 2012-01-03 | 2012-09-19 | Semiconductor packaging method and structure thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101100127A TWI463585B (en) | 2012-01-03 | 2012-01-03 | Semiconductor package and method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201330125A TW201330125A (en) | 2013-07-16 |
| TWI463585B true TWI463585B (en) | 2014-12-01 |
Family
ID=48992266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW101100127A TWI463585B (en) | 2012-01-03 | 2012-01-03 | Semiconductor package and method thereof |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP2013140936A (en) |
| KR (1) | KR101419329B1 (en) |
| SG (1) | SG191463A1 (en) |
| TW (1) | TWI463585B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200640030A (en) * | 2005-05-05 | 2006-11-16 | Po-Chien Li | Bump structure of LED plip chip |
| TW200812027A (en) * | 2006-08-22 | 2008-03-01 | Int Semiconductor Tech Ltd | Flip-chip attach structure and method |
| TW201005814A (en) * | 2008-05-16 | 2010-02-01 | Sumitomo Bakelite Co | Method for manufacturing semiconductor device and semiconductor device |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3633422B2 (en) * | 2000-02-22 | 2005-03-30 | ソニーケミカル株式会社 | Connecting material |
| JP4993880B2 (en) * | 2005-07-06 | 2012-08-08 | 旭化成イーマテリアルズ株式会社 | Anisotropic conductive adhesive sheet and finely connected structure |
| KR101116167B1 (en) * | 2007-10-29 | 2012-03-06 | 한양대학교 산학협력단 | Metal composite bump formation and bonding processing the same |
| JPWO2009122867A1 (en) * | 2008-03-31 | 2011-07-28 | 日本電気株式会社 | Semiconductor device, composite circuit device and manufacturing method thereof |
| WO2010013728A1 (en) * | 2008-07-31 | 2010-02-04 | 日本電気株式会社 | Semiconductor device and method for manufacturing same |
| JP5296116B2 (en) * | 2011-02-16 | 2013-09-25 | シャープ株式会社 | Semiconductor device |
| JP2012212864A (en) * | 2011-03-18 | 2012-11-01 | Sekisui Chem Co Ltd | Manufacturing method of connection structure and connection structure |
| TWM428492U (en) * | 2012-01-03 | 2012-05-01 | Chipbond Technology Corp | Semiconductor packaging structure |
-
2012
- 2012-01-03 TW TW101100127A patent/TWI463585B/en active
- 2012-06-19 JP JP2012138154A patent/JP2013140936A/en active Pending
- 2012-07-31 KR KR1020120083792A patent/KR101419329B1/en active IP Right Grant
- 2012-09-19 SG SG2012069548A patent/SG191463A1/en unknown
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200640030A (en) * | 2005-05-05 | 2006-11-16 | Po-Chien Li | Bump structure of LED plip chip |
| TW200812027A (en) * | 2006-08-22 | 2008-03-01 | Int Semiconductor Tech Ltd | Flip-chip attach structure and method |
| TW201005814A (en) * | 2008-05-16 | 2010-02-01 | Sumitomo Bakelite Co | Method for manufacturing semiconductor device and semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20130079980A (en) | 2013-07-11 |
| KR101419329B1 (en) | 2014-07-14 |
| SG191463A1 (en) | 2013-07-31 |
| JP2013140936A (en) | 2013-07-18 |
| TW201330125A (en) | 2013-07-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI587412B (en) | Package structures and methods for fabricating the same | |
| TWI469283B (en) | Package structure and package process | |
| TWI506743B (en) | Thermal management structure of semiconduvtor device and methods for forming the same | |
| TWI418003B (en) | Package structure having embedded electronic component and fabrication method thereof | |
| US8803323B2 (en) | Package structures and methods for forming the same | |
| US8963299B2 (en) | Semiconductor package and fabrication method thereof | |
| TW200416787A (en) | Semiconductor stacked multi-package module having inverted second package | |
| TWI611542B (en) | Electronic package structure and the manufacture thereof | |
| US11756844B2 (en) | Semiconductor device with a protection mechanism and associated systems, devices, and methods | |
| TWI416700B (en) | Chip-stacked package structure and method for manufacturing the same | |
| TWI469310B (en) | Flip-chip stacked package structure and its package methodfabrication method of a photonic crystal structure | |
| TWI529876B (en) | Package on package structure and manufacturing method thereof | |
| TW201508895A (en) | Package module with offset stack components | |
| KR101450761B1 (en) | A semiconductor package, stacked semiconductor package and manufacturing method thereof | |
| TWI463585B (en) | Semiconductor package and method thereof | |
| TWI508197B (en) | Semiconductor package and manufacturing method thereof | |
| TWI604593B (en) | Semiconductor package and method of manufacture | |
| TWI435667B (en) | Print circuit board assembly | |
| JP3178121U (en) | Semiconductor package | |
| TWI381512B (en) | Multi-chip stack structure | |
| TWI491014B (en) | Method of forming semiconductor stack unit and semiconductor package | |
| TWI447869B (en) | Chip stacked package structure and applications thereof | |
| TWI380417B (en) | Thin type multi-chip package | |
| TWI534978B (en) | Chip package structure | |
| KR20150056406A (en) | Semi-conductor flip-chip package |