JP2013140936A - Semiconductor package manufacturing method and semiconductor package - Google Patents

Semiconductor package manufacturing method and semiconductor package Download PDF

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JP2013140936A
JP2013140936A JP2012138154A JP2012138154A JP2013140936A JP 2013140936 A JP2013140936 A JP 2013140936A JP 2012138154 A JP2012138154 A JP 2012138154A JP 2012138154 A JP2012138154 A JP 2012138154A JP 2013140936 A JP2013140936 A JP 2013140936A
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copper
semiconductor package
package according
chip
bonding surface
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Cheng-Hung Shii
政宏 施
su-zhen Lin
淑真 林
Zheng Fan Lin
政帆 林
yong wei Xie
永偉 謝
Ming Yi Liu
明益 劉
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Chipbond Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package manufacturing method capable of preventing liberation of a copper ion.SOLUTION: A semiconductor package manufacturing method comprises: providing a substrate 110 which includes an upper surface 111, and a plurality of conductive pads 112 provided on the upper surface 111 and each having a first junction surface 113 and lateral walls 113; and flip-chip bonding a chip 120 to the substrate 110. The chip 120 has a principal surface 121 and a plurality of copper-containing bumps 122 provided on the principal surface. The copper-containing bump 122 has a second junction surface 122a and an annular surface 122b. The semiconductor package manufacturing method further comprises: providing anti-liberation colloids 130 between the substrate 110 and the chip 120. A plurality of anti-liberation materials included in the anti-liberation colloids 130 coat the annular surfaces 122b of the plurality copper-containing bumps 122 and the lateral walls 114 of the conductive pads 112. Because of this, when the copper ions in the copper-containing bump 122 are liberated, the anti-liberation materials 131 trap the liberated copper ions thereby to prevent a short-circuit.

Description

本発明は半導体パッケージの製造方法に関し、より詳しくは、銅イオンの遊離を防止可能な半導体パッケージの製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor package, and more particularly to a method for manufacturing a semiconductor package capable of preventing the liberation of copper ions.

近年、電子製品の体積が軽薄短小となる趨勢にあることから、電子製品内部の回路のレイアウトの間隔もますます小さくなる傾向にある。   In recent years, the volume of electronic products tends to be light, thin, and short, and therefore, the circuit layout interval inside the electronic products tends to become smaller and smaller.

特開平０７−１４７３７１号公報JP 07-147371 A

しかしながら、前述した従来の技術では、電気回路間の微細な間隔は容易に短絡を引き起こすといった問題があった。   However, the above-described conventional technique has a problem that a fine interval between electric circuits easily causes a short circuit.

本発明は、このような従来の問題に鑑みてなされたものである。本発明の目的は、銅イオンの遊離を防止可能な半導体パッケージの製造方法を提供することにある。   The present invention has been made in view of such conventional problems. An object of the present invention is to provide a method for manufacturing a semiconductor package capable of preventing the liberation of copper ions.

本発明の半導体パッケージの製造方法は、上表面及び上表面上に設けられるとともにそれぞれ第１接合表面を有する複数の導電パッドを含む基板を提供するステップと、チップを基板にフリップチップ結合させるステップと、複数の銅含有バンプの複数の環状の表面を覆う遊離防止材を有する複数の遊離防止コロイドを基板及びチップの間に形成させるステップと、を含む。チップは、主面及び主面に設けられる複数の銅含有バンプを有し、主面は基板の上表面側に向き、複数の銅含有バンプは直接複数の導電パッドに接合され、それぞれの銅含有バンプは第２接合表面及び環状の表面を具備することを特徴とする。   A method of manufacturing a semiconductor package according to the present invention includes providing a substrate including a plurality of conductive pads provided on an upper surface and each having a first bonding surface, and flip-chip bonding the chip to the substrate. Forming a plurality of release preventing colloids between the substrate and the chip having an release preventing material covering the plurality of annular surfaces of the plurality of copper-containing bumps. The chip has a main surface and a plurality of copper-containing bumps provided on the main surface, the main surface faces the upper surface side of the substrate, the plurality of copper-containing bumps are directly bonded to a plurality of conductive pads, and each copper-containing bump The bump has a second bonding surface and an annular surface.

遊離防止コロイドが有する遊離防止材は、複数の銅含有バンプを覆うため、銅含有バンプ中の銅イオンの遊離が発生するとき、遊離防止材は遊離した銅イオンを捕捉し、短絡の発生を防止できる。   The release prevention material of the release prevention colloid covers multiple copper-containing bumps, so when release of copper ions in the copper-containing bump occurs, the release prevention material captures the released copper ions and prevents the occurrence of short circuits. it can.

本発明によれば、銅イオンの遊離を防止可能な半導体パッケージの製造方法が得られる。   ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor package which can prevent liberation of copper ion is obtained.

本発明の一実施形態に係る半導体パッケージの製造方法を説明する断面概略図である。It is a cross-sectional schematic diagram explaining the manufacturing method of the semiconductor package which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体パッケージの製造方法を説明する断面概略図である。It is a cross-sectional schematic diagram explaining the manufacturing method of the semiconductor package which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体パッケージの製造方法を説明する断面概略図である。It is a cross-sectional schematic diagram explaining the manufacturing method of the semiconductor package which concerns on one Embodiment of this invention.

以下、図面を参照して、本発明を実施するための形態について、詳細に説明する。なお、本発明は、以下に説明する実施形態に限定されるものではない。   DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments described below.

（一実施形態）
本発明の一実施形態に係る半導体パッケージの製造方法を図１Ａから図１Ｃに示す。 (One embodiment)
A method of manufacturing a semiconductor package according to an embodiment of the present invention is shown in FIGS. 1A to 1C.

まず、図１Ａに示すように、基板１１０を提供する。基板１１０は、上表面１１１及び上表面１１１に設けられる複数の導電パッド１１２を有し、それぞれの導電パッド１１２は、第１接合表面１１３及び側壁１１４を有する。本実施形態では、それぞれの導電パッド１１２の第１接合表面１１３は、第１領域１１３ａ及び第１領域１１３ａの外側に位置する第２領域１１３ｂを有する。   First, as shown in FIG. 1A, a substrate 110 is provided. The substrate 110 has an upper surface 111 and a plurality of conductive pads 112 provided on the upper surface 111, and each conductive pad 112 has a first bonding surface 113 and a side wall 114. In the present embodiment, the first bonding surface 113 of each conductive pad 112 has a first region 113a and a second region 113b located outside the first region 113a.

次に、図１Ｂに示すように、チップ１２０を基板１１０にフリップチップ結合により実装する。チップ１２０は、主面１２１及び複数の主面１２１に設けられる銅含有バンプ１２２を有し、銅含有バンプ１２２は、第２接合表面１２２ａ及び環状の表面１２２ｂを有する。主面１２１は、基板１１０の上表面１１１側に向いており、複数の銅含有バンプ１２２は、複数の導電パッド１１２に直接接合される。本実施形態では、複数の銅含有バンプ１２２を形成する材料は、銅／ニッケル、銅／ニッケル／金のうちのいずれか１つが選ばれる。それぞれの導電パッド１１２の第１接合表面１１３の第１領域１１３ａは、それぞれの銅含有バンプ１２２の第２接合表面１２２ａと対応する。また、第１接合表面１１３及び第２接合表面１２２ａは平面である。   Next, as shown in FIG. 1B, the chip 120 is mounted on the substrate 110 by flip chip bonding. The chip 120 includes a main surface 121 and a copper-containing bump 122 provided on the plurality of main surfaces 121, and the copper-containing bump 122 has a second bonding surface 122a and an annular surface 122b. The main surface 121 faces the upper surface 111 side of the substrate 110, and the plurality of copper-containing bumps 122 are directly bonded to the plurality of conductive pads 112. In the present embodiment, as the material for forming the plurality of copper-containing bumps 122, any one of copper / nickel and copper / nickel / gold is selected. The first region 113 a of the first bonding surface 113 of each conductive pad 112 corresponds to the second bonding surface 122 a of each copper-containing bump 122. The first bonding surface 113 and the second bonding surface 122a are flat.

最後に、図１Ｃに示すように、遊離防止コロイド１３０を基板１１０及びチップ１２０の間に設ける。本実施形態では、遊離防止コロイド１３０は、チップ１２０の側面１２３に延びるように形成される。遊離防止コロイド１３０が有する複数の遊離防止材１３１は、複数の銅含有バンプ１２２の環状の表面１２２ｂ及び導電パッド１１２の側壁１１４を覆う。より好ましくは、複数の遊離防止材１３１は、複数の第１接合表面１１３の第２領域１１３ｂを覆い半導体パッケージ１００を形成する。   Finally, as shown in FIG. 1C, an anti-release colloid 130 is provided between the substrate 110 and the chip 120. In this embodiment, the release preventing colloid 130 is formed to extend to the side surface 123 of the chip 120. The plurality of release preventing materials 131 included in the release preventing colloid 130 cover the annular surfaces 122 b of the plurality of copper-containing bumps 122 and the side walls 114 of the conductive pads 112. More preferably, the plurality of release preventing materials 131 cover the second regions 113 b of the plurality of first bonding surfaces 113 to form the semiconductor package 100.

複数の遊離防止材１３１はプリフラックスであり、プリフラックスの材料は、ベンズイミダゾール類、またはイミダゾール類のうちのいずれか１つである。本実施形態では、イミダゾール類として、ベンゾトリアゾール、フェニルイミダゾール、置換フェニルイミダゾール、アリールフェニルイミダゾール、またはこれらの混合体のうちのいずれか１つであり、ベンズイミダゾール類としては、ベンゾトリアゾール、フェニルイミダゾール、置換フェニルイミダゾール、アリールフェニルイミダゾール、またはこれらの混合体のうちのいずれか１つである。   The plurality of release preventing materials 131 are preflux, and the material of the preflux is any one of benzimidazoles and imidazoles. In the present embodiment, the imidazole is any one of benzotriazole, phenylimidazole, substituted phenylimidazole, arylphenylimidazole, or a mixture thereof, and the benzimidazoles are benzotriazole, phenylimidazole, Any one of substituted phenylimidazole, arylphenylimidazole, or a mixture thereof.

遊離防止コロイド１３０が有する複数の遊離防止材１３１は複数の銅含有バンプ１２２を覆うため、複数の銅含有バンプ１２２中の銅イオンの遊離が発生するとき、複数の遊離防止材１３１は遊離した銅イオンを捕捉し、短絡の発生を防止できる。   Since the plurality of release preventing materials 131 included in the release preventing colloid 130 cover the plurality of copper-containing bumps 122, when release of copper ions in the plurality of copper-containing bumps 122 occurs, the plurality of release preventing materials 131 are separated from the released copper. Ions can be captured and short circuit can be prevented.

図１Ｃに示す半導体パッケージ１００は、基板１１０、チップ１２０及び遊離防止コロイド１３０を含む。基板１１０は、上表面１１１及び複数の上表面１１１に設けられる導電パッド１１２を有する。それぞれの導電パッド１１２は第１接合表面１１３及び側壁１１４を有し、それぞれの導電パッド１１２の第１接合表面１１３は第１領域１１３ａ及び第１領域１１３ａの外側に位置する第２領域１１３ｂを有する。   A semiconductor package 100 shown in FIG. 1C includes a substrate 110, a chip 120, and a release preventing colloid 130. The substrate 110 has an upper surface 111 and a plurality of conductive pads 112 provided on the upper surface 111. Each conductive pad 112 has a first bonding surface 113 and a sidewall 114, and the first bonding surface 113 of each conductive pad 112 has a first region 113a and a second region 113b located outside the first region 113a. .

チップ１２０は、基板１１０にフリップチップ結合されるとともに、主面１２１及び主面１２１に設けられる複数の銅含有バンプ１２２を有する。主面１２１は、基板１１０の上表面１１１側に向いており、複数の銅含有バンプ１２２は複数の導電パッド１１２に直接接合される。それぞれの銅含有バンプ１２２は、第２接合表面１２２ａ及び環状の表面１２２ｂを有し、それぞれの導電パッド１１２の第１接合表面１１３の第１領域１１３ａはそれぞれの銅含有バンプ１２２の第２接合表面１２２ａに対応する。第１接合表面１１３及び第２接合表面１２２ａはどれも平面である。   The chip 120 is flip-chip bonded to the substrate 110 and has a main surface 121 and a plurality of copper-containing bumps 122 provided on the main surface 121. The main surface 121 faces the upper surface 111 side of the substrate 110, and the plurality of copper-containing bumps 122 are directly bonded to the plurality of conductive pads 112. Each copper-containing bump 122 has a second bonding surface 122 a and an annular surface 122 b, and the first region 113 a of the first bonding surface 113 of each conductive pad 112 is the second bonding surface of each copper-containing bump 122. 122a. The first bonding surface 113 and the second bonding surface 122a are both flat.

遊離防止コロイド１３０は、基板１１０及びチップ１２０の間に設けられるとともに、チップ１２０の側面１２３に延びるように形成される。遊離防止コロイド１３０が有する複数の遊離防止材１３１は、複数の銅含有バンプ１２２の環状の表面１２２ｂ及び導電パッド１１２の側壁１１４を覆うとともに、複数の導電パッド１１２の第１接合表面１１３の第２領域１１３ｂを覆う。   The release preventing colloid 130 is provided between the substrate 110 and the chip 120, and is formed to extend to the side surface 123 of the chip 120. The plurality of release preventing materials 131 included in the release preventing colloid 130 cover the annular surfaces 122b of the plurality of copper-containing bumps 122 and the side walls 114 of the conductive pads 112, and the second of the first bonding surfaces 113 of the plurality of conductive pads 112. The region 113b is covered.

上述の実施形態は、本発明の技術思想及び特徴を説明するためのものにすぎず、当該技術分野を熟知する者に本発明の内容を理解させるとともにこれをもって実施させることを目的とし、本発明の特許請求の範囲を限定するものではない。従って、本発明の精神を逸脱せずに行う各種の同様の効果を有する改良、または変更は、特許請求の範囲に記載の内容に含まれるものとする。   The above-described embodiments are merely for explaining the technical idea and features of the present invention, and are intended to allow those skilled in the art to understand the contents of the present invention and to carry out the same with the present invention. It is not intended to limit the scope of the claims. Accordingly, improvements or modifications having various similar effects made without departing from the spirit of the present invention are intended to be included in the contents of the claims.

１００：半導体パッケージ、１１０：基板、１１１：上表面、１１２：導電パッド、１１３：第１接合表面、１１３ａ：第１領域、１１３ｂ：第２領域、１１４：側壁、１２０：チップ、１２１：：主面、１２２：銅含有バンプ、１２２ａ：第２接合表面、１２２ｂ：環状の表面、１２３：側面、１３０：遊離防止コロイド、１３１：遊離防止材。   100: Semiconductor package, 110: Substrate, 111: Upper surface, 112: Conductive pad, 113: First bonding surface, 113a: First region, 113b: Second region, 114: Side wall, 120: Chip, 121 :: Main Surface, 122: copper-containing bump, 122a: second bonding surface, 122b: annular surface, 123: side surface, 130: release prevention colloid, 131: release prevention material.

Claims (18)

上表面及び前記上表面上に設けられるとともにそれぞれ第１接合表面を有する複数の導電パッドを含む基板を提供するステップと、
チップを前記基板にフリップチップ結合させるステップと、
複数の銅含有バンプの環状の表面を覆う複数の遊離防止材を有する遊離防止コロイドを前記基板及び前記チップの間に形成させるステップと、
を含み、
前記チップは主面及び前記主面上に設けられる複数の前記銅含有バンプを有し、前記主面は前記基板の前記上表面側に向き、かつ複数の前記銅含有バンプは直接複数の前記導電パッドに接合され、前記銅含有バンプは第２接合表面及び環状の表面を具備することを特徴とする半導体パッケージの製造方法。 Providing a substrate including a top surface and a plurality of conductive pads provided on the top surface and each having a first bonding surface;
Flip chip bonding the chip to the substrate;
Forming a release preventing colloid having a plurality of release preventing materials covering an annular surface of the plurality of copper-containing bumps between the substrate and the chip;
Including
The chip has a main surface and a plurality of the copper-containing bumps provided on the main surface, the main surface is directed to the upper surface side of the substrate, and the plurality of copper-containing bumps are directly connected to the plurality of the conductive layers. A method of manufacturing a semiconductor package, wherein the copper-containing bump is bonded to a pad, and the copper-containing bump has a second bonding surface and an annular surface. 前記第１接合表面及び前記第２接合表面の形状は、平面であることを特徴とする請求項１に記載の半導体パッケージの製造方法。   The method of manufacturing a semiconductor package according to claim 1, wherein shapes of the first bonding surface and the second bonding surface are flat surfaces. 前記導電パッドは、側壁を有し、前記複数の遊離防止材は前記側壁を覆うことを特徴とする請求項１に記載の半導体パッケージの製造方法。   The method of manufacturing a semiconductor package according to claim 1, wherein the conductive pad has a side wall, and the plurality of release preventing materials cover the side wall. 前記導電パッドの前記第１接合表面は、第１領域及び前記第１領域の外側に位置する第２領域を有し、前記第１領域は前記銅含有バンプの前記第２接合表面に対応する位置に形成されることを特徴とする請求項１に記載の半導体パッケージの製造方法。   The first bonding surface of the conductive pad has a first region and a second region located outside the first region, and the first region corresponds to the second bonding surface of the copper-containing bump. The method of manufacturing a semiconductor package according to claim 1, wherein the semiconductor package is formed as follows. 前記遊離防止材は、前記第１接合表面の前記第２領域を覆うことを特徴とする請求項４に記載の半導体パッケージの製造方法。   The method of manufacturing a semiconductor package according to claim 4, wherein the release preventing material covers the second region of the first bonding surface. 前記遊離防止材は、プリフラックスであることを特徴とする請求項１に記載の半導体パッケージの製造方法。   The method of manufacturing a semiconductor package according to claim 1, wherein the release preventing material is a preflux. 前記プリフラックスは、ベンズイミダゾール類、またはイミダゾール類のうちのいずれか１つであることを特徴とする請求項６に記載の半導体パッケージの製造方法。   The method of manufacturing a semiconductor package according to claim 6, wherein the preflux is any one of benzimidazoles and imidazoles. 前記イミダゾール類は、ベンゾトリアゾール、フェニルイミダゾール、置換フェニルイミダゾール、アリールフェニルイミダゾール、またはこれらの混合体のうちのいずれか１つであり、前記ベンズイミダゾール類はベンゾトリアゾール、フェニルイミダゾール、置換フェニルイミダゾール、アリールフェニルイミダゾール、またはこれらの混合体のうちのいずれか１つであることを特徴とする請求項７に記載の半導体パッケージの製造方法。   The imidazole is any one of benzotriazole, phenylimidazole, substituted phenylimidazole, arylphenylimidazole, or a mixture thereof, and the benzimidazoles are benzotriazole, phenylimidazole, substituted phenylimidazole, aryl The method for manufacturing a semiconductor package according to claim 7, wherein the method is any one of phenylimidazole and a mixture thereof. 前記銅含有バンプは、銅／ニッケル、または銅／ニッケル／金のうちのいずれか１つから形成されることを特徴とする請求項１に記載の半導体パッケージの製造方法。   The method of manufacturing a semiconductor package according to claim 1, wherein the copper-containing bump is formed of any one of copper / nickel or copper / nickel / gold. 上表面及び前記上表面に設けられるとともにそれぞれ第１接合表面を有する複数の導電パッドを含む基板と、
前記基板にフリップチップ結合されるチップと、
前記基板及び前記チップの間に形成されるとともに銅含有バンプの環状の表面を覆う複数の遊離防止材を有する遊離防止コロイドと、
を含み、
前記チップは、主面及び前記主面上に設けられる複数の前記銅含有バンプを有し、前記主面は前記基板の前記上表面側に向き、かつ前記銅含有バンプは直接前記導電パッドに接合し、前記銅含有バンプは第２接合表面及び環状の表面を具備することを特徴とする半導体パッケージ。 A substrate including a plurality of conductive pads provided on the upper surface and the upper surface and each having a first bonding surface;
A chip flip-chip bonded to the substrate;
A release prevention colloid having a plurality of release prevention materials formed between the substrate and the chip and covering an annular surface of the copper-containing bump;
Including
The chip has a main surface and a plurality of the copper-containing bumps provided on the main surface, the main surface faces the upper surface side of the substrate, and the copper-containing bump is directly bonded to the conductive pad. The copper-containing bump has a second bonding surface and an annular surface. 前記第１接合表面及び前記第２接合表面の形状は、平面であることを特徴とする請求項１０に記載の半導体パッケージ。   The semiconductor package according to claim 10, wherein the first bonding surface and the second bonding surface are flat. 前記導電パッドは側壁を有し、前記遊離防止材は前記側壁を覆うことを特徴とする請求項１０に記載の半導体パッケージ。   The semiconductor package according to claim 10, wherein the conductive pad has a side wall, and the release preventing material covers the side wall. 前記導電パッドの前記第１接合表面は、第１領域及び前記第１領域の外側に位置する第２領域を有し、前記第１領域は前記銅含有バンプの前記第２接合表面に対応する位置に形成されることを特徴とする請求項１０に記載の半導体パッケージ。   The first bonding surface of the conductive pad has a first region and a second region located outside the first region, and the first region corresponds to the second bonding surface of the copper-containing bump. The semiconductor package according to claim 10, wherein the semiconductor package is formed. 前記遊離防止材は、前記第１接合表面の前記第２領域を覆うことを特徴とする請求項１３に記載の半導体パッケージ。   The semiconductor package according to claim 13, wherein the release preventing material covers the second region of the first bonding surface. 前記遊離防止材は、プリフラックスであることを特徴とする請求項１０に記載の半導体パッケージ。   The semiconductor package according to claim 10, wherein the release preventing material is a preflux. 前記プリフラックスは、ベンズイミダゾール類かイミダゾール類のうちのいずれか１つであることを特徴とする請求項１５に記載の半導体パッケージ。   The semiconductor package according to claim 15, wherein the preflux is any one of benzimidazoles and imidazoles. 前記イミダゾール類は、ベンゾトリアゾール、フェニルイミダゾール、置換フェニルイミダゾール、アリールフェニルイミダゾール、またはこれらの混合体のうちのいずれか１つであり、前記ベンズイミダゾール類は、ベンゾトリアゾール、フェニルイミダゾール、置換フェニルイミダゾール、アリールフェニルイミダゾール、またはこれらの混合体のうちのいずれか１つであることを特徴とする請求項１６に記載の半導体パッケージ。   The imidazole is any one of benzotriazole, phenylimidazole, substituted phenylimidazole, arylphenylimidazole, or a mixture thereof, and the benzimidazoles are benzotriazole, phenylimidazole, substituted phenylimidazole, The semiconductor package according to claim 16, wherein the package is any one of arylphenylimidazole or a mixture thereof. 前記銅含有バンプは、銅／ニッケル、または銅／ニッケル／金のうちのいずれか１つで形成されることを特徴とする請求項１０に記載の半導体パッケージ。   The semiconductor package according to claim 10, wherein the copper-containing bump is formed of any one of copper / nickel or copper / nickel / gold.
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