TWI248221B - Bump structure of LED flip chip - Google Patents

Bump structure of LED flip chip Download PDF

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Publication number
TWI248221B
TWI248221B TW094114531A TW94114531A TWI248221B TW I248221 B TWI248221 B TW I248221B TW 094114531 A TW094114531 A TW 094114531A TW 94114531 A TW94114531 A TW 94114531A TW I248221 B TWI248221 B TW I248221B
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Taiwan
Prior art keywords
flip chip
led flip
solder
bump
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TW094114531A
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Chinese (zh)
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TW200640030A (en
Inventor
Po-Chien Li
Ming-Kuo Wei
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Po-Chien Li
Ming-Kuo Wei
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Priority to TW094114531A priority Critical patent/TWI248221B/en
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Publication of TW200640030A publication Critical patent/TW200640030A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/06102—Disposition the bonding areas being at different heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Led Device Packages (AREA)
  • Wire Bonding (AREA)

Abstract

A bump structure of LED flip chip is disclosed. A plurality of bumps are disposed on a plurality of bond pads of a LED flip chip. Each bump includes a Cu (copper) pillar standoff formed by electroplating and a solder formed on top of the responding Cu pillar. The Cu pillar is used as a standoff during flip-chip connecting the LED flip chip to reduce solder consumption, diffusion and bump collapse. In addition, a thermal grease sealing the Cu pillar can be filled without void and the Cu pillar has excellent property of thermal conductivity, so as to improve the heat dissipation for the LED flip chip.

Description

1248221 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種LED(Light Emitting Diode，發 光二極體）晶片，特別係有關於一種LED覆晶晶片之凸塊 構 '造以及其封裝之運用。 【先前技術】 在早期的LED封裝中，LED晶片係黏貼至一例如導 線架之晶片載體，並以一打線形成之金線電性連接LED晶 片與晶片載體。最後再以一透光燈罩罩蔽LED晶片。因此 以往的LED晶片封裝是相當簡陋的，且所耗用的封裝材料 較多，不但單顆封裝體積大，封裝的效率亦較差。 近來疋將LED晶片設計為覆晶（fHp chip)型態，以凸 塊焊接接合至一具凹穴之晶片載體，例如我國專利證號第 227570唬「發光二極體封裝結構」之所揭示者。目前常用 於LED覆Μ晶片之凸塊材質係為錫鉛合金，但會有凸塊坶 陷、擴散與導熱不良等問題。 凊參閱第1圖，一種習知之LED覆晶晶片1〇係主要 包含有一例如m-v半導體材質之基板u、一發光結構 12、複數個銲墊13、14、以及複數個錫鉛凸塊2〇。其中 該發光結構12係為島狀形成於該基板11上，該些銲墊13 係分別連接該發光結構12之兩電極。而該些錫鉛凸塊2〇 係接合至該些銲墊13、14。請參閲第2圖，在led封教 過程中，會經過一加熱回焊步驟，以使該LED覆晶晶片 1〇係藉由該些錫鉛凸塊20接合至在一晶片載體3〇之一上 ,1248221 表面30上之複數個連接墊32，而該些錫鉛凸塊20係會熔 融而呈圓弧球狀。此外，一反射罩40係設置於該晶片載 體30之該上表面31。其中，在回焊該些錫鉛凸塊2〇時， 該些錫热凸塊20係為熔融態而能焊接至該些連接塾32， 但該些錫鉛凸塊20在回焊時極容易擴散或沾附至該晶片 載體30之其它金屬部位，並且該些錫錯凸塊2〇在回焊時 會埒陷造成該LED覆晶晶片1〇與該晶片載體3〇之間隔無 法控制。因此，在該晶片載體3〇之該上表面31係應覆蓋 有一銲罩層（solder mask)33，以有效界定該些錫鉛凸塊2〇 之焊接面積。然而，即使在該LED覆晶晶片1〇與該晶片 載體30會填充有一導熱膠5〇,該銲罩層33仍會有害於熱 量由该LED覆晶晶片1〇傳導至該晶片載體3〇。此外，在 覆晶接合之回焊步驟之後，由於該些錫鉛凸塊2〇係為圓 弧凸面，其在與該些銲墊i3、i4以及在與該些連接墊32 之間會开> 成一尖銳夾角’加以上述無法控制之間隔，導致 鑲導熱膠50之填充困難而會有空隙51產生，不但導熱能 力變差而且而内藏氣泡，容易導致該LED覆晶晶片1〇損 壞。再者，該些錫鉛凸塊2()之鉛成分會發出“粒子幅射 而造成電性干擾。此外，一透光封膠體6〇係可形成於該 反射罩40之開口内並密封該LED覆晶晶片1〇。 【發明内容】 本發明之主要目的係在於提供一種LED覆晶晶片之 凸塊構造以及其LED覆晶封裝構造，設置於一 lED覆晶 晶片之複數個銲墊上之每一凸塊係包含有一電鍍形成之 6 .1248221 銅柱間隔體（Cn pillar standoff f0rmed by electr〇plating)以 及一在該銅柱間隔體頂面之銲料或金屬接合層，該電鍍形 成之銅柱間隔體可以作為該led晶片在覆晶時，與一晶片 載體保持固定之間隙，並可減少銲料之用量、擴散與防止 凸塊之坍陷。此外，在封裝時一導熱膠能無空隙密封該銅 柱間隔體並且利用該銅柱間隔體本身之良好導熱能力，故 能增進該LED晶片之導熱。 本發明之次一目的係在於提供一種LED覆晶晶片之 • 凸塊構造以及其led覆晶封裝構造，其中在一 LED覆晶 B曰片上之凸塊係包含有一銅柱間隔體以及一在該銅柱間 隔體頂面之銲料或金屬接合層，該銅柱間隔體之柱側壁係 被覆有一有機吸附抗氧化膜（organic absorption antioxidant film)，以避免該銲料沾附至該柱側壁以及該銅 柱間隔體之氧化。 本發明之再一目的係在於提供一種LED覆晶晶片之 _ 凸塊構造以及其LED覆晶封裝構造，其中在一銅柱間隔體 頂面之銲料係為無鉛銲料（lead_free solder)，例如純錫或錫 銀，由該銅柱間隔體與該無鉛銲料構成之凸塊取代習知之 錫鉛凸塊，解決習知由錫鉛凸塊之鉛成分發出之α粒子幅 射造成電性干擾。 本發明之另一目的係在於提供一種LED覆晶晶片之 凸塊構造以及其LED覆晶封裝構造’其中在一 LED覆晶 晶片上之凸塊係包含有一銅柱間隔體以及一在該銅柱間 隔體頂面之銲料，該銅柱間隔體之體積係大於該銲料之體 7 1248221 積，較佳地，該銅柱間隔體之體積又大於該銲料之體積兩 倍以上，以減少銲料之用量並避免銲料過度擴散。 本發明之另一目的係在於提供一種LED覆晶封裝構 造，主要包含有一 LED覆晶晶片以及一晶片載體，在該 LED覆晶晶片上之凸塊係包含有一銅柱間隔體以及一在 該銅柱間隔體頂面之銲料或金屬接合層，該LED覆晶晶片 係以該銲料接合至該晶片載體，使該晶片載體之一上表面 係能缺乏銲罩層（lack of solder mask)，以利熱量傳導至該 ® 晶片載體。此外，一導熱膠係形成於該LED覆晶晶片與該 晶片載體之間並密封該些銅柱間隔體，不會有空隙，有利 於導熱能力。 依據本發明之LED覆晶晶片之凸塊構造，一 LED覆 晶晶片係包含有一發光結構、複數個電性連接該發光結構 之if*塾以及複數個設置於該些銲墊上之凸塊，每一凸塊係 包含一電鍍形成之銅柱間隔體以及一銲料，該銅柱間隔體 • 係設置於對應之銲墊上，每一銅柱間隔體係具有一頂面， 該銲料係形成於該銅柱間隔體之該頂面上。 【實施方式】 請參閱所附圖式，本發明將列舉以下之實施例說明。 本發明在一具體實施例中所揭示之LED覆晶晶片之 截面圖係如第3圖所示，利用該LED覆晶晶片之LED覆 晶封裝構造之截面圖係如第5圖所示。 請參閱第3圖，一 LED覆晶晶片110係主要包含有一 基板111、一發光結構112、複數個電性連接該發光結構 8 1248221 112之銲墊113、114以及複數個設置於該些銲墊ι13、114 上之凸塊120。該發光結構112係包含有n滲雜層、透明 導電層、P滲雜層、反射層（圖未繪出）等等，以在導電源 時發出光源。而其中一銲墊11 3係電性連接該發光結構112 之底層，至少一銲墊114係電性連接該發光結構112之頂 層。在本實施例中，在該些銲墊113、114上係形成有一 凸塊下金屬層（Under Bump Metallurgy layer，UBM) 115， 以利接合該些凸塊120並防止該些凸塊12〇往該LED覆晶 晶片110之其它金屬部位擴散。 每一凸塊120係包含一電鍍形成之銅柱間隔體（Cll pillar standoff formed by electroplating) 121 以及一銲料 122 ’該銅柱間隔體121係可以電鍍形成方式設置於對應 之銲藝113、114上。在本實施例中，該銅柱間隔體ι21 係固著於該凸塊下金屬層115。每一銅柱間隔體121係具 有一頂面121A以及一柱側壁121B，該些銲料12 2係形成 於對應銅柱間隔體121之頂面121A上。較佳地，該些銲 料122係為無錯銲料（leacj-free solder)，例如純錫、錫銀等 銲料或是鎳金等金屬接合層，可以避免習知錫鉛凸塊中鉛 成分發出之α粒子幅射而造成電性干擾問題。 由於’該些銅柱間隔體121係能在回焊該些銲料122 時仍維持形狀，不會因回焊溫度而變形，因此該led覆晶 晶片110在覆晶接合至一晶片載體14〇時，係可使該LEd 覆晶晶片110與該晶片載體140保持固定之間隙（如第5 圖所示）’而不會有發生該些凸塊i2〇坍陷之問題，更可以 1248221 減少該些銲料122之用量與擴散，並且該些銅柱間隔體121 之體積係應大於對應銲料122之體積，較佳地，該些銅柱 間隔體121之體積係應大於對應銲料122之體積兩倍以 上，以有效發揮在LED覆晶接合時之間隔保持效果，通常 該銅柱間隔體121之高度約為10〜70微米（// m)。此外， 如第3圖所示，該些銅柱間隔體121之該柱側壁121B係 可被覆有一有機吸附抗氧化膜130，例如有機保焊劑（0SP) 或類似物質，以避免該些銲料122沾附至對應銅柱間隔體 121之該柱側壁121B，並可防止該些銅柱間隔體ι21氧化。 請參閱第4圖，較佳地，在形成該些凸塊12〇之過程 中’该LED覆晶晶片11〇係為晶圓型態，利用一光阻材料 210形成於該LED覆晶晶片11 〇上。在微影成像之後，該 光阻材料210具有複數個對準於該些銲墊113、114之開 孔211。在該凸塊下金屬層115之電性導通之下，可以在 該些開孔211内電鍍形成該些銅柱間隔體121。較佳地， φ 5亥些知料122亦為電鍍形成，且共用同一光阻材料210， 以降低凸塊之製造成本。即在該光阻材料21〇之同一開孔The invention relates to an LED (Light Emitting Diode) wafer, in particular to a bump structure of an LED flip chip and a package thereof. Use. [Prior Art] In the early LED package, the LED chip was adhered to a wafer carrier such as a lead frame, and the LED chip and the wafer carrier were electrically connected by a gold wire formed by a single wire. Finally, the LED chip is covered with a transparent light cover. Therefore, the conventional LED chip package is quite simple, and the packaging materials used are large, and the package size is large, and the package efficiency is also poor. Recently, the LED chip has been designed as a flip-chip type (fHp chip) type, and is bump-bonded to a recessed wafer carrier. For example, the disclosure of the "Light Emitting Diode Package Structure" of the Chinese Patent No. 227570. . At present, the bump material commonly used in LED-covered wafers is tin-lead alloy, but there are problems such as bump collapse, diffusion, and poor thermal conductivity. Referring to Fig. 1, a conventional LED flip chip 1 is mainly composed of a substrate u such as an m-v semiconductor material, a light emitting structure 12, a plurality of pads 13, 14 and a plurality of tin-lead bumps 2'. The light-emitting structure 12 is formed on the substrate 11 in an island shape, and the solder pads 13 are respectively connected to the two electrodes of the light-emitting structure 12. The tin-lead bumps 2 are bonded to the pads 13, 14. Referring to FIG. 2, during the LED encapsulation process, a heating reflow step is performed to bond the LED flip chip 1 to the wafer carrier 3 by the tin-lead bumps 20. One of the 1282421 surfaces 30 has a plurality of connection pads 32, and the tin-lead bumps 20 are melted to form a circular arc. In addition, a reflector 40 is disposed on the upper surface 31 of the wafer carrier 30. Wherein, when the tin-lead bumps 2 are reflowed, the tin-hot bumps 20 are in a molten state and can be soldered to the connection ports 32, but the tin-lead bumps 20 are extremely easy to reflow. Diffused or adhered to other metal portions of the wafer carrier 30, and the tin bumps 2 are collapsed during reflow, resulting in an uncontrollable spacing between the LED flip chip 1 and the wafer carrier 3 . Therefore, the upper surface 31 of the wafer carrier 3 should be covered with a solder mask 33 to effectively define the soldering area of the tin-lead bumps 2〇. However, even if the LED flip chip 1 and the wafer carrier 30 are filled with a thermal conductive paste 5, the solder mask layer 33 is detrimental to the conduction of heat from the LED flip chip 1 to the wafer carrier 3 . In addition, after the reflow process of the flip chip bonding, since the tin-lead bumps 2 are arcuate convex surfaces, they are opened between the pads i3, i4 and the connection pads 32. The sharp angle is formed by the above-mentioned uncontrollable interval, which causes the filling of the thermal conductive adhesive 50 to be difficult, and the void 51 is generated, which not only has poor thermal conductivity but also contains air bubbles, which easily causes the LED flip chip to be damaged. Furthermore, the lead components of the tin-lead bumps 2 () may emit "particle radiation to cause electrical interference. In addition, a light-transmissive encapsulant 6 may be formed in the opening of the reflector 40 and sealed. LED flip chip 1〇. SUMMARY OF THE INVENTION The main object of the present invention is to provide a bump structure of an LED flip chip and an LED flip chip package structure thereof, which are disposed on a plurality of pads of a lED flip chip. A bump comprises a etched 6.1248221 copper pillar spacer (Cn pillar standoff f0rmed by electr〇plating) and a solder or metal bonding layer on the top surface of the copper pillar spacer, the copper pillar spacing formed by the plating The body can serve as a gap between the LED wafer and the wafer carrier during the flip chip, and can reduce the amount of solder, diffusion and prevent the bump from collapsing. In addition, a thermal paste can seal the copper pillar without a gap during packaging. The spacer and the good thermal conductivity of the copper spacer itself can improve the thermal conductivity of the LED chip. The second object of the present invention is to provide a bump structure of an LED flip chip and Led flip chip package structure, wherein the bump on an LED flip chip B includes a copper pillar spacer and a solder or metal bonding layer on the top surface of the copper spacer spacer, the pillar sidewall of the copper spacer spacer The invention is coated with an organic absorption antioxidant film to prevent the solder from adhering to the column sidewall and the oxidation of the copper pillar spacer. A further object of the present invention is to provide an LED flip chip. a bump structure and an LED flip chip package structure, wherein a solder on a top surface of a copper pillar spacer is a lead-free solder, such as pure tin or tin silver, and the copper pillar spacer and the lead-free solder are formed The bump replaces the conventional tin-lead bump to solve the conventional problem that the alpha particle radiation emitted by the lead component of the tin-lead bump causes electrical interference. Another object of the present invention is to provide a bump structure of the LED flip chip. And an LED flip chip package structure in which the bumps on an LED flip chip comprise a copper pillar spacer and a solder on the top surface of the copper spacer spacer, the volume of the copper spacer spacer Preferably, the volume of the copper spacer is greater than twice the volume of the solder to reduce the amount of solder and avoid excessive diffusion of the solder. Another object of the present invention is An LED flip chip package structure is provided, which mainly comprises an LED flip chip and a wafer carrier, wherein the bump on the LED flip chip comprises a copper pillar spacer and a solder on the top surface of the copper spacer A metal bonding layer, the LED flip chip is bonded to the wafer carrier by the solder, such that an upper surface of the wafer carrier is capable of lacking a solder of a solder mask to facilitate heat conduction to the wafer carrier. In addition, a thermal conductive adhesive is formed between the LED flip chip and the wafer carrier and seals the copper post spacers without voids, which is advantageous for thermal conductivity. According to the bump structure of the LED flip chip of the present invention, an LED flip chip includes a light emitting structure, a plurality of if*s electrically connected to the light emitting structure, and a plurality of bumps disposed on the pads, each of A bump comprises a plated copper pillar spacer and a solder, the copper spacer is disposed on the corresponding pad, each copper spacer has a top surface, and the solder is formed on the copper pillar The top surface of the spacer. [Embodiment] Referring to the drawings, the present invention will be described by way of the following examples. A cross-sectional view of an LED flip chip disclosed in a specific embodiment of the present invention is shown in Fig. 3, and a cross-sectional view of the LED flip chip package structure using the LED flip chip is as shown in Fig. 5. Referring to FIG. 3, an LED flip chip 110 mainly includes a substrate 111, a light emitting structure 112, a plurality of pads 113, 114 electrically connected to the light emitting structure 8 1248221 112, and a plurality of pads disposed on the pads. The bumps 120 on ι13, 114. The light emitting structure 112 includes an n-permeable layer, a transparent conductive layer, a P-permeable layer, a reflective layer (not shown), and the like to emit a light source when the power is turned on. One of the pads 11 3 is electrically connected to the bottom layer of the light emitting structure 112 , and at least one of the pads 114 is electrically connected to the top layer of the light emitting structure 112 . In this embodiment, an under bump metallurgy layer (UBM) 115 is formed on the pads 113 and 114 to facilitate bonding the bumps 120 and preventing the bumps 12 from flowing toward each other. The other metal portions of the LED flip chip 110 are diffused. Each of the bumps 120 includes a plating pillar formed by electroplating 121 and a solder 122. The copper pillar spacers 121 are disposed on the corresponding soldering wires 113 and 114 by electroplating. . In this embodiment, the copper pillar spacer ι21 is fixed to the under bump metal layer 115. Each of the copper pillar spacers 121 has a top surface 121A and a pillar sidewall 121B. The solder 12 2 is formed on the top surface 121A of the corresponding copper pillar spacer 121. Preferably, the solders 122 are lead-free solders, such as solders such as pure tin and tin-silver, or metal bonding layers such as nickel-gold, which can avoid the lead component in the tin-lead bumps. The alpha particle radiation causes electrical interference problems. Since the copper pillar spacers 121 can maintain the shape while reflowing the solders 122 and are not deformed by the reflow temperature, the LED flip chip 110 is flip-chip bonded to a wafer carrier 14 , the LEd flip chip 110 and the wafer carrier 140 can be kept at a fixed gap (as shown in FIG. 5), without the problem that the bumps i2 are collapsed, and the 1242821 can be reduced. The amount of the copper column spacers 121 should be greater than the volume of the corresponding solder 122. Preferably, the volume of the copper column spacers 121 should be more than twice the volume of the corresponding solder 122. In order to effectively exhibit the effect of maintaining the spacing during LED flip-chip bonding, the height of the copper pillar spacers 121 is generally about 10 to 70 micrometers (//m). In addition, as shown in FIG. 3, the pillar sidewalls 121B of the copper pillar spacers 121 may be coated with an organic adsorption anti-oxidation film 130, such as an organic solder resist (0SP) or the like, to prevent the solders from being wetted. The column sidewalls 121B of the corresponding copper pillar spacers 121 are attached, and the copper pillar spacers ι21 are prevented from being oxidized. Referring to FIG. 4 , in the process of forming the bumps 12 ' , the LED flip chip 11 is a wafer type, and the photoresist wafer 210 is formed on the LED flip chip 11 . 〇上. After lithography, the photoresist material 210 has a plurality of openings 211 aligned with the pads 113, 114. The copper pillar spacers 121 may be plated in the openings 211 under the electrical conduction of the under bump metal layer 115. Preferably, the φ 5 liters of the material 122 are also formed by electroplating, and share the same photoresist material 210 to reduce the manufacturing cost of the bumps. That is, the same opening in the photoresist material 21

LED覆晶晶片11〇。LED flip chip 11〇.

低成本之LED覆晶封裝構造。其中該晶 3曰片110係可覆晶接合至 並加以封裝成一高導熱、 _該晶片載體140係具有 10 1248221 上表面141’該上表面141上係形成複數個連接墊142。 通常該晶片載體140之該上表面141係設置有一反射罩 150 ’該反射罩150係具有一反射鏡面ι51，其係位在該反 射罩150之一開口内。在覆晶接合過程中之回焊時，該些 銲料122係焊接至該些連接墊142。藉由該些銅柱間隔體 121保持該LED覆晶晶片11〇與該晶片載體ι4〇之間隔， 且能降少該些銲料122之用量，使得該些銲料122不會過 度擴散或沾附該晶片載體140，並且防止該些凸塊120之 埒陷。因此’該晶片載體140之該上表面141係可以作成 缺乏銲罩層（lack of s〇ider mask)之結構，以利熱量由該 led覆晶晶片110傳導至該晶片載體14〇。此外，在覆晶 接合之同時或之後，由於該些銅柱間隔體121不會在與接 合之該些銲墊113、114之間或是在與該些連接墊142之 間幵y成填充死角，一導熱膠i 6〇係能無空隙地形成於該 LED覆曰曰晶片11〇與該晶片載體14〇之間，有利於熱量傳 導再者省些銅柱間隔體^之導熱性約為4， 遢優於習知錫鉛凸塊之導熱性（約5〇 w/mK)。因此，本發Low cost LED flip chip package construction. The crystal wafer 110 can be flip-chip bonded to and packaged into a high thermal conductivity. The wafer carrier 140 has a top surface 141' of 10 1248221. The upper surface 141 is formed with a plurality of connection pads 142. Typically, the upper surface 141 of the wafer carrier 140 is provided with a reflective cover 150' which has a mirrored surface ι 51 that is positioned within one of the openings of the reflective cover 150. The solder 122 is soldered to the connection pads 142 during reflow soldering during flip chip bonding. The LED flip chip 121 is spaced apart from the wafer carrier by the copper pillar spacers 121, and the amount of the solders 122 is reduced, so that the solders 122 are not excessively diffused or adhered. The wafer carrier 140 is prevented from collapsing the bumps 120. Therefore, the upper surface 141 of the wafer carrier 140 can be made to have a structure of a lack of a mask to allow heat to be conducted from the led flip chip 110 to the wafer carrier 14A. In addition, at the same time as or after the flip chip bonding, the copper pillar spacers 121 do not fill the dead corner between the bonding pads 113, 114 and the bonding pads 142. A thermal conductive adhesive i 6 can be formed between the LED cover wafer 11 and the wafer carrier 14 无 without voids, which is advantageous for heat conduction and further saves the thermal conductivity of the copper spacers to about 4 , 遢 is superior to the thermal conductivity of the tin-lead bumps (about 5〇w/mK). Therefore, this issue

LED覆晶晶片11 〇之散熱效率。The heat dissipation efficiency of the LED flip chip 11 〇.

轉換由該LED覆晶晶片 ，一透光封膠體170或是一透光 1覆晶晶片110。該透光封膠體17〇 1 110並包含有螢光粉，以吸收並 1發出之光源，例如由該led 11 1248221 覆晶晶片110發出之藍光或紫光轉換成白光。 本發明之保護範圍當視後附之申請專利範圍所界定 • 者為準任何熟知此項技藝者，在不脫離本發明之精神和 範圍内所作之任何變化與修改，均屬於本發明之保護範 圍。 【圖式簡單說明】 第1圖··習知LED覆晶晶片之截面示意圖。 第2圖：習知LED覆晶封裝構造之截面示意圖。 •第3 ® :依本發明之一具體實施例，一種led覆晶晶片 之截面示意圖。 第4圖：依本發明之一具體實施例，該led覆晶晶片在 電鍍形成凸塊時之截面示意圖。 第5圖：依本發明之一具體實施例，一種包含該led覆 晶晶片之LED覆晶封裝構造之截面示意圖。 【主要元件符號說明】 10 LED覆晶晶片 11 基板 12 發光結構 13 銲墊 14 銲墊 20 銲料凸塊 30 晶片載體 31 上表面 32 連接墊 33 銲罩層 40 反射罩 50 導熱膠 51 空隙 60 透光封膠體 110 LED覆晶晶片 111 基板 112 發光結構 113 銲墊 12 1248221 114 銲塾 115 凸塊下金屬層 120 凸塊 121 銅柱間隔體 121A 121B 柱側壁 122 銲料 130 有機吸附抗氧化膜 140 晶片載體 141 上表面 142 150 反射罩 151 反射鏡面 160 導熱膠 170 透光封膠體 210 光阻材料 211 開孔 頂面 連接墊The wafer is flipped by the LED, a light-transmissive encapsulant 170 or a light-transmissive 1 flip chip 110. The light-transmissive encapsulant 17 〇 1 110 and containing phosphor powder to absorb and emit light, for example, blue or violet light emitted by the LED 11 1248221 flip chip 110 is converted into white light. The scope of the present invention is defined by the scope of the appended claims. Any changes and modifications made without departing from the spirit and scope of the invention are intended to be included in the scope of the present invention. . BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view of a conventional LED flip chip. Figure 2: A schematic cross-sectional view of a conventional LED flip chip package structure. • 3®: A schematic cross-sectional view of a led flip chip in accordance with an embodiment of the present invention. Fig. 4 is a cross-sectional view showing the LED flip chip in the form of bumps formed by electroplating according to an embodiment of the present invention. Figure 5 is a cross-sectional view showing an LED flip chip package structure including the LED flip chip according to an embodiment of the present invention. [Main component symbol description] 10 LED flip chip 11 substrate 12 light-emitting structure 13 pad 14 pad 20 solder bump 30 wafer carrier 31 upper surface 32 connection pad 33 solder mask layer 40 reflective cover 50 thermal paste 51 gap 60 light transmission Sealant 110 LED flip chip 111 substrate 112 light emitting structure 113 solder pad 12 1248221 114 solder bump 115 under bump metal layer 120 bump 121 copper pillar spacer 121A 121B pillar sidewall 122 solder 130 organic adsorption anti-oxidation film 140 wafer carrier 141 Upper surface 142 150 Reflector 151 Mirror surface 160 Thermal paste 170 Light-transmissive sealant 210 Photoresist material 211 Opening top connection pad

1313

Claims (1)

1248221 十、申請專利範圍： 1、 一種LED覆晶晶片之凸塊構造，該LED覆晶晶片係 包含有一發光結構、複數個電性連接該發光結構之銲 墊以及複數個設置於該些銲墊上之凸塊，每一凸塊係 包含： 一電鍍形成之銅柱間隔體（Cu pillar standoff formed by electroplating)，其係設置於對應之銲墊上，每一 鋼柱間隔體係具有一頂面及一柱側壁；及 ® 一銲料，其係形成於該銅柱間隔體之該頂面上。 2、 如申請專利範圍第i項所述之led覆晶晶片之凸塊構 造，其中該銅柱間隔體之柱側壁係被覆有一有機吸附 抗氧化膜，以避免該銲料沾附至該柱側壁。 3 、如申請專利範圍第1項所述之LED覆晶晶片之凸塊構 造，其中該銲料係為無鉛銲料（lead_free solder)。 4如申請專利範圍第工項所述之lED覆晶晶片之凸塊構 • 造，其中該銲料係為純錫（Sn)。 5如申請專利範圍第i項所述之lED覆晶晶片之凸塊構 k，其中該鋼柱間隔體之體積係大於該銲料之體積。 6、 如申請專利範圍第i項所述之LED覆晶晶片之凸塊構 造，其中該銅柱間隔體之體積係大於該銲料之體積兩 倍以上。 7、 如：請專利範圍第！項所述之LED覆晶晶片之凸塊構 k其中该銅柱間隔體之高度約為1〇~7〇微米（"爪）。 8、 如W專利範圍第i項所述之㈣覆晶晶片之凸塊構 1248221 ^其中该些銲墊上係形成有一凸塊下金屬層 (UBM) ’以利接合該些銅柱間隔體。 9如申明專利範圍第i項所述之覆晶晶片之凸塊構 以，其中該銲料係由電鍍形成。 10如申Μ專利範圍第9項所述之LED覆晶晶片之凸塊構 k，其中該銲料係與該銅柱間隔體藉由一光阻材料之 同一開孔加以電鍍形成。 11 種LED覆晶封裝構造，包含·· - LED覆晶晶片，其係包含有一發光結構、複數個電 性連接该發光結構之銲墊以及複數個設置於該些銲 墊上之凸塊，每一凸塊係包含： 一電鍍形成之銅柱間隔體，其係設置於對應之銲墊 上’每一銅柱間隔體係具有一頂面；及 鋅料，其係形成於該銅柱間隔體之該頂面上；及 一晶片載體，其係具有一上表面以及複數個位於該上 表面之連接墊，以供該些銲料之接合。 12如申明專利範圍第11項所述之[ED覆晶封裝構造， 其中該晶片載體之該上表面係缺乏銲罩層（Uck 〇f solder mask)。 13、如申請專利範圍第^項所述之LED覆晶封裝構造， 其另包含有一導熱膠，其係形成於該LED覆晶晶片與 δ亥晶片載體之間並密封該些銅柱間隔體。 W、如申請專利範圍第Π項所述之LED覆晶封裝構造， 其中該晶片載體之該上表面係設置有一反射罩。 15 1248221 15、=請專利範圍第14項所述之LED覆 16其中該反射罩係具有在—開口内之反射鏡面。 、如^請專利範圍第以15項所述之^|晶封裝構 ，其另包含有-透光封膠體，其係密封該LED覆曰 晶片。 U復日曰 17 18 士申°月專利範圍帛16項所述之led覆晶封裝構、I， 其中該透光封膠體係包含有螢光粉。 t k， 19 如申睛專利範圍第U項所述之LED覆晶封裝構造， 其中該銲料係為無鉛銲料。 如申凊專利範圍第U項所述之LED覆晶封裴構造， 其中該銲料係為純錫。 20 如申請專利範圍第:^項所述之LED覆晶封裝構造， 其中該銲料係為鎳金。 21如中請專利範圍第u項所述之LED覆晶封裝構造， 其中該銅柱間隔體之體積係大於該銲料之體積。 22、如申請專利範圍帛u項所述之LED覆晶封装構造， 其中該鋼柱間隔體之體積係大於該銲料之體積兩倍 以上。 23、 如申請專利範圍第n項所述之LED覆晶封裝構造， 其中該銅柱間隔體之高度約為10〜70微米m)。 24、 如申請專利範圍第n項所述之LED覆晶封裝構造， 其中該些銲墊上係形成有一凸塊下金屬層（ϋΒΜ)，以 利接合該些銅柱間隔體。 25、 如申請專利範圍第U項所述之LED覆晶封裝構造， 16 1248221 其中該銲料係由電鍍形成。 26 27 28、 29、 30、 31、 32、 、如申請專利範圍第25項所述之LED覆晶封裝構造， 其中該銲料係與該銅柱間隔體藉由一光阻材料之同 一開孔加以電艘形成。 、一種LED覆晶晶片之凸塊構造，該LED覆晶晶片係 包含有一發光結構、複數個電性連接該發光結構之銲 墊以及複數個設置於該些銲墊上之凸塊，每一凸塊係 包含： 電鑛形成之銅柱間隔體（Cu piiiar stan(j0ff f〇rmed by electroplating)，其係設置於對應之銲墊上，每一 銅柱間隔體係具有一頂面及一柱側壁；及 一金屬接合層，其係形成於該銅柱間隔體之該頂面 上。 如申請專利範圍第27項所述之LED覆晶晶片之凸塊 構造，其中該金屬接合層係包含鎳金。 如申請專利範圍第27項所述之LED覆晶晶片之凸塊 構迢’其中该銅柱間隔體之體積係大於該金屬接合層 之體積。 如申請專利範圍第27項所述之LED覆晶晶片之凸塊 構ie ’其中該銅柱間隔體之體積係大於該金屬接合層 之體積兩倍以上。 如申請專利範圍第27項所述之LED覆晶晶片之凸塊 構造’其中該銅柱間隔體之高度約為1〇〜7〇微米（V爪）。 如申請專利範圍第27項所述之LED覆晶晶片之凸塊 17 1248221 構造，其中該些銲墊上係形成有一凸塊下金屬層 (UBM)，以利接合該些銅柱間隔體。 33、 如申請專利範圍第27項所述之LED覆晶晶片之凸塊 構造，其中該金屬接合層係由電鍍形成。 34、 如申請專利範圍第33項所述之LED覆晶晶片之凸塊 構造，其中該金屬接合層係與該銅柱間隔體藉由一光 阻材料之同一開孔加以電鍍形成。1248221 X. Patent application scope: 1. A bump structure of an LED flip chip, the LED flip chip comprises a light emitting structure, a plurality of pads electrically connected to the light emitting structure, and a plurality of pads disposed on the pads The bumps, each of the bumps comprises: a Cu pillar standoff formed by electroplating, which is disposed on the corresponding pad, each of the column spacers has a top surface and a column a sidewall; and a solder formed on the top surface of the copper pillar spacer. 2. The bump structure of the LED flip chip according to claim i, wherein the pillar side wall of the copper pillar spacer is coated with an organic adsorption anti-oxidation film to prevent the solder from adhering to the pillar sidewall. 3. The bump structure of the LED flip chip according to claim 1, wherein the solder is lead-free solder. 4 The bump structure of the lED flip chip as described in the application of the patent scope, wherein the solder is pure tin (Sn). 5 The bump structure k of the lED flip chip as described in claim i, wherein the volume of the steel column spacer is greater than the volume of the solder. 6. The bump structure of the LED flip chip according to claim i, wherein the volume of the copper spacer is greater than twice the volume of the solder. 7, such as: please patent scope! The bump structure of the LED flip chip described in the item wherein the height of the copper pillar spacer is about 1 〇 to 7 μm ("claw). 8. The bump structure 1248221 of the flip chip according to the fourth aspect of the patent scope of the invention, wherein the pads are formed with an under bump metal layer (UBM) to facilitate bonding the copper pillar spacers. 9. The bump of a flip chip as described in claim i, wherein the solder is formed by electroplating. The bump structure of the LED flip chip according to claim 9, wherein the solder and the copper spacer are formed by electroplating the same opening of a photoresist material. 11 LED flip chip package structure, comprising: · LED flip chip, comprising a light emitting structure, a plurality of pads electrically connected to the light emitting structure, and a plurality of bumps disposed on the pads, each The bump system comprises: a plated copper column spacer disposed on the corresponding pad; each copper column spacer system has a top surface; and a zinc material formed on the top of the copper column spacer And a wafer carrier having an upper surface and a plurality of connection pads on the upper surface for bonding the solder. 12. The ED flip chip package structure of claim 11, wherein the upper surface of the wafer carrier lacks a Uck 〇f solder mask. 13. The LED flip chip package structure of claim 2, further comprising a thermal conductive paste formed between the LED flip chip and the δ ray wafer carrier and sealing the copper post spacers. The LED flip chip package structure of claim 4, wherein the upper surface of the wafer carrier is provided with a reflective cover. 15 1248221 15 , = Please refer to the LED cover 16 of the patent scope of claim 14, wherein the reflector has a mirror surface in the opening. For example, please refer to the patent package described in Item 15 of the patent, which further comprises a light-transmissive encapsulant for sealing the LED-covered wafer. U 曰日曰 17 18 士申°月 patent scope 帛16 of the LED flip chip package structure, I, wherein the light-transmissive sealing system contains phosphor powder. t k, 19 The LED flip chip package structure of claim U, wherein the solder is lead-free solder. The LED flip-chip sealing structure described in claim U, wherein the solder is pure tin. 20 The LED flip chip package structure as claimed in claim 4, wherein the solder is nickel gold. The LED flip chip package structure of claim 5, wherein the volume of the copper post spacer is greater than the volume of the solder. 22. The LED flip chip package structure of claim 2, wherein the volume of the steel column spacer is greater than twice the volume of the solder. 23. The LED flip chip package structure of claim n, wherein the height of the copper pillar spacer is about 10 to 70 micrometers m). 24. The LED flip chip package structure of claim n, wherein the pads are formed with an under bump metal layer to facilitate bonding the copper pillar spacers. 25. The LED flip chip package structure of claim U, 16 1248221, wherein the solder is formed by electroplating. The LED flip chip package structure of claim 25, wherein the solder system and the copper column spacer are provided by the same opening of a photoresist material. The electric boat is formed. a bump structure of an LED flip chip, the LED flip chip comprising a light emitting structure, a plurality of pads electrically connected to the light emitting structure, and a plurality of bumps disposed on the pads, each bump The system comprises: a copper pillar spacer formed by an electric ore (J0ff f〇rmed by electroplating), which is disposed on a corresponding pad, each copper pillar spacer system has a top surface and a pillar side wall; The metal bonding layer is formed on the top surface of the copper pillar spacer. The bump structure of the LED flip chip according to claim 27, wherein the metal bonding layer comprises nickel gold. The bump structure of the LED flip chip of the invention of claim 27, wherein the volume of the copper spacer is greater than the volume of the metal bonding layer. The LED flip chip according to claim 27 of the patent application. a bump structure in which the volume of the copper pillar spacer is more than twice the volume of the metal bonding layer. The bump structure of the LED flip chip of the invention of claim 27, wherein the copper pillar spacer It The height is about 1 〇 to 7 〇 micrometers (V-claw). The LED flip-chip wafer bump 17 1248221 structure according to claim 27, wherein the solder pads are formed with an under bump metal layer (UBM). The bump structure of the LED flip chip according to claim 27, wherein the metal bonding layer is formed by electroplating. The bump structure of the above-mentioned LED flip chip, wherein the metal bonding layer and the copper pillar spacer are plated by the same opening of a photoresist material. 1818
TW094114531A 2005-05-05 2005-05-05 Bump structure of LED flip chip TWI248221B (en)

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Cited By (1)

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Publication number Priority date Publication date Assignee Title
US8846519B2 (en) 2006-10-14 2014-09-30 Advanpack Solutions Pte Ltd. Interconnections for fine pitch semiconductor devices and manufacturing method thereof

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TWI463585B (en) * 2012-01-03 2014-12-01 Chipbond Technology Corp Semiconductor package and method thereof
TWI842489B (en) * 2023-04-24 2024-05-11 友達光電股份有限公司 Display apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8846519B2 (en) 2006-10-14 2014-09-30 Advanpack Solutions Pte Ltd. Interconnections for fine pitch semiconductor devices and manufacturing method thereof
US9362206B2 (en) 2006-10-14 2016-06-07 Advanpack Solutions Pte Ltd. Chip and manufacturing method thereof

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