CN206236700U - A kind of many I/O flip LED chips array bump packaging structures - Google Patents

Abstract

The purpose of this utility model is to provide a kind of many I/O flip LED chips array bump packaging structures, including the electrode of flip LED chips array salient point, the array salient point minimum unit of electrode is 2Pin × 2Pin arrays, into corner or Triangle-Profile.Array salient point includes being layed in the passivation layer of chip functions layer surface, covering electrode window through ray and intercalation electrode window and being layed in metal layer on chip functions layer, is layed on metal layer and surround metal layer and formed and is reserved with the welding resistance layer pattern of welding resistance window, is embedded with array solder bump higher than welding resistance window in filling in welding resistance window.The encapsulating structure ensures to form a planar structure for stabilization in reflux course, ensure the uniform feed of P/N knots, reduce connection defect, reduce contact resistance and thermal resistance, improve technology stability and encapsulation yields, multi-chip, the sequencing drive control of many combinations and diversified array chip product are capable of achieving, subsequent encapsulating process is simpler, in hgher efficiency, cost is lower.

Description

A kind of many I/O flip LED chips array bump packaging structures

Technical field

The utility model is related to a kind of LED encapsulation structure, especially a kind of many I/O flip LEDs array bump packaging structures.

Background technology

Because illuminating LED current density and power density are continuously increased, traditional formal dress packaged type thermal resistance high, electrode CURRENT DISTRIBUTION is uneven, the low problem of wire bond package efficiency be increasingly becoming great power LED development and penetration and promotion bottleneck. With the release of face-down bonding technique, LED chips can eliminate gold thread and be bonded and use solder or conduction with the connection of wiring board Glue is encapsulated, and is referred to as " without gold thread encapsulation ", also referred to as " exempts from encapsulation ".One is disclosed in Chinese utility model patent CN1787242 The method for packing of flip LED chips is planted, upside-down mounting welding core and Al printed circuit board (PCB)s are directly welded key using thick Cu and Au salient points Close, the flip LED coplanarity of this pair of bump structure is poor, have impact on the stability and bonding quality of bonding；Cu as salient point without Method keeps out lead-free tin solder（High-tin solder）Etch, connection reliability is greatly lowered；Using proof gold as convex point material, So that salient point preparation cost is significantly raised.In recent years, industrial quarters generally replaces pure Au using the eutectic auri solder of Au80Sn20 As the connecting material of flip-chip packaged.But gold-tin alloy eutectic melting point is high, is not suitable for plastic package structure；Thermal compression welding must be used And common Reflow Soldering can not be used, so as to cause packaging technology complicated, packaging cost is still very high.Additionally, traditional LED core Piece only one of which P-N junction and two electrodes so that can not only be implanted into two solder bumps on single LEDs chip and lose die bond Coplanar stability, many I/O LED chip arrays of multiple P-N junctions can not be realized.

With being continuously increased for LED component power, multi-chip, the LED integrated circuit luminescent devices of multi-pipe pin have become The developing direction of LED component of new generation, its optimal structure type is exactly the integrated flip LED chips of many I/O array formats, and It is expected to turn into the basic luminescent device of LED illumination component from now on.

The content of the invention

The purpose of this utility model is to solve above-mentioned having in the prior art present in great power LED and flip LED A kind of shortcoming and defect, there is provided many I/O flip LEDs array bump packaging structures, many I/O flip LEDs array salient point encapsulation knots Structure can realize the extensive manufacture of flip LED, the upside-down mounting electrode of LED single-chips be resolved into LED chip array bump structure, most Junior unit is 2Pin × 2Pin arrays, advantageously ensures that one planar structure of stabilization of formation in reflux course, is further reduced Attachment alignment difficulty；Big electrode is divided into small many I/O array structures, multi-chip, the sequencing of many combinations is capable of achieving and is driven Dynamic control, while ensureing the uniform feed of P/N knots, reducing connection defect, reduce contact resistance and thermal resistance；Improve process stabilizing Property and encapsulation yields, be capable of achieving multi-chip, the sequencing drive control of many combinations and diversified array chip product, follow-up envelope Dress technique is simpler, in hgher efficiency, cost is lower, is more suitable for large-scale industrial production.

The utility model solve technical scheme that its technical problem is used for：A kind of many I/O flip LED chips array salient points Encapsulating structure, the single electrode of flip LED chips is array salient point；Described array salient point includes being layed in chip functions layer table In the passivation layer in face, covering electrode window through ray and intercalation electrode window and be layed on chip functions layer metal layer, be layed in On metal layer and surround metal layer formed be reserved with welding resistance window welding resistance layer pattern, in welding resistance window filling be embedded with height In the array solder bump of welding resistance window, metal layer is located at the lower section of array solder bump.The utility model is using evaporation, electricity Plating and chemical plating method make more than three layers of metal layer, and layers of material to metal layer optimizes combination, enters one Step simplify preparation technology, reduce preparation cost, improve pad tolerance solder or soldering paste it is molten（It is molten）Erosion.Metal layer energy and array Solder bump forms good metallurgical binding, and solder is molten under diffusion impervious layer can effectively prevent multi-reflow and high-temperature aging （It is molten）Erosion.Welding resistance window is provided with metal layer, the welding resistance window can be constrained in the case where electrode area is not reduced The region of array solder bump backflow, welding resistance window can constrain the formation of array solder bump, prevent array solder bump from returning Solder excessive formation defect during stream.It is relatively regular, high that welding resistance window also ensures that array solder bump is formed in reflux course Degree unified hemispherical or elliposoidal so that the use of array solder bump more controllable precise, effective array prevent solder convex Point climbs wall, it is to avoid climbing caused by wall functional layer failure or leak electricity because of array solder bump, improves technology stability With the yields of encapsulation.

This mode is that the upside-down mounting electrode of single led flip-chip is resolved into LED flip chip array（Multiple electrodes）It is convex Point structure, the array salient point minimum unit of the electrode of the flip LED chips is 2Pin × 2Pin arrays；Saved with a P/N The P electrode of flip LED chips is divided into 2 array salient points, and N electrode is divided into 2 array salient points, constitutes one and contains 4 battle arrays The array structure of row salient point.Or, it is convex that an electrode with a flip LED chips for P/N sections is divided into 2 arrays Point, another electrode is not split to form 1 array salient point, and composition contains 3 array structures of array salient point.2Pin × the 2Pin The LED flip chip of array is the LEDs chip that single P/N knots are constituted, and its P electrode makes two or more parallel connections（Or string Connection）Array salient point, N electrode also makes two or more parallel connections（Or series connection）Array salient point.

Or be to plant 4 on two 2 P electrodes and 2 N electrodes of the flip LED chips of P/N sections Array solder bump constitutes 4 I/O flip LED chips array bump packaging structures.The array salient point is in flip LED chips surface Into corner or Triangle-Profile.The LED flip chip of 2Pin × 2Pin arrays is two independent P/N knots, four electrodes point Not Zhi Ru array salient point constitute 2 discrete light emitting diodes, i.e. each P (or N) electrode make two or more parallel connections（Or string Connection）Array salient point；Similarly, the flip LED chips of 2Pin × 2Pin arrays can also be three or more independent P/N Knot, it is in parallel that each P (or N) electrode makes three or more（Or series connection）Array salient point to constitute three or more discrete luminous Diode.

Further, described metal layer is by Cr/Al/Ti/Pt（Au）Or Ni/Al/Ti/Pt（Au）Or Ni/Ag/Ti/ Pt（Au）Composition multilayer metal compound structure；Described metallized layer surface is additionally provided with the diffusion barrier positioned at welding resistance bottom of window Layer, diffusion impervious layer is by Ni（P）Metal structure is constituted, the electrode size of the size more than flip LED chips of diffusion impervious layer.

Further, described welding resistance window is rounded or ellipse, and the size of welding resistance layer pattern is less than diffusion impervious layer Size.Welding resistance layer pattern is printed on the diffusion barrier.Welding resistance window is rounded, oval etc., is covered in diffusion impervious layer table Face edge, the core of welding resistance window exposes the pad locations of array solder bump implantation.

Further, described array solder bump is solder containing pb or lead-free tin solder or tin solder or the weldering of indium base Any one of material or bismuthino or auri solder；Described array solder bump is rounded square or oval spherical.Without slicker solder Parent metal is as using SAC305 or SAC105, SAC0307 etc..The array salient point has preparation process is simple, preparation efficiency high, convex The good advantage of point uniformity；The material selection of solder bump of the present utility model, solder of its cost far below Au80Sn20 is convex Point material.

In addition, the utility model further relates to a kind of method for packing of many I/O flip LED chips array bump packaging structures, The step of method for packing is：

（1）The metal of multiple layer metal Rotating fields is formed using the method for evaporation, plating and chemical plating on electrode window through ray surface Change layer, then cover diffusion impervious layer in metallized layer surface；

（2）Welding resistance layer pattern is made in the printing of diffusion impervious layer surface periphery surrounding and form welding resistance window again, welding resistance window The formation of mouth constraint array solder bump, prevents the excessive formation defect of array solder bump solder during reflow；

（3）Using EFI print or the forming method of Printing Paste backflow or the implantation of laser soldered ball or plating array solder bump Array solder bump is formed on welding resistance window.

Further, the step in the method for packing（1）In diffusion impervious layer be covered on metallized layer surface and use Two ways；When it is low current and small-power to encapsulate flip LED chips, diffusion impervious layer is using sputtering or vacuum evaporation mode On metal layer；When encapsulate flip LED chips be high current and it is high-power when, diffusion impervious layer using plating or chemical plating The mode for thickening is on metal layer.

In addition, the generation type of electrode window through ray is：In chip functions layer and Sapphire Substrate top surface on using evaporation, plating Chip surface passivation layer is set with the method for chemical plating, the electrode position of correspondence flip LED chips is not provided with chip surface passivation Layer forms electrode window through ray.

The packaged type of many I/O flip LEDs array bump packaging structures of the present utility model can be in follow-up encapsulation stream Product specification in journey according to needed for flexibly designs cut lengths, and it is also an option that directly carries out wafer-level packaging （CSP）, fluorescent material coating, array solder bump spray printing are directly carried out after can on demand being cut on flip LED chips and are returned The operations such as stream.Compared with conventional thermocompression technique, the flip LED chips subsequent encapsulating process is simpler, in hgher efficiency, cost more It is low, it is more suitable for large-scale industrial production.

The beneficial effects of the utility model are：Many I/O flip LEDs array bump packaging structures of the present utility model can be realized The extensive manufacture of flip LED, LED chip array bump structure is resolved into by the upside-down mounting electrode of LED single-chips, and minimum unit is 2Pin × 2Pin arrays, advantageously ensure that one planar structure of stabilization of formation in reflux course, further reduce attachment alignment Difficulty；Big electrode is divided into small many I/O array structures, multi-chip, the sequencing drive control of many combinations is capable of achieving, together When ensure P/N knot uniform feed, reduce connection defect, reduce contact resistance and thermal resistance；The many I/O arrays salient points of extensive upside-down mounting Structure, is conducive to improving technology stability and encapsulation yields, and subsequent encapsulating process is simpler, in hgher efficiency, cost is lower, It is more suitable for large-scale industrial production.

Brief description of the drawings

Below in conjunction with the accompanying drawings, and by reference to following detailed description, the utility model will be better understood and it is understood Advantages and features, accompanying drawing is used to illustrate the utility model, and unrestricted the utility model；Representing the accompanying drawing of structure may not press Ratio is drawn；Also, in accompanying drawing, same or similar element indicates same or similar label：

Fig. 1 is the encapsulating structure profile of the array salient point of the flip LED chips array in the utility model；

Fig. 2 is the schematic diagram of a kind of many I/O flip LEDs array bump packaging structures of the utility model embodiment 1；

Fig. 3 is the profile of a kind of many I/O flip LEDs array bump packaging structures of the utility model embodiment 1；

Fig. 4 is the schematic diagram of a kind of many I/O flip LEDs array bump packaging structures of the utility model embodiment 2；

Fig. 5 is the schematic diagram of a kind of many I/O flip LEDs array bump packaging structures of the utility model embodiment 3.

Specific embodiment

Fig. 1 is the array bump packaging structure profile of flip LED chips, the various pieces of forming array as illustrated, Including chip functions layer and Sapphire Substrate 1, the passivation layer 2 of flip LED chips function layer surface is layed in, covers electrode window through ray And intercalation electrode window in and be layed in chip functions layer on metal layer 3, be layed on chip surface passivation layer and surround Metal layer forms and is reserved with the welding resistance layer pattern 4 of welding resistance window, is embedded with the battle array higher than welding resistance window in filling in welding resistance window Row solder bump 5.The utility model makes more than three layers of metal layer using evaporation, plating and chemical plating method, and to gold The layers of material of categoryization layer optimizes combination, further simplifies preparation technology, reduces preparation cost, improves pad tolerance solder Or soldering paste is molten（It is molten）Erosion.Metal layer can form good metallurgical binding with array solder bump, and diffusion impervious layer can be effective Prevent multi-reflow and high-temperature aging under solder it is molten（It is molten）Erosion.Welding resistance window, the welding resistance window are provided with metal layer The region of array solder bump backflow can be constrained in the case where electrode area is not reduced, welding resistance window can constrain array weldering Expect the formation of salient point, prevent the excessive formation defect of array solder bump solder during reflow.Welding resistance window also ensures array solder Salient point forms relatively regular, high unity hemispherical or elliposoidal in reflux course so that the use of array solder bump More controllable precise, what effective array prevented solder bump climbs wall, it is to avoid climb function caused by wall because of array solder bump Layer failure is leaked electricity, and improves the yields of technology stability and encapsulation.

The metallized layer surface is additionally provided with the diffusion impervious layer positioned at welding resistance bottom of window.

The unit of array salient point composition is 2Pin, and the metal layer is by Cr/Al/Ti/Pt（Au）Or Ni/Al/Ti/Pt （Au）Or Ni/Ag/Ti/Pt（Au）Composition multilayer metal compound structure, diffusion impervious layer is by Ni（P）Metal structure is constituted, diffusion Electrode size of the size on barrier layer more than flip LED chips base material.

The welding resistance window is rounded or ellipse, and solder mask size is less than diffusion impervious layer size.On the diffusion barrier Printing welding resistance layer pattern.Welding resistance window is rounded, oval etc., diffusion impervious layer marginal surface is covered in, in welding resistance window Center portion point exposes the pad locations of solder bump implantation.The array solder bump is rounded.

The array solder bump is solder containing pb or lead-free tin solder or tin solder or indium-based solder or bismuthino solder Any one.Lead-free tin solder is as using SAC305 or SAC105, SAC0307 etc..The array salient point has preparation technology letter The single, advantage that preparation efficiency is high, salient point uniformity is good；The material selection of array solder bump of the present utility model, its cost is remote Solder bump material less than Au80Sn20.

In addition, the present embodiment 1 further relates to a kind of method for packing of many I/O flip LED chips array bump packaging structures, should The step of method for packing is：

（1）The metal of multiple layer metal Rotating fields is formed using the method for evaporation, plating and chemical plating on electrode window through ray surface Change layer, then cover diffusion impervious layer in metallized layer surface；

（2）Welding resistance layer pattern is made in the printing of diffusion impervious layer surface periphery surrounding and form welding resistance window again, welding resistance window The formation of mouth constraint array solder bump, prevents the excessive formation defect of array solder bump solder during reflow；

（3）Using EFI print or the forming method of Printing Paste backflow or the implantation of laser soldered ball or plating array solder bump Array solder bump is formed on welding resistance window.

Embodiment 1

The present embodiment 1 is transformed on the basis of Fig. 1, and difference is, the present embodiment 2 be use unit for The flip LED chips array bump packaging structure of 2Pin × 2Pin.It is specific as follows：

As shown in Figures 2 and 3, in the present embodiment 1, the 2Pin of flip LED chips array bump packaging structure side is down The P electrode of LED chip is filled, the 2Pin of opposite side is the N electrode of flip LED chips, 1 discrete light emitting diode is constituted, by P Electrode is divided into 2 array salient points, and N electrode is divided into 2 array salient points and constitutes 4 array structures for array salient point； Or an electrode of flip LED chips is only divided into 2 array salient points, it is convex that another electrode does not split 1 array of reservation Point, composition contains 3 array structures of array salient point.

As shown in Figures 2 and 3, in the present embodiment 1, flip LED chips array bump packaging structure may also be side 2Pin is the P electrode of flip LED chips, and the 2Pin of opposite side is the N electrode of flip LED chips, constitutes 2 discrete luminous two Pole pipe, plants 4 array solder bumps and constitutes many I/O flip LED chips array bump packaging structures above.In Fig. 2 and Fig. 3 1 is chip functions layer and Sapphire Substrate, and 2 is chip surface passivation layer, and 3 is metal layer, and 4 is welding resistance layer pattern, and 5 is battle array Row solder bump.

Embodiment 2

The present embodiment 2 is transformed on the basis of embodiment 1, and difference is that the present embodiment 2 is to use unit It is the flip LED chips array bump packaging structure of 2Pin × 4Pin.It is specific as follows：

As shown in figure 4, it is 2Pin × 4Pin that flip LED chips array bump packaging structure uses unit（2 minimum single Unit）.On same flip LED chips（2 P/N sections）Form the battle array of 6 or 8 array solder bumps as described in Example 1 Row bump structure；Or a P/N section is uniformly distributed 4 array solder bumps as described in Example 1, another P/N sections 3 array solder bumps as described in Example 1 are distributed, on same LEDs chip（2 P/N sections）Merge and form 7 array welderings Expect the array bump structure of salient point.

Embodiment 3

The present embodiment 3 is transformed on the basis of embodiment 1 and 2, and difference is：As shown in figure 5, the implementation Example 4 is extensive many I/O flip LEDs array bump packaging structures（Multiple minimum units）, week can be fabricated in whole wafer The structure that phase property is repeated（Minimum unit is 2Pin × 2Pin）, all array solder bumps（Minimum unit is that 4 array solders are convex Point）It is in the same size to be evenly distributed on metal layer；Or the N on a minimum unit（Or p）Electrode is 1 big array weldering Material salient point, P（Or N）Electrode is 2 small array solder bumps, all array solder bumps（Minimum unit is 3 array solders Salient point）It is distributed on metal layer；Or any combination of above two minimum unit.Then array size as needed Selective cutting and splitting are carried out, the array structure of size needed for being formed.

The above, is only preferred embodiment of the present utility model, not makees any to structure of the present utility model Formal limitation.It is every any simple modification made to above example according to technical spirit of the present utility model, equivalent Change and modification, still fall within the range of the technical solution of the utility model.

Claims (10)

1. a kind of many I/O flip LED chips array bump packaging structures, it is characterised in that the electrode of single flip LED chips is Array salient point；Described array salient point includes being layed in the passivation layer of chip functions layer surface, covering electrode window through ray and embedded electricity In the window of pole and be layed on chip functions layer metal layer, be layed on metal layer and surround metal layer and form reserved There is the welding resistance layer pattern of welding resistance window, be embedded with the array solder bump higher than welding resistance window, metallization in filling in welding resistance window Layer is located at the lower section of array solder bump.

2. many I/O flip LED chips array bump packaging structures according to claim 1, it is characterised in that flip LED The array salient point minimum unit of the electrode of chip is 2Pin × 2Pin arrays；With a P electricity for the flip LED chips of P/N sections Pole is divided into 2 array salient points, and N electrode is divided into 2 array salient points, constitutes one and contains 4 array junctions of array salient point Structure.

3. many I/O flip LED chips array bump packaging structures according to claim 1, it is characterised in that flip LED The array salient point minimum unit of the electrode of chip is 2Pin × 2Pin arrays；With one one of the flip LED chips of P/N sections Electrode is divided into 2 array salient points, and another electrode is not split to form 1 array salient point, and composition contains 3 battle arrays of array salient point Array structure.

4. many I/O flip LED chips array bump packaging structures according to claim 1, it is characterised in that flip LED The array salient point minimum unit of the electrode of chip is 2Pin × 2Pin arrays；In with two the 2 of the flip LED chips of P/N sections 4 array solder bumps are planted in individual P electrode and 2 N electrodes and constitutes 4 I/O flip LED chips arrays salient point encapsulation knots Structure.

5. a kind of many I/O flip LED chips array bump packaging structures according to Claims 1-4 any one, it is special Levy and be, described array salient point is in flip LED chips surface into corner or Triangle-Profile.

6. a kind of many I/O flip LED chips array bump packaging structures according to claim 5, it is characterised in that described Metal layer by Cr/Al/Ti/Pt（Au）Or Ni/Al/Ti/Pt（Au）Or Ni/Ag/Ti/Pt（Au）Composition multilayer metal compound Structure.

7. a kind of many I/O flip LED chips array bump packaging structures according to claim 6, it is characterised in that described Metallized layer surface be additionally provided with diffusion impervious layer positioned at welding resistance bottom of window, diffusion impervious layer is by Ni（P）Metal structure group Into the electrode size of the size more than flip LED chips of diffusion impervious layer.

8. a kind of many I/O flip LED chips array bump packaging structures according to claim 7, it is characterised in that described Welding resistance window is rounded or ellipse, the size of welding resistance layer pattern is less than diffusion impervious layer size.

9. a kind of many I/O flip LED chips array bump packaging structures according to claim 8, it is characterised in that described Array solder bump be solder containing pb or lead-free tin solder or tin solder or indium-based solder or bismuthino or auri solder Any one.

10. a kind of many I/O flip LED chips array bump packaging structures according to claim 9, it is characterised in that institute The array solder bump stated is rounded square or oval spherical.