WO2009122867A1 - Semiconductor device, composite circuit device, and methods for manufacturing semiconductor device and composite circuit device - Google Patents

Semiconductor device, composite circuit device, and methods for manufacturing semiconductor device and composite circuit device Download PDF

Info

Publication number
WO2009122867A1
WO2009122867A1 PCT/JP2009/054544 JP2009054544W WO2009122867A1 WO 2009122867 A1 WO2009122867 A1 WO 2009122867A1 JP 2009054544 W JP2009054544 W JP 2009054544W WO 2009122867 A1 WO2009122867 A1 WO 2009122867A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
electrode portion
bump
semiconductor device
solid solution
Prior art date
Application number
PCT/JP2009/054544
Other languages
French (fr)
Japanese (ja)
Inventor
兼二 難波
田子　雅基
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP2010505517A priority Critical patent/JPWO2009122867A1/en
Publication of WO2009122867A1 publication Critical patent/WO2009122867A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/1148—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/11845—Chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/1191—Forming a passivation layer after forming the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13021—Disposition the bump connector being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13563—Only on parts of the surface of the core, i.e. partial coating
    • H01L2224/13564—Only on the bonding interface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13563—Only on parts of the surface of the core, i.e. partial coating
    • H01L2224/13566—Both on and outside the bonding interface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1357—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053—Bonding environment
    • H01L2224/81095—Temperature settings
    • H01L2224/81096—Transient conditions
    • H01L2224/81097—Heating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/8182—Diffusion bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Definitions

  • the present invention relates to a semiconductor device, a composite circuit device, and a manufacturing method thereof, which can cope with fine pitch bonding using a flip-chip mounting form.
  • SiP System which realized systematization by packaging a plurality of semiconductor elements such as CPU (Central Processing Unit) and memory into one package in Package
  • SiP System which realized systematization by packaging a plurality of semiconductor elements such as CPU (Central Processing Unit) and memory into one package in Package
  • This SiP structure is a structure in which the circuit surfaces of two semiconductor elements are arranged facing each other and bonded via bumps. Therefore, since both are semiconductor elements, it is possible to form fine wirings and electrodes, and to form junctions between the semiconductor elements at a fine pitch.
  • FIG. 9A and 9B are cross-sectional views showing an example of the method for manufacturing the semiconductor device described above.
  • an adhesion layer 6 and an adhesive layer 7 are formed in this order on the electrode 3, and further a semiconductor element 1 having an electrode portion on which a solder bump 15 mainly composed of Sn is formed via a barrier metal 14. Form. Similar to the semiconductor element 1, the adhesion layer 6 and the adhesive layer 7 are formed in this order on the electrode 3, and the solder bump 15 is further formed thereon via the barrier metal 14, or on the barrier metal 14.
  • a substrate 2 having an electrode portion on which an Au thin film is formed is formed.
  • the semiconductor element 1 and the substrate 2 having the above-described configuration are aligned at positions where both electrode portions face each other (FIG. 9A).
  • solder bumps 15 are formed by a plating method, height variations (volume variations) are likely to occur within the surface due to plating accuracy. Thereafter, both electrode parts are brought into contact with each other, heated and loaded to join the electrode parts together, and then a thermosetting resin that becomes the underfill resin layer 11 is sealed in the gap between the semiconductor element 1 and the substrate 2. The semiconductor device is obtained by curing [FIG. 9B].
  • the underfill resin layer 11 When the underfill resin layer 11 is formed, the semiconductor element 1 and the substrate 2 are electrically joined via both electrode portions in a state where the positions of both electrode portions coincide with each other. Further, a protective film 5 having an electrode portion forming region opened is formed on the circuit surfaces of the semiconductor element 1 and the substrate 2. Therefore, the gap between the semiconductor element 1 and the substrate 2 is wide in the electrode portion formation region and narrow in other regions. Therefore, the underfill resin layer 11 must be formed by enclosing a thermosetting resin between the semiconductor element 1 and the substrate 2 having such a gap difference. JP 2002-110726 A JP 2004-179635 A JP 2005-31188 A
  • the first problem is that solder short-circuit defects are likely to occur between adjacent solder bumps. This is caused by melting the solder and forming bumps or bonding the bumps. In the solder bump structure, the bump expands in the lateral direction in the molten state at the time of bump formation or bump bonding. Furthermore, there is variation in the accuracy of solder plating between the solder bumps. Accordingly, since the interval between adjacent bumps is narrow in the fine pitch bonding, a solder short is likely to occur in the bump forming process and the bump bonding process, and the yield may be reduced by solidifying as it is.
  • the second problem is that it is difficult to obtain sufficient bonding reliability.
  • the power consumption of LSIs has been reduced due to miniaturization of transistors and wiring.
  • there has been a limit to low power consumption and the current that flows per unit wiring does not decrease even if miniaturization advances. Occurs.
  • the electromigration phenomenon has been highlighted as a major issue.
  • the intermetallic compound layer of Sn and Ni or Cu grows at an accelerated rate due to the electromigration phenomenon and segregates, thereby generating Kirkendall voids and cracks at the interface. It is known to cause occurrence and reduce its reliability.
  • Patent Document 1 As a joining structure of fine pitch electrodes that do not use solder bumps, a structure in which Cu bumps are joined with an intermetallic compound of Sn and Cu has been proposed as disclosed in Patent Document 1, for example.
  • the metal compound layer of Sn and Cu is the joint center.
  • the reaction between Sn and Cu may cause an electromigration phenomenon when an electric current is applied, and the movement of Sn or Cu may cause separation of intermetallic compounds (multi-layering) or generation of Kirkendall voids.
  • These intermetallic compounds are special structures composed of a specific atomic ratio in the crystal structure. Therefore, they have mechanically brittle properties, cracks at the interface with the base metal, and differences in crystal structure. Therefore, there is a possibility that Kirkendall void is generated at the interface.
  • Fine pitching reduces the electrode size, so that the variation in plating at the time of bump formation and the influence on the bump shape due to the shape of the underlying electrode and the opening of the insulating film tend to appear remarkably. For this reason, a gap is likely to be generated at the bump bonding interface at the time of initial bonding. However, if mounting is performed with a high load in order to prevent the generation of such a gap, a bonding defect due to deformation of the columnar electrode may occur.
  • the shape of the bump surface is uneven due to the influence of the opening shape formed by the electrode portion and the insulating film, and each of the bumps has a plating accuracy. There is a risk that the height may be uneven between the bumps. Therefore, at the time of joining the semiconductor elements, the mounting load is set to be high in order to cancel the unevenness and height variation of the bump surface, and the semiconductor elements may be damaged.
  • Patent Document 3 proposes a structure in which a bump in which one or both of Au and Ag are formed on a Cu bump and a bump in which one or both of Pt and Pd are formed on a Cu bump are bonded.
  • a bump in which one or both of Au and Ag are formed on a Cu bump and a bump in which one or both of Pt and Pd are formed on a Cu bump are bonded.
  • Ag is used as the bonding material, there is a possibility that an insulation failure between adjacent bumps may occur due to ion migration.
  • the third problem is that voids are generated when the underfill resin layer is formed. This is because, as a state after the bonding of the solder bumps, there is a gap difference between the semiconductor element and the substrate depending on the presence or absence of the protective film between the area where the solder bumps are disposed and the area where the solder bumps are not. This gap difference causes a flow rate difference depending on the location when encapsulating the underfill resin, and air entrainment occurs due to the flow rate difference, which may cause voids at the joints and cracks at the joints starting from the voids. There is.
  • the present invention has been made to solve the above-described problems of the technology, and the object thereof is a semiconductor that can cope with a fine pitch and can obtain high reliability, particularly in a flip chip mounting form. It is to provide an apparatus and a manufacturing method thereof.
  • Another object of the present invention is to provide a composite circuit device applicable to bonding between semiconductor elements and bonding between substrates, and a method for manufacturing the same.
  • a semiconductor device includes a bonding portion in which a first electrode portion on a semiconductor element and a second electrode portion on a substrate are electrically bonded so as to face each other, and the bonding And a solid solution region including a bonding material that forms a solid solution with one or both of the constituent material of the first electrode portion and the constituent material of the second electrode portion.
  • a method for manufacturing a semiconductor device according to a first aspect of the present invention for solving the above-described problem includes a bonding portion in which the first electrode portion on the semiconductor element and the second electrode portion on the substrate are electrically bonded. Forming the first electrode portion and the second electrode portion made of a metal material selected to have a solid solution region, and aligning the first electrode portion and the second electrode portion so as to face each other; The first electrode portion and the second electrode portion are brought into pressure contact, heated in the pressure contacted state, and held in the heated state to form a solid solution region in the joint portion. .
  • the first electrode portion and the second electrode portion are formed so that one region is a Cu bump and the other component material is Au so that the first electrode portion and the second electrode portion are formed. Aligning so as to face each other, bringing the first electrode part and the second electrode part into pressure contact, heating in the pressure contacted state, holding in the heated state, and holding the heated state A solid solution region is formed at the joint.
  • the composite circuit device includes a joint part electrically joined so that a first electrode part on a circuit board and a second electrode part on another circuit board face each other, and the joint part And a solid solution region containing a bonding material that forms a solid solution with one or both of the constituent material of the first electrode portion and the constituent material of the second electrode portion.
  • the method of manufacturing the composite circuit device of the present invention is selected so that the joint portion where the first electrode portion on the circuit board and the second electrode portion on the other circuit board are electrically joined has a solid solution region.
  • the present invention it is possible to provide a semiconductor device, a composite circuit circuit device, and a method for manufacturing the same that can cope with a fine pitch and can obtain high reliability particularly in a flip chip mounting form.
  • the semiconductor device of the present invention has a joint part in which the first electrode part on the semiconductor element and the second electrode part on the substrate are electrically joined so as to face each other. And the joining part is comprised so that the solid solution area
  • the concentration of the joined portion is inclined from the joining interface. It becomes the graded layer.
  • the solid solution region is an inclined layer in which the concentration of one or both of the constituent material of the first electrode portion and the constituent material of the second electrode portion is inclined.
  • the obtained semiconductor device does not become a discontinuous bonding interface even when a diffusion reaction or an electromigration phenomenon progresses, a starting point such as a defect or a crack does not occur, and a structure with high bonding reliability can be obtained.
  • the solid solution region is preferably a solid solution layer of Cu and Au.
  • the constituent material of the first electrode part and the constituent material of the second electrode part may be Cu, the bonding material may be Au, and the solid solution region may be made of Cu and Au.
  • the constituent material of the first electrode portion and the constituent material of the second electrode portion may be configured such that one is Cu and the other is Au, and the solid solution region is made of Cu and Au.
  • first electrode portion and the second electrode portion may be Cu bumps
  • the bonding material may be Au
  • the solid solution region may be made of Cu bumps and Au.
  • the first electrode portion and the second electrode portion may be configured such that one of them is a Cu bump and the other constituent material is Au, and the solid solution region is made of Cu and Au.
  • substrate may be a semiconductor element.
  • a protective film may not be formed on the semiconductor element and the substrate, or a protective film having a depressed central portion between adjacent junctions may be formed.
  • one or both of the first electrode portion and the second electrode portion may have a bump structure, and a protective film that is lower than the height of the bump and has a depressed center may be provided between adjacent joint portions.
  • first electrode portion and the second electrode portion may have a bump structure
  • the bonding portion may be formed of a bump having a flattened bonding surface on the bonding portion side of the bump.
  • constituent material of the solid solution region may be configured to be a solid solution type material.
  • the first electrode portion and the second electrode made of a metal material selected so that the joint portion between the first electrode portion and the second electrode portion has a solid solution region.
  • An electrode part is formed and aligned so that the first electrode part and the second electrode part face each other.
  • a 1st electrode part and a 2nd electrode part are made to press-contact, and it heats in the state made to press-contact, hold
  • the method for manufacturing a semiconductor device of the present invention it is possible to generate a solid solution layer by applying heat from the semiconductor element side, so even when a plurality of semiconductor elements are continuously bonded to one substrate, It is possible to suppress the load caused by heating and the change in composition due to the aging of the electrode part, and it is possible to prevent a decrease in reliability due to a local change in strength due to segregation or the like.
  • the surface of the Cu bumps is flattened to make the height uniform.
  • the electrode portions having a flat surface can be formed, so that the electrode portions can be brought into contact with each other with a low mounting load. As a result, there is no damage to the semiconductor element.
  • an adhesion layer and an adhesive layer are laminated so as to cover one or both electrodes of the semiconductor element and the substrate, a resist is formed on the adhesive layer, and the resist above the electrode is removed.
  • a resist is formed on the adhesive layer, and the resist above the electrode is removed.
  • an opening is formed, and the electrode is formed by filling the opening with a metal material.
  • the electrode part formed in the opening part and the resist other than the opening part are processed to flatten the electrode part, supply a bonding material for forming a solid solution region on the electrode part, and the resist after the flattening process is applied.
  • the adhesive layer and the adhesive layer other than the electrode portion are removed.
  • an adhesive layer and an adhesive layer are laminated so as to cover one or both electrodes of the semiconductor element and the substrate, a resist is formed on the adhesive layer, and the resist above the electrode is formed. Is removed to form an opening, and the opening is filled with a metal material to form an electrode portion. Then, the remaining resist is removed, the adhesion layer and the adhesive layer other than the electrode part are removed, a protective film is formed so as to cover the electrode part, the electrode part and the protective film are processed, the electrode part is flattened, and the electrode A bonding material for forming a solid solution region is supplied on the part, and a predetermined amount of the protective film is uniformly removed to project the electrode part.
  • the etching rate of the resist or the protective film is faster, and the resist or the protective film may be processed to be lower than the height of the electrode part between the joints and to be depressed in the center.
  • the supply of the bonding material onto the electrode part may be performed by an electroless plating method.
  • the electrode part may be a Cu bump and the bonding material may be Au.
  • a thin film of Au is formed on the Cu bump using a substitution Au plating bath, and further formed to a desired film thickness using a combination of substitution and reduction type Au plating bath. May be.
  • the first electrode part and the second electrode part are formed so that the joint part between the first electrode part and the second electrode part has a solid solution region.
  • an adhesion layer and an adhesion layer are laminated so as to cover one or both electrodes of a semiconductor element and a substrate, a resist is formed on the adhesion layer, and a resist above the electrodes is formed. Are removed to form openings, and the openings are filled with Cu to form Cu bumps. Thereafter, the Cu bump formed in the opening and the resist other than the opening are processed to flatten the electrode part, the resist after the flattening process is removed, and the adhesion layer and the adhesive layer other than the Cu bump are removed.
  • an adhesion layer and an adhesion layer are laminated so as to cover one or both electrodes of the semiconductor element and the substrate, a resist is formed on the adhesion layer, and the upper part of the electrode is formed.
  • the resist is removed to form openings, and the openings are filled with Cu to form Cu bumps.
  • the remaining resist is removed, the adhesion layer and the adhesive layer other than the Cu bump are removed, a protective film is formed so as to cover the Cu bump, the Cu bump and the protective film are processed, the Cu bump is flattened, and protection is performed. A predetermined amount of the film is removed uniformly to project the Cu bumps.
  • the etching rate of the resist or the protective film is faster, and the resist or the protective film may be processed so as to be lower than the height of the electrode part between the joints and the center is depressed.
  • FIG. 1 is a sectional view showing a semiconductor device according to the first embodiment of the present invention.
  • the semiconductor device shown in FIG. 1 has Cu bumps 8 on the electrodes 3 provided on the semiconductor element 1, and also has Cu bumps 8 on the electrodes 3 provided on the substrate 2.
  • a solid solution layer 10 made of Cu and Au.
  • the solid solution layer 10 is a layer existing in a region (solid solution region) in a joint portion between the Cu bumps 8 and 8 on both the semiconductor element 1 side and the substrate 2 side.
  • the solid solution layer 10 has a Cu concentration. Is an inclined layer that is uniformly inclined.
  • the thickness of the solid solution layer 10 is 0.5 ⁇ m and the thickness of the Cu bump 8 is 1 ⁇ m or more, preferably 3 ⁇ m or more, long-term storage reliability in a high-temperature storage environment is improved.
  • An underfill resin layer 11 is formed between the semiconductor element 1 and the substrate 2.
  • an adhesion layer 6 and an adhesive layer 7 are provided in this order on the electrode 3 provided on the semiconductor element 1 and on the electrode 3 provided on the substrate 2. 8 is provided on the adhesive layer 7.
  • An insulating film 4 is provided on the surface of the semiconductor element 1 and the substrate 2 other than the electrode 3.
  • the solid solution layer 10 includes a case where the concentration of the material constituting the solid solution is uniformly inclined, the boundary with the Cu bump 8 may not be clear. Therefore, in the present application, for example, a region including Cu of the Cu bump 8 and Au as a bonding material is referred to as a solid solution region, and the solid solution region is present in the bonded portion.
  • the electrode portion refers to a portion from the electrode 3 to the Cu bump 8, mainly the bump 8 provided on the electrode 3, and the first electrode portion in the semiconductor element 1 which is a circuit board on one side.
  • the electrode part is indicated, and the second electrode part is an electrode part in the substrate 2 which is a circuit board on the other side.
  • a junction part shall point out the part in which Cu bump 8 and 8 which opposes joined and the solid solution layer 10 was formed.
  • the electrodes of the semiconductor element 1 and the substrate 2 are joined to each other through the solid solution layer 10 of Cu and Au.
  • the solid solution layer 10 is formed on the semiconductor element 1 side and the substrate 2 side.
  • the Cu bumps 8 and 8 are inclined layers (also referred to as reaction layers) in which the Cu concentration gradient is uniformly inclined, so that there is no discontinuity and excellent mechanical strength.
  • the connection portion in which the solid solution layer 10 is formed does not become a discontinuous bonding interface even when a diffusion reaction or an electromigration phenomenon proceeds, so that no starting point such as a defect or a crack is generated. Therefore, reliability can be improved.
  • an electrode 3 made of Al or the like provided on the circuit surface and an insulating film 4 made of SiON, SiO 2 or the like covering the circuit surface in a form having an opening on a part of the electrode 3 are provided.
  • a semiconductor element 1 and a substrate 2 are prepared or prepared.
  • An adhesion layer 6 made of Ti or the like and an adhesive layer 7 made of Cu or the like are formed on the entire surface of the electrode 3 and the insulating film 4 by sputtering or the like on the electrode formation surface side of the semiconductor element 1 and the substrate 2.
  • a photosensitive resist 12 is formed on the adhesive layer 7 by spin coating or the like, and only the resist 12 above the electrode is removed by exposure and development, and an opening having a desired size is formed on the electrode 3.
  • Cu that becomes the bumps 8 is deposited in the openings of the resist 12 by an electrolytic plating method or the like [FIG. 2A]. At this time, the height of the Cu bump 8 may vary between the electrodes 3.
  • the Cu bump 8 is flattened.
  • various kinds of flattening such as a mechanical polishing method, a chemical mechanical polishing method (CMP), and a grinding process are performed on the Cu bump 8 that is an electrode portion formed in the opening and the resist 12 other than the Cu bump 8. This is performed using a processing means [FIG. 2B].
  • an Au thin film that is a bonding material 9 for finally forming a solid solution region with Cu is formed on the Cu bump 8 [FIG. 2C].
  • Au having a desired plating thickness can be formed using a substitution Au plating bath.
  • an Au thin film having a desired plating thickness may be formed using a combination of substitution and reduction type Au plating bath.
  • the thickness of the bonding material 9 made of Au or the like is not particularly limited, for example, a range of 0.03 ⁇ m to 0.5 ⁇ m can be exemplified, but other thicknesses may be used.
  • the semiconductor element 1 and the substrate 2 used in the semiconductor device according to the present embodiment can be obtained. These are obtained in a mode in which a bonding material 9 made of Au is provided on the bonding surface of the planarized Cu bump 8 [FIG. 2D].
  • the semiconductor element 1 and the substrate 2 on which the Cu bumps 8 and the bonding material 9 are formed alignment is performed so that the positions of both electrode portions coincide (FIG. 2E).
  • the semiconductor element 1 is separated into a desired size by dicing.
  • the back surface of the semiconductor element 1 may be processed by a polishing method or the like to reduce the thickness to a desired thickness.
  • the substrate 2 may be singulated or thinned.
  • the substrate side may be preheated to room temperature or to the extent that the reaction between Cu and Au does not proceed rapidly, and heating for reacting Cu and Au from the semiconductor element 1 side may be performed.
  • an underfill resin layer 11 is formed by injecting a resin between the semiconductor element 1 and the substrate 2 to obtain the semiconductor device according to the first embodiment of the present invention [FIG. 2F]. .
  • the substrate It is possible to suppress a load due to heating to 2 and a change in composition due to a change with time of the electrode part, and reliability deterioration due to a local change in strength due to segregation or the like does not occur.
  • each electrode portion has a uniform height and a flat surface.
  • the opposing electrode portions can be brought into contact with each other with a low mounting load setting, so that damage to the semiconductor element 1 can be suppressed.
  • the gap between the semiconductor element 1 and the substrate 2 can be kept wide and there is no gap difference. Since the resin sealing property can be improved and generation of voids in the resin can be suppressed, high reliability can be obtained.
  • the bonding material 9 made of Au is supplied before the adhesion layer 6 and the adhesive layer 7 are removed from unnecessary portions, when the bonding material 9 is supplied by electroless plating, between the electrodes. There is no potential difference. Therefore, variations in plating thickness and non-precipitation due to a potential difference between the Cu bumps can be suppressed, and a stable bonding state can be obtained between the Cu bumps.
  • the resist 12 is formed, the Cu bumps 8 are flattened, and then a bonding material 9 made of Au is formed. Thereafter, the resist 12 is removed, so that Cu polishing debris can be removed from the semiconductor element 1. And hardly remain on the circuit surface of the substrate 2. Therefore, it is possible to suppress the occurrence of insulation failure or the like in the semiconductor device and improve reliability.
  • a structure in which the semiconductor element 1 and the substrate 2 are joined is shown.
  • a composite circuit device in which the semiconductor elements 1 and 1 are joined may be used, or a composite circuit in which the substrates 2 and 2 are joined. It may be a device.
  • the bonding material 9 made of Au is supplied to both the semiconductor element 1 and the substrate 2, but only one of the electrode portions may be provided. Furthermore, only one of the electrode part of the semiconductor element 1 and the electrode part of the substrate 2 is composed of a bonding material 9 made of Cu bumps 8 and Au, and the other is formed with a Cu electrode without a bump structure. It may be a structure in which Further, only one of the electrode portion of the semiconductor element 1 and the electrode portion of the substrate 2 is constituted by the Cu bump 8, the other is not formed with a bump structure, a Cu electrode is formed, and a bonding material made of Au on the Cu electrode. 9 may be formed and both may be joined.
  • the bonding structure is formed through the solid solution layer 10 of Cu and Au.
  • Au bump and Pt, Au bump and Pd, Cu bump and Pt, Cu bump and A combination of a bump material such as Pd or Co bump and Pd and a bonding material may be used, and the solid solution layer 10 may be formed by a combination thereof, and a bonding structure via the solid solution layer 10 may be used.
  • the constituent material of such a solid solution region is preferably made of a solid solution type material.
  • FIG. 3 is a sectional view showing a semiconductor device according to the second embodiment of the present invention. As shown in FIG. 3, the present embodiment is different from the first embodiment in that an arc-shaped protective film 5 whose center is depressed is formed between adjacent Cu bumps 8 and 8. is there.
  • the adhesion between the semiconductor element 1 and the substrate 2 and the underfill resin layer 11 is improved, and the protective film 5 includes the semiconductor element 1 and the substrate 2. Since it functions as a relaxation layer with respect to the stress caused by the difference in linear expansion, it is possible to improve the reliability.
  • the surface of the protective film 5 has an arc shape in which the center is depressed between the adjacent bumps 8 and 8, a wide space can be secured between the semiconductor element 1 and the substrate 2 after bonding. As a result, it is possible to secure the encapsulating property of the underfill resin, suppress the generation of voids in the resin, and obtain high reliability.
  • FIG. 4A to 4H are process diagrams showing a method for manufacturing a semiconductor device according to the present embodiment.
  • the process is the same as that of the first embodiment up to the step of depositing Cu to be the bumps 8 in the openings of the resist 12 [FIG. 4A].
  • the remaining resist 12 is removed, and the adhesion layer 6 and the adhesion layer 7 formed except for under the bumps 8 are removed using a wet etching method or the like [FIG. 4B].
  • a protective film 5 made of a thermosetting polyimide resin or the like is supplied and cured using a spin coat method or the like so as to cover the bumps 8 [FIG. 4C].
  • the protective film 5 and the bumps 8 are processed by various flattening means such as a mechanical polishing method, a chemical mechanical polishing method (CMP), and a grinding process to flatten the bumps 8 [FIG. 4D].
  • the polishing or grinding conditions are adjusted so that the polishing amount or the grinding amount of the protective film 5 is larger than the etching rate of Cu, and polishing or grinding is performed. It is processed so as to form an arc shape with the center recessed.
  • the degree of the depression is not particularly limited, but may be any degree as long as the underlying insulating film 4 or the like is not exposed from the protective film 5 even after the protective film 5 is uniformly removed in a subsequent step.
  • a bonding material 9 made of Au is formed on the bumps 8 by using an electroless plating method or the like [FIG. 4E].
  • Au having a desired plating thickness can be formed using a substitution Au plating bath.
  • an Au thin film having a desired plating thickness may be formed using a combination of substitution and reduction type Au plating bath.
  • the protective film 5 is uniformly removed by a dry etching method or the like, and the tip end side of the bump 8 is protruded, so that the semiconductor element 1 and the substrate 2 used in the embodiment of the present invention are planarized.
  • a structure of the bonding material 9 composed of the Cu bump 8 and Au is obtained [FIG. 4F].
  • the semiconductor element 1 and the substrate 2 on which the bumps 8 and the bonding material 9 are formed alignment is performed so that the positions of both the electrodes 3 and 3 coincide [FIG. 4G].
  • the semiconductor element 1 is separated into a desired size by dicing.
  • the back surface of the semiconductor element 1 may be processed by a polishing method or the like to reduce the thickness to a desired thickness.
  • the substrate 2 may be singulated or thinned.
  • the bump 8 since the bump 8 is planarized in a state in which the adhesion between the bump 8 and the protective film 5 is obtained, the bump 8 and the protective film 5 are peeled off during processing, polished, or ground. It is possible to suppress bump shape defects such as the above and bump loss. Further, by forming the protective film 5, it is possible to improve the protection of the circuit surfaces of the semiconductor element 1 and the substrate 2, and it is possible to suppress damage during the manufacturing process.
  • FIG. 5 is a cross-sectional view of a semiconductor device according to the third embodiment of the present invention. As shown in FIG. 5, this embodiment is different from the first embodiment in that a solid solution layer 10 of Cu and Au is also formed on the side wall of the bump 8 protruding from the protective film 5 of the semiconductor element 1 and the substrate 2. This is different from the second embodiment.
  • FIGS. 6A to 6H are process diagrams showing a method of manufacturing a semiconductor device according to the third embodiment of the present invention.
  • the process up to flattening of the bumps 8 is the same as in the second embodiment (FIGS. 6A to 6D).
  • the protective film 5 is uniformly removed by a predetermined amount using a dry etching method or the like, and the tip side of the bump 8 is projected [FIG. 6E].
  • a bonding material 9 made of Au is formed at the tip of the bump 8.
  • the Cu bumps 8 of the semiconductor element 1 and the substrate 2 in the present embodiment have a structure in which the bonding material 9 is formed on the flattened tip side surface [FIG. 6F].
  • the semiconductor element 1 is separated into a desired size by dicing.
  • the back surface of the semiconductor element 1 may be processed by a polishing method or the like to be thinned to a desired thickness.
  • the substrate 2 may be singulated or thinned.
  • pressurization and heating are performed in the same manner as in the first embodiment, and a solid solution layer 10 of Cu and Au is formed between the bumps 8 and 8 on the semiconductor element 1 and the substrate 2. Are joined.
  • an underfill resin layer 11 is formed between the semiconductor element 1 and the substrate 2 to obtain the semiconductor device of this embodiment [FIG. 6H].
  • the protective film 5 is first removed uniformly by a predetermined amount and the bumps 8 are projected, so that the region where the bonding material 9 is formed by plating is also increased on the side surface in the vicinity of the tip that continues to the tip. Even in a fine bump having a small surface area, the starting point of the plating reaction can be easily performed, and supply variation and non-deposition of the bonding material 9 made of Au can be suppressed. Therefore, it is possible to obtain a stable bonding state between the bumps.
  • the protective film 5 is first uniformly removed by a predetermined amount, and the tip end side of the bump is protruded, followed by the step of forming the bonding material 9 made of Au.
  • the bonding material 9 made of Au.
  • FIG. 7 is a sectional view of a semiconductor device according to the fourth embodiment of the present invention.
  • the present embodiment is different from the first, second, and third embodiments in that the electrode portion of the substrate 2 facing the electrode portion of the semiconductor element 1 is Au bump 13. It is the point comprised by.
  • the bumps 8 of the semiconductor element 1 and the Au bumps 13 of the substrate 2 are joined via a solid solution layer 10 of Cu and Au.
  • the solid solution layer 10 is an inclined layer (reaction layer) in which the concentration of Cu is uniformly inclined from the Cu bump 8 of the semiconductor element 1 toward the Au bump 13 of the substrate 2.
  • An underfill resin layer 11 is formed between the semiconductor element 1 and the substrate 2.
  • the electrode portions of the semiconductor element 1 and the substrate 2 are joined to each other through the solid solution layer 10 of Cu and Au.
  • the mechanical strength is excellent.
  • a discontinuous bonding interface does not occur, so that no starting point such as a defect or a crack occurs. Therefore, reliability can be improved.
  • FIGS. 8A to 8E are process diagrams showing a method for manufacturing a semiconductor device used in the present embodiment.
  • an electrode 3 made of Al or the like provided on the circuit surface and an insulating film 4 made of SiON, SiO 2 or the like covering the circuit surface in a form having an opening on a part of the electrode 3 are provided.
  • a substrate 2 is prepared or prepared.
  • An adhesion layer 6 made of Ti or the like and an adhesive layer 7 made of Cu or the like are formed on the entire surface of the electrode 3 and the insulating film 4 on the electrode forming side of the substrate 2 by sputtering or the like.
  • a photosensitive resist 12 is supplied onto the adhesive layer 7 by spin coating or the like, and only the resist 12 above the electrode is removed by exposure and development, and an opening having a desired size is formed on the electrode 3. Further, Au serving as the bumps 13 is deposited in the openings of the resist 12 by an electrolytic plating method or the like [FIG. 8A]. At this time, the height of the Au bump 13 may vary between the electrodes 3.
  • the Au bump 13 is flattened.
  • various kinds of flattening such as a mechanical polishing method, a chemical mechanical polishing method (CMP), and a grinding process are performed on the Au bump 13 which is an electrode portion formed in the opening and the resist 12 other than the Au bump 13. This is done using the processing means [FIG. 8B].
  • the substrate 2 used in this embodiment can be obtained.
  • the substrate 2 has a structure including a flattened Au bump 13 as an electrode part [FIG. 8C].
  • the substrate 2 having the structure of the Au bump 13, the planarized Cu bump 8 shown in the first embodiment, and the bonding material 9 made of Au formed on the front end surface of the Cu bump 8; Positioning is performed using the semiconductor element 1 having a position so that the positions of both electrode portions coincide with each other [FIG. 8D]. At this time, the semiconductor element 1 is separated into a desired size by dicing. Further, the back surface of the semiconductor element 1 may be processed by a polishing method or the like to be thinned to a desired thickness. Similarly, the substrate 2 may be singulated or thinned.
  • the pressure is applied so that the bonding material 9 surface of the Cu bump 8 and the tip surface of the Au bump 13 are all in contact with each other, and the Cu bump 8, the bonding material 9 and the Au bump 13 are heated to a predetermined temperature or higher.
  • the substrate side may be preheated to room temperature or to the extent that the reaction between Cu and Au does not proceed rapidly, and heating for reacting Cu and Au from the semiconductor element 1 side may be performed.
  • an underfill resin layer 11 is formed by injecting a resin between the semiconductor element 1 and the substrate 2 to obtain a semiconductor device according to the fourth embodiment of the present invention [FIG. 8E]. .
  • either one of the bumps of the electrode part of the semiconductor element 1 and the electrode part of the substrate 2 is made of Au, which is easier to deform than Cu, the bump surfaces are bonded to each other with a lower mounting load setting at the time of bonding. As a result, damage to the semiconductor element 1 can be suppressed.
  • the structure in which the semiconductor element 1 and the substrate 2 are joined is shown.
  • the semiconductor elements 1 and 1 may be joined together or the substrates 2 and 2 may be joined together.
  • the structure of the planarized Cu bump 8 and the bonding material 9 made of Au shown in the first embodiment is used, but the structure shown in the second and third embodiments is used. It may be.
  • the structures shown in the first to third embodiments are used for the semiconductor element 1 or the substrate 2, a structure in which the bonding material 9 made of Au is not supplied may be adopted.
  • the Au bump 13 may be structured to have a sharpened structure composed of a structure in which the planarization process is not performed or a structure in which the tip side of the Au bump 13 is pointed.
  • a semiconductor element 1 and a substrate 2 having an insulating film 4 were prepared.
  • An adhesion layer 6 made of Ti and an adhesive layer 7 made of Cu were formed on the entire surface of the electrode 3 and the insulating film 4 by sputtering on the electrode formation surface side of the semiconductor element 1 and the substrate 2.
  • a photosensitive resist 12 was formed on the adhesive layer 7 by spin coating, and only the resist 12 above the electrode was removed by exposure and development, and an opening with a desired size was formed on the electrode 3.
  • Cu serving as the bumps 8 was deposited in the openings of the resist 12 by electrolytic plating so as to have a thickness of 8 ⁇ m [FIG. 6A].
  • the height of the bump 8 was varied by ⁇ 2 ⁇ m between the electrodes 3.
  • the remaining resist 12 was removed by an etching method, and the adhesion layer 6 and the adhesive layer 7 formed other than under the bumps 8 were removed by a wet etching method (FIG. 6B).
  • thermosetting polyimide resin was supplied by a spin coating method so as to cover the bumps 8, and was thermally cured to form the protective film 5 [FIG. 6C].
  • the bump 8 was covered with the protective film 5 having a thickness of at least about 1 ⁇ m.
  • the protective film 5 and the bumps 8 were polished and planarized by using a chemical mechanical polishing method until the height of the bumps 8 became 5 ⁇ m [FIG. 6D].
  • the slurry and the processing conditions are adjusted so that the polishing amount of the protective film 5 is larger than the etching rate of Cu, and the center of the surface of the protective film 5 after processing is between the adjacent bumps 8 and 8. It was made to become a hollow arc shape.
  • the protective film 5 was degenerated by a dry etching method, and the tip side of the bump 8 was protruded by 2 ⁇ m [FIG. 6E].
  • the tip surface of the flattened Cu bump 8 and the side surface near the tip connected to the tip surface are also provided.
  • a bonding material 9 made of Au was formed [FIG. 6F].
  • an Au film is formed with a thickness of 0.03 ⁇ m on the tip surface of the Cu bump 8 and the side surface near the tip connected to the tip surface using a substitution Au plating bath, and then substitution and reduction are performed.
  • the final bonding material 9 was formed to a thickness of 0.1 ⁇ m using a combination type Au plating bath.
  • the reaction between Au, which is the bonding material 9 of both the semiconductor element 1 and the substrate 2, and Cu, which is the material of both the bumps 8, proceeds, and both the bumps 8, 8 Cu and Au were formed into a solid solution between them, and were joined via the formed solid solution layer 10.
  • the state of the solid solution layer 10 after the bonding is inclined so that the Cu concentration decreases from both the bumps 8 and 8 toward the bonding center, and the Cu concentration at the bonding center is larger than the bulk concentration of the Cu bump 8. It was about 10at%. Further, the estimated thickness of the solid solution layer 10 was about 0.5 ⁇ m.
  • thermosetting resin to be the underfill resin layer 11 is poured between the semiconductor element 1 and the substrate 2 at a temperature at which the substrate 2 becomes 70 ° C., and heated by heating at an environmental temperature of 150 ° C. for 1 hour.
  • the semiconductor device of this example was obtained by curing [FIG. 6H].
  • the thickness of Au as the bonding material is 0.1 ⁇ m and the thickness of the solid solution layer formed by bonding is 0.5 ⁇ m.
  • the crystal depending on the thickness of the bonding material and bump plating conditions is used. Their thickness varies depending on the size of the grains and joining conditions.
  • the thickness of Au which is a bonding material, also has a function of preventing the oxidation of the Cu surface in the bonding process. Therefore, it is preferable that the thickness be at least 0.03 ⁇ m on one electrode side. Further, the upper limit of the thickness of Au needs to give a large energy in order to react with all Cu of the electrode or bump when the total thickness of Au supplied to the surfaces of both electrode parts exceeds 1 ⁇ m. It is specified because it is expensive and Au is not preferable in terms of productivity and economy.
  • the thickness of the solid solution layer formed when 0.1 ⁇ m of Au as a bonding material is supplied to both electrodes or bump surfaces of the semiconductor element 1 and the substrate 2 is about 0.5 ⁇ m. It is considered that the thickness of Cu is required to be at least 1 ⁇ m or more on one electrode side. In other words, the thickness of Cu with respect to the thickness of Au is 1:10 or more, and more preferably 1:30 or more. Furthermore, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention described above.
  • the present invention can be applied to a semiconductor device, a composite circuit device, and a manufacturing method thereof that can cope with fine pitch bonding using a flip-chip mounting form.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

A semiconductor device applicable to fine pitch with high reliability for flip-chip mounting is provided. A composite circuit device and methods for manufacturing the semiconductor device and the composite circuit device are also provided. The semiconductor device has a connecting section (10) where an electrode (3) on a semiconductor element (1) and an electrode (3) on a substrate (2) face each other and are electrically connected. Furthermore, the semiconductor device has a solid solution layer (10), which exists in the connecting section (10) and contains a connecting material which forms a solid solution with one or both of a constituent material of the electrode (3) on the semiconductor element (1) and a constituent material of the electrode (3) on the substrate (2).

Description

半導体装置、複合回路装置及びそれらの製造方法Semiconductor device, composite circuit device and manufacturing method thereof
　本発明は、特にフリップチップ方式の実装形態を用いた微細ピッチ接合に対応できる、半導体装置、複合回路装置及びそれらの製造方法に関する。 The present invention relates to a semiconductor device, a composite circuit device, and a manufacturing method thereof, which can cope with fine pitch bonding using a flip-chip mounting form.
　近年、半導体装置の高性能化、高機能化に対応するパッケージ構造として、ＣＰＵ（中央演算処理装置）やメモリ等の複数個の半導体素子を１パッケージ化することでシステム化を実現したＳｉＰ（System　in　Package）構造が知られている。このＳｉＰ構造における半導体素子の実装形態では、多ピン化や電極間ピッチの微細化に対応するために、半導体素子の回路面上に形成されたバンプを介して基板上に実装するフリップチップ方式が用いられている。また近年では、ＣＰＵとメモリ間におけるデータ転送能力の向上等を目的としたチップ・オン・チップ（Chip　on　Chip）型のＳｉＰ構造が採用されている。このＳｉＰ構造は、２つの半導体素子の回路面が向き合った状態で配置され、バンプを介し接合されている構造である。従って、両方共に半導体素子であるため、微細な配線や電極を形成することができ、半導体素子間における接合部を微細ピッチに形成することが可能である。 In recent years, as a package structure corresponding to higher performance and higher functionality of semiconductor devices, SiP (System which realized systematization by packaging a plurality of semiconductor elements such as CPU (Central Processing Unit) and memory into one package in Package) structure is known. In the mounting form of the semiconductor element in this SiP structure, in order to cope with the increase in the number of pins and the reduction in the pitch between the electrodes, there is a flip chip method in which the semiconductor chip is mounted on the substrate via bumps formed on the circuit surface of the semiconductor element It is used. In recent years, a chip-on-chip (SiP) type SiP structure has been adopted for the purpose of improving the data transfer capability between the CPU and the memory. This SiP structure is a structure in which the circuit surfaces of two semiconductor elements are arranged facing each other and bonded via bumps. Therefore, since both are semiconductor elements, it is possible to form fine wirings and electrodes, and to form junctions between the semiconductor elements at a fine pitch.
　図９Ａ及び図９Ｂは、上記した半導体装置の製造方法の一例を示す断面図である。初めに、電極３上に密着層６と接着層７がその順で形成され、さらにその上にバリアメタル１４を介してＳｎを主成分とするハンダバンプ１５が形成された電極部を有する半導体素子１を形成する。半導体素子１と同様に、電極３上に密着層６と接着層７がその順で形成され、さらにその上にバリアメタル１４を介しハンダバンプ１５が形成された電極部、もしくはそのバリアメタル１４上にＡｕ薄膜が形成された電極部を具備する基板２を形成する。上記の構成を有する、半導体素子１と基板２とを、両方の電極部が対向する位置に位置合わせを行う〔図９Ａ〕。ここで、ハンダバンプ１５はめっき法で形成されていることから、めっき精度により面内で高さバラツキ（体積バラツキ）が生じ易い。その後、両方の電極部を当接し、加熱、荷重を加えて電極部同士を接合した後、半導体素子１と基板２との間の隙間にアンダーフィル樹脂層１１となる熱硬化性樹脂を封入し、硬化させることで半導体装置を得ている〔図９Ｂ〕。 9A and 9B are cross-sectional views showing an example of the method for manufacturing the semiconductor device described above. First, an adhesion layer 6 and an adhesive layer 7 are formed in this order on the electrode 3, and further a semiconductor element 1 having an electrode portion on which a solder bump 15 mainly composed of Sn is formed via a barrier metal 14. Form. Similar to the semiconductor element 1, the adhesion layer 6 and the adhesive layer 7 are formed in this order on the electrode 3, and the solder bump 15 is further formed thereon via the barrier metal 14, or on the barrier metal 14. A substrate 2 having an electrode portion on which an Au thin film is formed is formed. The semiconductor element 1 and the substrate 2 having the above-described configuration are aligned at positions where both electrode portions face each other (FIG. 9A). Here, since the solder bumps 15 are formed by a plating method, height variations (volume variations) are likely to occur within the surface due to plating accuracy. Thereafter, both electrode parts are brought into contact with each other, heated and loaded to join the electrode parts together, and then a thermosetting resin that becomes the underfill resin layer 11 is sealed in the gap between the semiconductor element 1 and the substrate 2. The semiconductor device is obtained by curing [FIG. 9B].
　アンダーフィル樹脂層１１の形成時において、半導体素子１と基板２とは、両方の電極部の位置が一致した状態で両方の電極部を介して電気的に接合されている。また、半導体素子１と基板２の回路面上には電極部形成領域を開口した保護膜５が形成されている。そのため、半導体素子１と基板２との間の隙間は、電極部形成領域では広く、その他の領域では狭くなっている。従って、こうしたギャップ差のある半導体素子１と基板２との間に熱硬化性樹脂を封入してアンダーフィル樹脂層１１を形成しなければならない。
特開２００２－１１０７２６号公報 特開２００４－１７９６３５号公報 特開２００５－３１１１８８号公報 When the underfill resin layer 11 is formed, the semiconductor element 1 and the substrate 2 are electrically joined via both electrode portions in a state where the positions of both electrode portions coincide with each other. Further, a protective film 5 having an electrode portion forming region opened is formed on the circuit surfaces of the semiconductor element 1 and the substrate 2. Therefore, the gap between the semiconductor element 1 and the substrate 2 is wide in the electrode portion formation region and narrow in other regions. Therefore, the underfill resin layer 11 must be formed by enclosing a thermosetting resin between the semiconductor element 1 and the substrate 2 having such a gap difference.
JP 2002-110726 A JP 2004-179635 A JP 2005-31188 A
　しかしながら、上記のような構造には幾つかの問題点がある。 However, the above structure has several problems.
　第１の課題は、隣接するハンダバンプ間でハンダのショート不良が発生し易いことである。この原因は、ハンダを溶融させてバンプ形成したりバンプ接合したりすることに起因する。ハンダバンプ構造では、バンプ形成時やバンプ接合時の溶融状態において、バンプは横方向への広がりが生じる。さらに、各ハンダバンプ間では、ハンダめっきの精度の点でもバラツキがある。従って、微細ピッチの接合では隣接するバンプ間の間隔が狭いことから、バンプ形成工程やバンプ接合工程においてハンダショートが発生し易く、そのまま凝固してしまうことで歩留まりが低下するおそれがある。 The first problem is that solder short-circuit defects are likely to occur between adjacent solder bumps. This is caused by melting the solder and forming bumps or bonding the bumps. In the solder bump structure, the bump expands in the lateral direction in the molten state at the time of bump formation or bump bonding. Furthermore, there is variation in the accuracy of solder plating between the solder bumps. Accordingly, since the interval between adjacent bumps is narrow in the fine pitch bonding, a solder short is likely to occur in the bump forming process and the bump bonding process, and the yield may be reduced by solidifying as it is.
　第２の課題は、十分な接合信頼性を得にくいということである。ＬＳＩはトランジスタや配線が微細化されることによって消費電力などが低減されてきたが、近年では低電力化に限界が生じ、微細化が進展しても単位配線あたりに流れる電流は低減されないという現象が発生する。このため、エレクトロマイグレーション現象が大きな課題としてクローズアップされている。これまでハンダによって接合されたフリップチップ実装部分では、ＳｎとＮｉもしくはＣｕとの金属間化合物層がエレクトロマイグレーション現象によって加速的に成長し、偏析することで、カーケンダルボイドの発生や界面でのクラック発生を引き起こし、その信頼性が低下することが知られている。今後、電極の微細化は進むが、半導体素子の低電力化は大きく進展しないため、バンプ当たりの電流密度は増加する傾向にある。そのため、１バンプ当りに流れる電流（電流密度）が増加することから、ますますエレクトロマイグレーションによるＳｎとＮｉとの金属間化合物層の偏析並びにカーケンダルボイドの発生が顕著になり、信頼性が低下してしまうおそれがある。 The second problem is that it is difficult to obtain sufficient bonding reliability. The power consumption of LSIs has been reduced due to miniaturization of transistors and wiring. However, in recent years, there has been a limit to low power consumption, and the current that flows per unit wiring does not decrease even if miniaturization advances. Occurs. For this reason, the electromigration phenomenon has been highlighted as a major issue. In flip-chip mounting parts that have been joined by solder so far, the intermetallic compound layer of Sn and Ni or Cu grows at an accelerated rate due to the electromigration phenomenon and segregates, thereby generating Kirkendall voids and cracks at the interface. It is known to cause occurrence and reduce its reliability. In the future, miniaturization of the electrode will progress, but the current density per bump tends to increase because the reduction in power consumption of the semiconductor element will not greatly progress. Therefore, since the current (current density) flowing per bump increases, segregation of the intermetallic compound layer of Sn and Ni and generation of Kirkendall void due to electromigration become more prominent and reliability decreases. There is a risk that.
　ハンダバンプを用いない微細ピッチ電極の接合構造として、例えば特許文献１のように、ＣｕバンプをＳｎとＣｕとの金属間化合物で接合した構造が提案されている。ここで提案された接合部は、ＳｎとＣｕとの金属化合物層が接合中心である。ＳｎとＣｕの反応は電流が印加されたときにエレクトロマイグレーション現象を起こすおそれがあり、ＳｎもしくはＣｕの移動が発生して金属間化合物の層分離（多層化）やカーケンダルボイドの発生を引き起こすおそれがある。こうした金属間化合物は結晶構造が特定の原子比率により構成される特殊な構造であることから、機械的に脆い特性を有するとともに、母金属との界面でクラックが発生したり、また結晶構造の違いからカーケンダルボイドが界面で発生したりするおそれがある。 As a joining structure of fine pitch electrodes that do not use solder bumps, a structure in which Cu bumps are joined with an intermetallic compound of Sn and Cu has been proposed as disclosed in Patent Document 1, for example. In the joint portion proposed here, the metal compound layer of Sn and Cu is the joint center. The reaction between Sn and Cu may cause an electromigration phenomenon when an electric current is applied, and the movement of Sn or Cu may cause separation of intermetallic compounds (multi-layering) or generation of Kirkendall voids. There is. These intermetallic compounds are special structures composed of a specific atomic ratio in the crystal structure. Therefore, they have mechanically brittle properties, cracks at the interface with the base metal, and differences in crystal structure. Therefore, there is a possibility that Kirkendall void is generated at the interface.
　また、バンプの微細化には次の課題もある。微細ピッチ化は電極サイズを小さくするため、バンプ形成時のめっきバラツキや、下地の電極と絶縁膜開口部の形状によるバンプ形状への影響が顕著に現われやすい。そのため、初期接合時にバンプ接合界面に隙間が発生しやすいが、そうした隙間の発生を防止するために高い荷重で実装すると、柱状電極の変形による接合不具合が発生することがある。 Also, there are the following issues in bump miniaturization. Fine pitching reduces the electrode size, so that the variation in plating at the time of bump formation and the influence on the bump shape due to the shape of the underlying electrode and the opening of the insulating film tend to appear remarkably. For this reason, a gap is likely to be generated at the bump bonding interface at the time of initial bonding. However, if mounting is performed with a high load in order to prevent the generation of such a gap, a bonding defect due to deformation of the columnar electrode may occur.
　更に、例えば特許文献２のように、めっき法のみでバンプを形成した構造では、電極部と絶縁膜とからなる開口形状の影響を受け、バンプ表面の形状に凹凸が生じたり、めっき精度により各バンプ間で高さが不均一になったりするおそれがある。従って、半導体素子の接合時においては、バンプ表面の凹凸や高さバラツキをキャンセルするために、実装荷重は高い設定となり、半導体素子に損傷を与えてしまうおそれがある。 Further, for example, as in Patent Document 2, in the structure in which the bump is formed only by the plating method, the shape of the bump surface is uneven due to the influence of the opening shape formed by the electrode portion and the insulating film, and each of the bumps has a plating accuracy. There is a risk that the height may be uneven between the bumps. Therefore, at the time of joining the semiconductor elements, the mounting load is set to be high in order to cancel the unevenness and height variation of the bump surface, and the semiconductor elements may be damaged.
　また更に、例えば特許文献３ではＣｕバンプ上にＡｕとＡｇの一方又は両方を形成したバンプと、Ｃｕバンプ上にＰｔとＰｄの一方又は両方を形成したバンプとを接合する構造が提案されているが、Ｃｕバンプと機械的特性が大きく異なるＡｕやＰｔ等の層が複数存在することで信頼性の点で課題がある。加えて、接合材料としてＡｇが用いられた場合では、イオンマイグレーションにより隣接バンプ間との絶縁不良が生じるおそれがある。 Furthermore, for example, Patent Document 3 proposes a structure in which a bump in which one or both of Au and Ag are formed on a Cu bump and a bump in which one or both of Pt and Pd are formed on a Cu bump are bonded. However, there are problems in terms of reliability due to the existence of a plurality of layers such as Au and Pt that have mechanical properties that are significantly different from those of the Cu bump. In addition, when Ag is used as the bonding material, there is a possibility that an insulation failure between adjacent bumps may occur due to ion migration.
　第３の課題は、アンダーフィル樹脂層の形成時において、ボイドが発生してしまうことである。この原因は、ハンダバンプの接合後の状態として、ハンダバンプが配置されたエリアとそうでない領域とで保護膜の有無により半導体素子と基板との間にギャップ差が生じることにある。こうしたギャップ差は、アンダーフィル樹脂の封入時に場所によって流速差を生じさせ、その流速差から空気の巻き込み等が生じ、接合部におけるボイドの発生や、ボイドを起点として接合部にクラックが発生するおそれがある。 The third problem is that voids are generated when the underfill resin layer is formed. This is because, as a state after the bonding of the solder bumps, there is a gap difference between the semiconductor element and the substrate depending on the presence or absence of the protective film between the area where the solder bumps are disposed and the area where the solder bumps are not. This gap difference causes a flow rate difference depending on the location when encapsulating the underfill resin, and air entrainment occurs due to the flow rate difference, which may cause voids at the joints and cracks at the joints starting from the voids. There is.
　本発明は、上記した技術の問題点を解決するためになされたものであって、その目的は、特にフリップチップ方式の実装形態において微細ピッチに対応し、且つ高い信頼性を得ることができる半導体装置及びその製造方法を提供することにある。 The present invention has been made to solve the above-described problems of the technology, and the object thereof is a semiconductor that can cope with a fine pitch and can obtain high reliability, particularly in a flip chip mounting form. It is to provide an apparatus and a manufacturing method thereof.
　また、本発明の他の目的は、半導体素子同士の接合や基板同士の接合にも適用できる複合回路装置及びその製造方法を提供することにある。 Another object of the present invention is to provide a composite circuit device applicable to bonding between semiconductor elements and bonding between substrates, and a method for manufacturing the same.
　（半導体装置）
　上記課題を解決するための本発明の半導体装置は、半導体素子上の第１電極部と基板上の第２電極部とが相互に対向するように電気的に接合された接合部と、前記接合部に存在し、前記第１電極部の構成材料及び前記第２電極部の構成材料の一方又は両方と固溶する接合材料を含む固溶体領域とを有するものである。 (Semiconductor device)
In order to solve the above-described problems, a semiconductor device according to the present invention includes a bonding portion in which a first electrode portion on a semiconductor element and a second electrode portion on a substrate are electrically bonded so as to face each other, and the bonding And a solid solution region including a bonding material that forms a solid solution with one or both of the constituent material of the first electrode portion and the constituent material of the second electrode portion.
　（第１の観点に係る半導体装置の製造方法）
　上記課題を解決するための本発明の第１の観点に係る半導体装置の製造方法は、半導体素子上の第１電極部と基板上の第２電極部とが電気的に接合される接合部が固溶体領域を有するように選択された金属材料からなる前記第１電極部と前記第２電極部とを形成し、前記第１電極部と前記第２電極部とが相互に対向するよう位置合せし、前記第１電極部と前記第２電極部とを加圧接触させ、前記加圧接触させた状態で加熱し、前記加熱した状態で保持して前記接合部に固溶体領域を形成するものである。 (Semiconductor device manufacturing method according to the first aspect)
A method for manufacturing a semiconductor device according to a first aspect of the present invention for solving the above-described problem includes a bonding portion in which the first electrode portion on the semiconductor element and the second electrode portion on the substrate are electrically bonded. Forming the first electrode portion and the second electrode portion made of a metal material selected to have a solid solution region, and aligning the first electrode portion and the second electrode portion so as to face each other; The first electrode portion and the second electrode portion are brought into pressure contact, heated in the pressure contacted state, and held in the heated state to form a solid solution region in the joint portion. .
　（第２の観点に係る半導体装置の製造方法）
　上記課題を解決するための本発明の第２の観点に係る半導体装置の製造方法は、半導体素子上の第１電極部と基板上の第２電極部とが電気的に接合する接合部が固溶体領域を有するように、一方をＣｕバンプとし、他方の構成材料をＡｕとする、前記第１電極部と前記第２電極部とを形成し、前記第１電極部と前記第２電極部とが相互に対向するよう位置合せする位置合わせし、前記第１電極部と前記第２電極部とを加圧接触させ、前記加圧接触させた状態で加熱し、前記加熱した状態で保持して前記接合部に固溶体領域を形成するものである。 (Semiconductor device manufacturing method according to second aspect)
According to a second aspect of the present invention for solving the above-described problem, a semiconductor device manufacturing method according to the second aspect of the present invention has a solid solution in which a joint portion where the first electrode portion on the semiconductor element and the second electrode portion on the substrate are electrically joined is a solid solution. The first electrode portion and the second electrode portion are formed so that one region is a Cu bump and the other component material is Au so that the first electrode portion and the second electrode portion are formed. Aligning so as to face each other, bringing the first electrode part and the second electrode part into pressure contact, heating in the pressure contacted state, holding in the heated state, and holding the heated state A solid solution region is formed at the joint.
　（複合回路装置及びその製造方法）
　本発明の複合回路装置は、回路板上の第１電極部と他の回路板上の第２電極部とが相互に対向するように電気的に接合された接合部と、前記接合部に存在し、前記第１電極部の構成材料及び前記第２電極部の構成材料の一方又は両方と固溶する接合材料を含む固溶体領とを有するものである。 (Composite circuit device and manufacturing method thereof)
The composite circuit device according to the present invention includes a joint part electrically joined so that a first electrode part on a circuit board and a second electrode part on another circuit board face each other, and the joint part And a solid solution region containing a bonding material that forms a solid solution with one or both of the constituent material of the first electrode portion and the constituent material of the second electrode portion.
　また、本発明の複合回路装置の製造方法は、回路板上の第１電極部と他の回路板上の第２電極部とが電気的に接合する接合部が固溶体領域を有するように選択された金属材料からなる前記第１電極部と前記第２電極部とを形成し、前記第１電極部と前記第２電極部とが相互に対向するよう位置合せし、前記第１電極部と前記第２電極部とを加圧接触させ、前記加圧接触させた状態で加熱し、前記加熱した状態で保持して前記接合部に固溶体領域を形成するものである。 Also, the method of manufacturing the composite circuit device of the present invention is selected so that the joint portion where the first electrode portion on the circuit board and the second electrode portion on the other circuit board are electrically joined has a solid solution region. Forming the first electrode portion and the second electrode portion made of a metal material, and aligning the first electrode portion and the second electrode portion so as to face each other; The second electrode portion is brought into pressure contact, heated in the pressure contact state, and held in the heated state to form a solid solution region in the joint portion.
　本発明によれば、特にフリップチップ方式の実装形態において微細ピッチに対応し、且つ高い信頼性を得ることができる半導体装置、複合回路回路装置及びそれらの製造方法を提供することができる。 According to the present invention, it is possible to provide a semiconductor device, a composite circuit circuit device, and a method for manufacturing the same that can cope with a fine pitch and can obtain high reliability particularly in a flip chip mounting form.
本発明の第１の実施形態による半導体装置の接合構造を示す断面図である。It is sectional drawing which shows the junction structure of the semiconductor device by the 1st Embodiment of this invention. 本発明の第１の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 1st Embodiment of this invention. 本発明の第１の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 1st Embodiment of this invention. 本発明の第１の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 1st Embodiment of this invention. 本発明の第１の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 1st Embodiment of this invention. 本発明の第１の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 1st Embodiment of this invention. 本発明の第１の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 1st Embodiment of this invention. 本発明の第２の実施形態による半導体装置の接合構造を示す断面図である。It is sectional drawing which shows the junction structure of the semiconductor device by the 2nd Embodiment of this invention. 本発明の第２の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 2nd Embodiment of this invention. 本発明の第２の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 2nd Embodiment of this invention. 本発明の第２の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 2nd Embodiment of this invention. 本発明の第２の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 2nd Embodiment of this invention. 本発明の第２の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 2nd Embodiment of this invention. 本発明の第２の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 2nd Embodiment of this invention. 本発明の第２の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 2nd Embodiment of this invention. 本発明の第２の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 2nd Embodiment of this invention. 本発明の第３の実施形態による半導体装置の接合構造を示す断面図である。It is sectional drawing which shows the junction structure of the semiconductor device by the 3rd Embodiment of this invention. 本発明の第３の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 3rd Embodiment of this invention. 本発明の第３の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 3rd Embodiment of this invention. 本発明の第３の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 3rd Embodiment of this invention. 本発明の第３の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 3rd Embodiment of this invention. 本発明の第３の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 3rd Embodiment of this invention. 本発明の第３の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 3rd Embodiment of this invention. 本発明の第３の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 3rd Embodiment of this invention. 本発明の第３の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 3rd Embodiment of this invention. 本発明の第４の実施形態による半導体装置の接合構造を示す断面図である。It is sectional drawing which shows the junction structure of the semiconductor device by the 4th Embodiment of this invention. 本発明の第４の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 4th Embodiment of this invention. 本発明の第４の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 4th Embodiment of this invention. 本発明の第４の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 4th Embodiment of this invention. 本発明の第４の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 4th Embodiment of this invention. 本発明の第４の実施の形態による半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device by the 4th Embodiment of this invention. 関連する半導体装置の接合構造及び接合方法を示す断面図である。It is sectional drawing which shows the junction structure and joining method of a related semiconductor device. 関連する半導体装置の接合構造及び接合方法を示す断面図である。It is sectional drawing which shows the junction structure and joining method of a related semiconductor device.
符号の説明Explanation of symbols
　１　半導体素子
　２　基板
　３　電極
　４　絶縁膜
　５　保護膜
　６　密着層
　７　接着層
　８　バンプ（電極部）
　９　接合材料
　１０　固溶体層（接合部）
　１１　アンダーフィル樹脂層
　１２　レジスト
　１３　Ａｕバンプ（電極部）
　１４　バリアメタル
　１５　ハンダバンプ DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Board | substrate 3 Electrode 4 Insulating film 5 Protective film 6 Adhesion layer 7 Adhesion layer 8 Bump (electrode part)
9 Bonding material 10 Solid solution layer (bonding part)
11 Underfill resin layer 12 Resist 13 Au bump (electrode part)
14 Barrier metal 15 Solder bump
　本発明の半導体装置は、半導体素子上の第１電極部と基板上の第２電極部とが相互に対向するように電気的に接合された接合部を有している。そして、その接合部は、第１電極部の構成材料及び第２電極部の構成材料の一方又は両方と固溶する接合材料を含む固溶体領域（固溶体層）が存在しているように構成される。 The semiconductor device of the present invention has a joint part in which the first electrode part on the semiconductor element and the second electrode part on the substrate are electrically joined so as to face each other. And the joining part is comprised so that the solid solution area | region (solid solution layer) containing the joining material which forms a solid solution with one or both of the constituent material of the 1st electrode part and the constituent material of the 2nd electrode part may exist. .
　これにより、その固溶体領域を介して接合した第１電極部と第２電極部は、規則格子である金属間化合物層を介して接続した場合と異なり、その接合部は接合界面からの濃度が傾斜した傾斜層となる。例えば、固溶体領域は、第１電極部の構成材料と第２電極部の構成材料の一方又は両方の濃度が傾斜した傾斜層である。その結果、接合部に不連続部がなく、機械的強度に優れ、接合信頼性が高い半導体装置を提供できる。また、得られた半導体装置は、拡散反応やエレクトロマイグレーション現象が進行しても不連続な接合界面とはならないので、不良、クラックなどの起点が生じず、接合信頼性の高い構造が得られる。 Thus, unlike the case where the first electrode portion and the second electrode portion joined via the solid solution region are connected via the intermetallic compound layer which is a regular lattice, the concentration of the joined portion is inclined from the joining interface. It becomes the graded layer. For example, the solid solution region is an inclined layer in which the concentration of one or both of the constituent material of the first electrode portion and the constituent material of the second electrode portion is inclined. As a result, it is possible to provide a semiconductor device that has no discontinuous portion in the bonding portion, excellent mechanical strength, and high bonding reliability. In addition, since the obtained semiconductor device does not become a discontinuous bonding interface even when a diffusion reaction or an electromigration phenomenon progresses, a starting point such as a defect or a crack does not occur, and a structure with high bonding reliability can be obtained.
　特に、その固溶体領域は、ＣｕとＡｕとの固溶体層であることが好ましい。例えば、第１電極部の構成材料と第２電極部の構成材料がＣｕであり、接合材料がＡｕであり、固溶体領域がＣｕとＡｕからなるように構成してもよい。又は、第１電極部の構成材料と第２電極部の構成材料は一方がＣｕで他方がＡｕであり、固溶体領域がＣｕとＡｕからなるように構成してもよい。 In particular, the solid solution region is preferably a solid solution layer of Cu and Au. For example, the constituent material of the first electrode part and the constituent material of the second electrode part may be Cu, the bonding material may be Au, and the solid solution region may be made of Cu and Au. Alternatively, the constituent material of the first electrode portion and the constituent material of the second electrode portion may be configured such that one is Cu and the other is Au, and the solid solution region is made of Cu and Au.
　第１電極部と第２電極部の一方又は両方がＣｕバンプであり、接合材料がＡｕであり、固溶体領域がＣｕバンプとＡｕからなるように構成してもよい。又は、第１電極部と第２電極部は一方がＣｕバンプで他方の構成材料がＡｕであり、固溶体領域がＣｕとＡｕからなるように構成してもよい。 One or both of the first electrode portion and the second electrode portion may be Cu bumps, the bonding material may be Au, and the solid solution region may be made of Cu bumps and Au. Alternatively, the first electrode portion and the second electrode portion may be configured such that one of them is a Cu bump and the other constituent material is Au, and the solid solution region is made of Cu and Au.
　なお、基板が半導体素子であるように構成してもよい。 In addition, you may comprise so that a board | substrate may be a semiconductor element.
　また、本発明の半導体装置によれば、半導体素子と基板に保護膜を形成しない、もしくは隣り合う接合部間で中央部が窪んだ保護膜を形成してもよい。例えば、第１電極部と第２電極部の一方又は両方がバンプ構造からなり、隣接する接合部間にはバンプの高さよりも低く且つ中央が窪んだ保護膜が設けられていてもよい。これにより、アンダーフィル樹脂の封入性を向上させることができ、樹脂内のボイド発生を抑制することができる。 Also, according to the semiconductor device of the present invention, a protective film may not be formed on the semiconductor element and the substrate, or a protective film having a depressed central portion between adjacent junctions may be formed. For example, one or both of the first electrode portion and the second electrode portion may have a bump structure, and a protective film that is lower than the height of the bump and has a depressed center may be provided between adjacent joint portions. Thereby, the enclosure property of underfill resin can be improved and the void generation | occurrence | production in resin can be suppressed.
　また、第１電極部と第２電極部の一方又は両方がバンプ構造からなり、接合部は、バンプの接合部側が平坦化した接合面を持つバンプで形成されてなるように構成してもよい。接合材料としてＡｕの厚さを極薄で形成すれば、ＦＣ実装時に短時間で固溶体層を形成することができるので、生産性が向上し、Ａｕの使用量を抑制でき、経済的効果が高い。この効果はバンプを平坦化することでさらに効果を増すことができる。 In addition, one or both of the first electrode portion and the second electrode portion may have a bump structure, and the bonding portion may be formed of a bump having a flattened bonding surface on the bonding portion side of the bump. . If the Au material is formed with a very thin thickness as the bonding material, a solid solution layer can be formed in a short time during FC mounting, so that productivity is improved, the amount of Au used can be suppressed, and an economic effect is high. . This effect can be further increased by flattening the bump.
　また、固溶体領域の構成材料が、全率固溶体型の材料からなるように構成してもよい。 Further, the constituent material of the solid solution region may be configured to be a solid solution type material.
　他方、上記の半導体装置の製造方法の例としては、まず、第１電極部と第２電極部との接合部が固溶体領域を有するように選択された金属材料からなる第１電極部と第２電極部とを形成し、第１電極部と第２電極部とが相互に対向するよう位置合せする。そして、第１電極部と第２電極部とを加圧接触させ、加圧接触させた状態で加熱し、加熱した状態で保持して接合部に固溶体領域を形成する。 On the other hand, as an example of the manufacturing method of the semiconductor device, first, the first electrode portion and the second electrode made of a metal material selected so that the joint portion between the first electrode portion and the second electrode portion has a solid solution region. An electrode part is formed and aligned so that the first electrode part and the second electrode part face each other. And a 1st electrode part and a 2nd electrode part are made to press-contact, and it heats in the state made to press-contact, hold | maintains in the heated state, and forms a solid solution area | region in a junction part.
　本発明の半導体装置の製造方法によれば、半導体素子側から加熱を加えて固溶体層を生成させるが可能なので、１つの基板に複数個の半導体素子を連続して接合する場合においても、基板への加熱による負荷や、電極部の経時変化による組成の変化を抑制することができ、偏析などによる局所的な強度の変化による信頼性低下を防ぐことができる。 According to the method for manufacturing a semiconductor device of the present invention, it is possible to generate a solid solution layer by applying heat from the semiconductor element side, so even when a plurality of semiconductor elements are continuously bonded to one substrate, It is possible to suppress the load caused by heating and the change in composition due to the aging of the electrode part, and it is possible to prevent a decrease in reliability due to a local change in strength due to segregation or the like.
　また、本発明の半導体素子の製造方法によれば、半導体素子の電極上と基板の電極上にそれぞれＣｕバンプを形成した場合、そのＣｕバンプの表面を平坦化加工することにより、高さが均一で表面が平担な電極部とすることができるので、低い実装荷重で各電極部間を当接でき、その結果、半導体素子への損傷がない。 According to the method for manufacturing a semiconductor element of the present invention, when Cu bumps are formed on the electrodes of the semiconductor element and the electrodes of the substrate, respectively, the surface of the Cu bumps is flattened to make the height uniform. Thus, the electrode portions having a flat surface can be formed, so that the electrode portions can be brought into contact with each other with a low mounting load. As a result, there is no damage to the semiconductor element.
　上記の電極部の形成の一例としては、半導体素子及び基板の一方又は両方の電極を覆うように密着層と接着層とを積層し、接着層上にレジストを形成し、電極上方のレジストを除去して開口部を形成し、開口部を金属材料で埋めて電極部を形成する。その後、開口部に形成した電極部と開口部以外のレジストとを加工して電極部を平坦化し、電極部上に固溶体領域を形成するための接合材料を供給し、平坦化加工後のレジストを除去し、電極部以外の密着層と接着層を除去する。 As an example of the formation of the electrode part, an adhesion layer and an adhesive layer are laminated so as to cover one or both electrodes of the semiconductor element and the substrate, a resist is formed on the adhesive layer, and the resist above the electrode is removed. Thus, an opening is formed, and the electrode is formed by filling the opening with a metal material. After that, the electrode part formed in the opening part and the resist other than the opening part are processed to flatten the electrode part, supply a bonding material for forming a solid solution region on the electrode part, and the resist after the flattening process is applied. The adhesive layer and the adhesive layer other than the electrode portion are removed.
　上記の電極部の形成の他の例としては、半導体素子及び基板の一方又は両方の電極を覆うように密着層と接着層とを積層し、接着層上にレジストを形成し、電極上方のレジストを除去して開口部を形成し、開口部を金属材料で埋めて電極部を形成する。その後、残りのレジストを除去し、電極部以外の密着層と接着層を除去し、電極部を覆うように保護膜を形成し、電極部と保護膜を加工して電極部を平坦化し、電極部上に固溶体領域を形成するための接合材料を供給し、保護膜を均一に所定量除去して電極部を突出させる。 As another example of the formation of the electrode part, an adhesive layer and an adhesive layer are laminated so as to cover one or both electrodes of the semiconductor element and the substrate, a resist is formed on the adhesive layer, and the resist above the electrode is formed. Is removed to form an opening, and the opening is filled with a metal material to form an electrode portion. Then, the remaining resist is removed, the adhesion layer and the adhesive layer other than the electrode part are removed, a protective film is formed so as to cover the electrode part, the electrode part and the protective film are processed, the electrode part is flattened, and the electrode A bonding material for forming a solid solution region is supplied on the part, and a predetermined amount of the protective film is uniformly removed to project the electrode part.
　上記の電極部の平坦化では、レジスト又は保護膜のエッチングレートの方が速く、レジスト又は保護膜は接合部間の電極部の高さよりも低く且つ中央が窪むように加工してもよい。 In the flattening of the electrode part, the etching rate of the resist or the protective film is faster, and the resist or the protective film may be processed to be lower than the height of the electrode part between the joints and to be depressed in the center.
　また、上記の電極部上への接合材料の供給では、無電解めっき法で行ってもよい。 Further, the supply of the bonding material onto the electrode part may be performed by an electroless plating method.
　また、電極部がＣｕバンプであり、接合材料がＡｕであるように構成してもよい。 Alternatively, the electrode part may be a Cu bump and the bonding material may be Au.
　他方、電極部上への接合材料の供給では、置換Ａｕめっき浴を用いてＣｕバンプにＡｕの薄膜を形成し、更に置換と還元の併用型のＡｕめっき浴を用いて所望の膜厚に形成してもよい。 On the other hand, in supplying the bonding material onto the electrode portion, a thin film of Au is formed on the Cu bump using a substitution Au plating bath, and further formed to a desired film thickness using a combination of substitution and reduction type Au plating bath. May be.
　半導体装置の製造方法の他の例としては、その電極部の形成では、第１電極部と第２電極部との接合部が固溶体領域を有するように、第１電極部と第２電極部の一方をＣｕバンプとし、他方の構成材料をＡｕとするものがある。 As another example of the manufacturing method of the semiconductor device, in the formation of the electrode part, the first electrode part and the second electrode part are formed so that the joint part between the first electrode part and the second electrode part has a solid solution region. Some have Cu bumps and the other is Au.
　Ｃｕバンプからなる電極部の形成の一例としては、半導体素子及び基板の一方又は両方の電極を覆うように密着層と接着層とを積層し、接着層上にレジストを形成し、電極上方のレジストを除去して開口部を形成し、開口部をＣｕで埋めてＣｕバンプを形成する。その後、開口部に形成したＣｕバンプと開口部以外のレジストとを加工して電極部を平坦化し、平坦化加工後のレジストを除去し、Ｃｕバンプ以外の密着層と接着層を除去する。 As an example of the formation of an electrode portion made of Cu bumps, an adhesion layer and an adhesion layer are laminated so as to cover one or both electrodes of a semiconductor element and a substrate, a resist is formed on the adhesion layer, and a resist above the electrodes is formed. Are removed to form openings, and the openings are filled with Cu to form Cu bumps. Thereafter, the Cu bump formed in the opening and the resist other than the opening are processed to flatten the electrode part, the resist after the flattening process is removed, and the adhesion layer and the adhesive layer other than the Cu bump are removed.
　Ｃｕバンプからなる電極部の形成の他の例としては、半導体素子及び基板の一方又は両方の電極を覆うように密着層と接着層とを積層し、接着層上にレジストを形成し、電極上方のレジストを除去して開口部を形成し、開口部をＣｕで埋めてＣｕバンプを形成する。その後、残りのレジストを除去し、Ｃｕバンプ以外の密着層と接着層を除去し、Ｃｕバンプを覆うように保護膜を形成し、Ｃｕバンプと保護膜を加工してＣｕバンプを平坦化し、保護膜を均一に所定量除去してＣｕバンプを突出させる。 As another example of the formation of the electrode portion made of Cu bump, an adhesion layer and an adhesion layer are laminated so as to cover one or both electrodes of the semiconductor element and the substrate, a resist is formed on the adhesion layer, and the upper part of the electrode is formed. The resist is removed to form openings, and the openings are filled with Cu to form Cu bumps. Thereafter, the remaining resist is removed, the adhesion layer and the adhesive layer other than the Cu bump are removed, a protective film is formed so as to cover the Cu bump, the Cu bump and the protective film are processed, the Cu bump is flattened, and protection is performed. A predetermined amount of the film is removed uniformly to project the Cu bumps.
　また、電極部の平坦化では、レジスト又は保護膜のエッチングレートの方が速く、レジスト又は保護膜は接合部間の電極部の高さよりも低く且つ中央が窪むように加工してもよい。 Further, in the flattening of the electrode part, the etching rate of the resist or the protective film is faster, and the resist or the protective film may be processed so as to be lower than the height of the electrode part between the joints and the center is depressed.
　以下、本発明の実施の形態について図面を参照しつつ具体的に説明する。なお、本発明の範囲は、以下の実施の形態のみに限定されるものではない。 Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings. The scope of the present invention is not limited only to the following embodiments.
　（第１の実施の形態）
　図１は、本発明の第１実施の形態に係る半導体装置を示す断面図である。図１に示す半導体装置は、半導体素子１に設けられた電極３上にＣｕバンプ８があり、基板２に設けられた電極３上にも同様にＣｕバンプ８があり、両方のバンプ８，８がＣｕとＡｕとからなる固溶体層１０を介して接合されている。ここで、固溶体層１０は、半導体素子１側と基板２側の両方のＣｕバンプ８，８の接合部にある領域（固溶体領域）に存在する層であり、この固溶体層１０は、Ｃｕの濃度が均一に傾斜した傾斜層となっている。一例として、この固溶体層１０の厚さを０．５μｍとし、Ｃｕバンプ８の厚さを１μｍ以上とし、望ましくは３μｍ以上とすれば、高温保管環境での長期保管信頼性が高くなる。そして、半導体素子１と基板２との間には、アンダーフィル樹脂層１１が形成されている。 (First embodiment)
FIG. 1 is a sectional view showing a semiconductor device according to the first embodiment of the present invention. The semiconductor device shown in FIG. 1 has Cu bumps 8 on the electrodes 3 provided on the semiconductor element 1, and also has Cu bumps 8 on the electrodes 3 provided on the substrate 2. Are joined via a solid solution layer 10 made of Cu and Au. Here, the solid solution layer 10 is a layer existing in a region (solid solution region) in a joint portion between the Cu bumps 8 and 8 on both the semiconductor element 1 side and the substrate 2 side. The solid solution layer 10 has a Cu concentration. Is an inclined layer that is uniformly inclined. As an example, when the thickness of the solid solution layer 10 is 0.5 μm and the thickness of the Cu bump 8 is 1 μm or more, preferably 3 μm or more, long-term storage reliability in a high-temperature storage environment is improved. An underfill resin layer 11 is formed between the semiconductor element 1 and the substrate 2.
　なお、詳しくは、半導体素子１に設けられた電極３の上、及び基板２に設けられた電極３の上には、密着層６と接着層７とがその順で設けられており、Ｃｕバンプ８はその接着層７上に設けられている。また、半導体素子１上及び基板２上の電極３以外の面には、絶縁膜４が設けられている。 Specifically, an adhesion layer 6 and an adhesive layer 7 are provided in this order on the electrode 3 provided on the semiconductor element 1 and on the electrode 3 provided on the substrate 2. 8 is provided on the adhesive layer 7. An insulating film 4 is provided on the surface of the semiconductor element 1 and the substrate 2 other than the electrode 3.
　本願において、固溶体層１０は、固溶体を構成する材料の濃度が均一に傾斜している場合を含むので、Ｃｕバンプ８との間の境界が明瞭でない場合がある。そのため、本願では、例えばＣｕバンプ８のＣｕと接合材料であるＡｕとを含む領域を固溶体領域と呼び、その固溶体領域が接合部に存在するものとしている。また、電極部とは、電極３からＣｕバンプ８までの部分、主には電極３上に設けられたバンプ８を指し、第１電極部とは一方の側の回路板である半導体素子１における電極部を指し、第２電極部とは他方の側の回路板である基板２における電極部を指している。また、接合部とは、対向するＣｕバンプ８，８が接合して固溶体層１０が形成された部分を指すものとする。 In the present application, since the solid solution layer 10 includes a case where the concentration of the material constituting the solid solution is uniformly inclined, the boundary with the Cu bump 8 may not be clear. Therefore, in the present application, for example, a region including Cu of the Cu bump 8 and Au as a bonding material is referred to as a solid solution region, and the solid solution region is present in the bonded portion. The electrode portion refers to a portion from the electrode 3 to the Cu bump 8, mainly the bump 8 provided on the electrode 3, and the first electrode portion in the semiconductor element 1 which is a circuit board on one side. The electrode part is indicated, and the second electrode part is an electrode part in the substrate 2 which is a circuit board on the other side. Moreover, a junction part shall point out the part in which Cu bump 8 and 8 which opposes joined and the solid solution layer 10 was formed.
　本実施の形態に係る半導体装置では、ＣｕとＡｕとの固溶体層１０を介して半導体素子１と基板２の電極同士を接合しており、この固溶体層１０は、半導体素子１側と基板２側のＣｕバンプ８，８からＣｕの濃度勾配が均一に傾斜した傾斜層（反応層ともいう）であるので、不連続がなく、機械的強度に優れている。また、この固溶体層１０が形成された接続部は、拡散反応やエレクトロマイグレーション現象が進行しても不連続な接合界面とはならないので、不良、クラックなどの起点が生じない。従って、信頼性を向上させることが可能となる。 In the semiconductor device according to the present embodiment, the electrodes of the semiconductor element 1 and the substrate 2 are joined to each other through the solid solution layer 10 of Cu and Au. The solid solution layer 10 is formed on the semiconductor element 1 side and the substrate 2 side. The Cu bumps 8 and 8 are inclined layers (also referred to as reaction layers) in which the Cu concentration gradient is uniformly inclined, so that there is no discontinuity and excellent mechanical strength. In addition, the connection portion in which the solid solution layer 10 is formed does not become a discontinuous bonding interface even when a diffusion reaction or an electromigration phenomenon proceeds, so that no starting point such as a defect or a crack is generated. Therefore, reliability can be improved.
　次に、この第１の実施の形態に係る半導体装置の製造方法について説明する。 Next, a method for manufacturing the semiconductor device according to the first embodiment will be described.
　初めに、回路面上に設けられたＡｌ等からなる電極３と、その電極３上の一部に開口部を有した態様で回路面上を覆うＳｉＯＮやＳｉＯ２等からなる絶縁膜４とを有する半導体素子１及び基板２を作製又は準備する。この半導体素子１及び基板２の電極形成面側に、スパッタ法等を用いてＴｉ等からなる密着層６とＣｕ等からなる接着層７を、その電極３と絶縁膜４の全面に形成する。そして、スピンコート等によって感光性のレジスト１２を接着層７上に形成し、露光現像することで電極上方のレジスト１２のみを除去し、電極３上に所望の大きさで開口部を形成する。更に、このレジスト１２の開口部に電解めっき法等でバンプ８となるＣｕを析出させる〔図２Ａ〕。このとき、Ｃｕバンプ８の高さは各電極３間でバラツキが生じていてもよい。 First, an electrode 3 made of Al or the like provided on the circuit surface and an insulating film 4 made of SiON, SiO 2 or the like covering the circuit surface in a form having an opening on a part of the electrode 3 are provided. A semiconductor element 1 and a substrate 2 are prepared or prepared. An adhesion layer 6 made of Ti or the like and an adhesive layer 7 made of Cu or the like are formed on the entire surface of the electrode 3 and the insulating film 4 by sputtering or the like on the electrode formation surface side of the semiconductor element 1 and the substrate 2. Then, a photosensitive resist 12 is formed on the adhesive layer 7 by spin coating or the like, and only the resist 12 above the electrode is removed by exposure and development, and an opening having a desired size is formed on the electrode 3. Further, Cu that becomes the bumps 8 is deposited in the openings of the resist 12 by an electrolytic plating method or the like [FIG. 2A]. At this time, the height of the Cu bump 8 may vary between the electrodes 3.
　次に、Ｃｕバンプ８の平坦化加工を行う。平坦化加工は、開口部に形成された電極部であるＣｕバンプ８と、Ｃｕバンプ８以外のレジスト１２とを、機械研磨法、化学機械研磨法（ＣＭＰ）、研削加工等の各種の平坦化加工手段を用いて行う〔図２Ｂ〕。 Next, the Cu bump 8 is flattened. In the flattening process, various kinds of flattening such as a mechanical polishing method, a chemical mechanical polishing method (CMP), and a grinding process are performed on the Cu bump 8 that is an electrode portion formed in the opening and the resist 12 other than the Cu bump 8. This is performed using a processing means [FIG. 2B].
　次に、無電解めっき法等を用いて、Ｃｕバンプ８上に、最終的にＣｕと固溶体領域を形成するための接合材料９であるＡｕ薄膜を形成する〔図２Ｃ〕。ここで、無電解めっき法で行う場合は、置換Ａｕめっき浴を用いて所望のめっき厚のＡｕを形成することができる。また、置換Ａｕめっき浴にてＡｕ薄膜を形成した後、置換と還元の併用型のＡｕめっき浴を用いて所望のめっき厚のＡｕ薄膜を形成してもよい。Ａｕ等からなる接合材料９の厚さは特に限定されないが、例えば０．０３μｍから０．５μｍの範囲を例示できるが、それ以外の厚さであってもよい。 Next, by using an electroless plating method or the like, an Au thin film that is a bonding material 9 for finally forming a solid solution region with Cu is formed on the Cu bump 8 [FIG. 2C]. Here, when the electroless plating method is used, Au having a desired plating thickness can be formed using a substitution Au plating bath. Alternatively, after forming an Au thin film in a substitution Au plating bath, an Au thin film having a desired plating thickness may be formed using a combination of substitution and reduction type Au plating bath. Although the thickness of the bonding material 9 made of Au or the like is not particularly limited, for example, a range of 0.03 μm to 0.5 μm can be exemplified, but other thicknesses may be used.
　その後、残りのレジスト１２を除去し、Ｃｕバンプ８の下以外に形成されている密着層６と接着層７とをウェットエッチング法等を用いて除去する。こうして、本実施の形態に係る半導体装置に用いられる半導体素子１及び基板２を得ることができる。これらは、平坦化されたＣｕバンプ８の接合面上にＡｕからなる接合材料９が設けられた態様で得られる〔図２Ｄ〕。 Thereafter, the remaining resist 12 is removed, and the adhesion layer 6 and the adhesion layer 7 formed other than under the Cu bumps 8 are removed using a wet etching method or the like. Thus, the semiconductor element 1 and the substrate 2 used in the semiconductor device according to the present embodiment can be obtained. These are obtained in a mode in which a bonding material 9 made of Au is provided on the bonding surface of the planarized Cu bump 8 [FIG. 2D].
　次に、Ｃｕバンプ８と接合材料９が形成された半導体素子１と基板２を用いて、両方の電極部の位置が一致するように位置合を行う〔図２Ｅ〕。このとき、半導体素子１は、ダイシング加工によって所望のサイズに個片化がなされている。また、半導体素子１の裏面を研磨法等にて加工し、所望の薄さに薄型化してもよい。基板２についても同様に個片化や薄型化を行ってもよい。 Next, using the semiconductor element 1 and the substrate 2 on which the Cu bumps 8 and the bonding material 9 are formed, alignment is performed so that the positions of both electrode portions coincide (FIG. 2E). At this time, the semiconductor element 1 is separated into a desired size by dicing. Further, the back surface of the semiconductor element 1 may be processed by a polishing method or the like to reduce the thickness to a desired thickness. Similarly, the substrate 2 may be singulated or thinned.
　その後、対向する電極部の接合材料９，９面が全て接触する程度に加圧し、両方のＣｕバンプ８と接合材料９を所定の温度以上に加熱する。ここで、加熱方法は、基板側を常温又はＣｕとＡｕとの反応が急速に進行しない程度の予備加熱とし、半導体素子１側よりＣｕとＡｕを反応させるための加熱を行ってもよい。 Thereafter, pressurization is performed so that the surfaces of the bonding materials 9 and 9 of the opposing electrode portions are all in contact with each other, and both the Cu bumps 8 and the bonding material 9 are heated to a predetermined temperature or more. Here, as the heating method, the substrate side may be preheated to room temperature or to the extent that the reaction between Cu and Au does not proceed rapidly, and heating for reacting Cu and Au from the semiconductor element 1 side may be performed.
　次に、この加熱状態を保持することによって半導体素子１と基板２の両方の接合材料９であるＡｕとＣｕバンプ８との反応が進み、ＡｕとＣｕとが固溶体化し、両方のＣｕバンプ８の濃度勾配が均一に傾斜し、厚さが例えば０．５μｍの固溶体層１０となることで接合される。最後に、半導体素子１と基板２との間に、樹脂を注入することによりアンダーフィル樹脂層１１を形成して、本発明の第１の実施の形態からなる半導体装置が得られる〔図２Ｆ〕。 Next, by maintaining this heating state, the reaction between Au and Cu bumps 8 which are the bonding materials 9 of both the semiconductor element 1 and the substrate 2 proceeds, and Au and Cu are solid-solutioned. Bonding is achieved by the concentration gradient being uniformly inclined and the solid solution layer 10 having a thickness of, for example, 0.5 μm. Finally, an underfill resin layer 11 is formed by injecting a resin between the semiconductor element 1 and the substrate 2 to obtain the semiconductor device according to the first embodiment of the present invention [FIG. 2F]. .
　本発明の半導体装置の製造方法では、半導体素子１側から加熱を加えて固溶体層１０を生成させることで、１つの基板２に複数個の半導体素子１を連続して接合する場合においても、基板２への加熱による負荷や、電極部の経時変化による組成の変化を抑制することが可能であり、偏析などによる局所的な強度の変化による信頼性低下が発生しない。 In the method of manufacturing a semiconductor device according to the present invention, even when a plurality of semiconductor elements 1 are continuously bonded to one substrate 2 by applying heat from the semiconductor element 1 side to generate the solid solution layer 10, the substrate It is possible to suppress a load due to heating to 2 and a change in composition due to a change with time of the electrode part, and reliability deterioration due to a local change in strength due to segregation or the like does not occur.
　また、半導体素子１と基板２の電極３上に形成したＣｕバンプ８を平坦化することで、各電極部はその高さが均一で且つ表面が平面となる。その結果、低い実装荷重設定で対向する各電極部を当接することができるので、半導体素子１への損傷を抑制することが可能である。 Further, by flattening the Cu bumps 8 formed on the semiconductor element 1 and the electrode 3 of the substrate 2, each electrode portion has a uniform height and a flat surface. As a result, the opposing electrode portions can be brought into contact with each other with a low mounting load setting, so that damage to the semiconductor element 1 can be suppressed.
　更に、半導体素子１と基板２に保護膜（図９Ａ及び図９Ｂの符号５を参照）を形成しないことによって、半導体素子１と基板２との間隔を広く保てると共にギャップ差が無いので、アンダーフィル樹脂の封入性を向上させることができ、樹脂内ボイドの発生を抑制が可能であることから、高い信頼性が得られる。 Further, since no protective film is formed on the semiconductor element 1 and the substrate 2 (see reference numeral 5 in FIGS. 9A and 9B), the gap between the semiconductor element 1 and the substrate 2 can be kept wide and there is no gap difference. Since the resin sealing property can be improved and generation of voids in the resin can be suppressed, high reliability can be obtained.
　また更に、不要箇所の密着層６と接着層７の除去を行う前にＡｕからなる接合材料９を供給しているため、無電解めっきにて接合材料９を供給する場合に、各電極間における電位差はない。従って、各Ｃｕバンプ間での電位差によるめっき厚のバラツキや未析出を抑制することができ、各Ｃｕバンプ間で安定した接合状態を得ることが可能である。 Furthermore, since the bonding material 9 made of Au is supplied before the adhesion layer 6 and the adhesive layer 7 are removed from unnecessary portions, when the bonding material 9 is supplied by electroless plating, between the electrodes. There is no potential difference. Therefore, variations in plating thickness and non-precipitation due to a potential difference between the Cu bumps can be suppressed, and a stable bonding state can be obtained between the Cu bumps.
　また更に、レジスト１２を形成した後にＣｕバンプ８の平坦化加工を行い、その後、Ａｕからなる接合材料９を形成し、その後、レジスト１２を除去することによって、Ｃｕの研磨屑等が半導体素子１や基板２の回路面に残存しにくい。従って、半導体装置における絶縁不良等の発生を抑制でき、信頼性を向上させることが可能である。 Further, after the resist 12 is formed, the Cu bumps 8 are flattened, and then a bonding material 9 made of Au is formed. Thereafter, the resist 12 is removed, so that Cu polishing debris can be removed from the semiconductor element 1. And hardly remain on the circuit surface of the substrate 2. Therefore, it is possible to suppress the occurrence of insulation failure or the like in the semiconductor device and improve reliability.
　本発明においては、半導体素子１と基板２とを接合した構造を示したが、半導体素子同士１，１を接合した複合回路装置であってもよいし、基板同士２，２を接合した複合回路装置であってもよい。 In the present invention, a structure in which the semiconductor element 1 and the substrate 2 are joined is shown. However, a composite circuit device in which the semiconductor elements 1 and 1 are joined may be used, or a composite circuit in which the substrates 2 and 2 are joined. It may be a device.
　また、Ａｕからなる接合材料９の供給を半導体素子１と基板２の両方に行っているが、何れか一方の電極部側だけであってもよい。また更に、半導体素子１の電極部と基板２の電極部の何れか一方のみを、Ｃｕバンプ８とＡｕからなる接合材料９で構成し、他方はバンプ構造とせずにＣｕ電極を形成して両者を接合した構造であってもよい。また、半導体素子１の電極部と基板２の電極部の何れか一方のみをＣｕバンプ８で構成し、他方はバンプ構造とせずにＣｕ電極を形成し、そのＣｕ電極上にＡｕからなる接合材料９を形成して両者を接合したものであってもよい。 Further, the bonding material 9 made of Au is supplied to both the semiconductor element 1 and the substrate 2, but only one of the electrode portions may be provided. Furthermore, only one of the electrode part of the semiconductor element 1 and the electrode part of the substrate 2 is composed of a bonding material 9 made of Cu bumps 8 and Au, and the other is formed with a Cu electrode without a bump structure. It may be a structure in which Further, only one of the electrode portion of the semiconductor element 1 and the electrode portion of the substrate 2 is constituted by the Cu bump 8, the other is not formed with a bump structure, a Cu electrode is formed, and a bonding material made of Au on the Cu electrode. 9 may be formed and both may be joined.
　また、この実施の形態ではＣｕとＡｕとの固溶体層１０を介した接合構造としているが、本発明においては、ＡｕバンプとＰｔや、ＡｕバンプとＰｄや、ＣｕバンプとＰｔや、ＣｕバンプとＰｄや、ＣｏバンプとＰｄ等のバンプ材と接合材料の組合せであってもよく、それらの組合せにより固溶体層１０を形成し、この固溶体層１０を介した接合構造としてもよい。こうした固溶体領域の構成材料は全率固溶体型の材料からなるものが好ましい。 In this embodiment, the bonding structure is formed through the solid solution layer 10 of Cu and Au. However, in the present invention, Au bump and Pt, Au bump and Pd, Cu bump and Pt, Cu bump and A combination of a bump material such as Pd or Co bump and Pd and a bonding material may be used, and the solid solution layer 10 may be formed by a combination thereof, and a bonding structure via the solid solution layer 10 may be used. The constituent material of such a solid solution region is preferably made of a solid solution type material.
　（第２の実施の形態）
　図３は、本発明の第２の実施の形態に係る半導体装置を示す断面図である。図３に示すように、本実施の形態が第１の実施の形態と相違する点は、隣接するＣｕバンプ８，８間に中央が窪んだ円弧状の保護膜５が形成されている点である。 (Second Embodiment)
FIG. 3 is a sectional view showing a semiconductor device according to the second embodiment of the present invention. As shown in FIG. 3, the present embodiment is different from the first embodiment in that an arc-shaped protective film 5 whose center is depressed is formed between adjacent Cu bumps 8 and 8. is there.
　本実施の形態では、そうした保護膜５を形成することで、半導体素子１及び基板２とアンダーフィル樹脂層１１との密着性が向上し、また、その保護膜５は、半導体素子１と基板２の線膨張差等によって生じる応力に対して緩和層として機能することから、信頼性を向上させることが可能である。 In the present embodiment, by forming such a protective film 5, the adhesion between the semiconductor element 1 and the substrate 2 and the underfill resin layer 11 is improved, and the protective film 5 includes the semiconductor element 1 and the substrate 2. Since it functions as a relaxation layer with respect to the stress caused by the difference in linear expansion, it is possible to improve the reliability.
　また、保護膜５の表面が隣接するバンプ８，８間で中央が窪んだ円弧状であることによって、接合後の半導体素子１と基板２との間を広く確保することができる。その結果、アンダーフィル樹脂の封入性を確保でき、樹脂内ボイドの発生を抑制し、高い信頼性を得ることが可能となる。 Further, since the surface of the protective film 5 has an arc shape in which the center is depressed between the adjacent bumps 8 and 8, a wide space can be secured between the semiconductor element 1 and the substrate 2 after bonding. As a result, it is possible to secure the encapsulating property of the underfill resin, suppress the generation of voids in the resin, and obtain high reliability.
　図４Ａ～図４Ｈは、本実施の形態に係る半導体装置の製造方法を示す工程図である。本実施の形態では、バンプ８となるＣｕをレジスト１２の開口部に析出させる工程まで、第１の実施の形態と同様である〔図４Ａ〕。 4A to 4H are process diagrams showing a method for manufacturing a semiconductor device according to the present embodiment. In the present embodiment, the process is the same as that of the first embodiment up to the step of depositing Cu to be the bumps 8 in the openings of the resist 12 [FIG. 4A].
　次に、残りのレジスト１２を除去し、バンプ８の下以外に形成されている密着層６と接着層７とをウェットエッチング法等を用い除去する〔図４Ｂ〕。 Next, the remaining resist 12 is removed, and the adhesion layer 6 and the adhesion layer 7 formed except for under the bumps 8 are removed using a wet etching method or the like [FIG. 4B].
　次に、バンプ８を覆うように熱硬化性のポリイミド樹脂等からなる保護膜５をスピンコート法等を用いて供給し硬化させる〔図４Ｃ〕。 Next, a protective film 5 made of a thermosetting polyimide resin or the like is supplied and cured using a spin coat method or the like so as to cover the bumps 8 [FIG. 4C].
　そして、保護膜５とバンプ８を機械研磨法、化学機械研磨法（ＣＭＰ）、研削加工等の各種の平坦化加工手段で加工し、バンプ８の平坦化加工を行う〔図４Ｄ〕。このとき、Ｃｕのエッチングレートよりも保護膜５の研磨量又は研削量の方が多くなるようにスラリーや加工条件を調整して研磨又は研削し、保護膜５の表面が隣接するバンプ８，８間で中央が窪んだ円弧状となるように加工する。その窪みの程度は特に限定されないが、後工程で保護膜５を均一に所定量除去した後であっても、下層である絶縁膜４等が保護膜５よりも露出しない程度であればよい。 Then, the protective film 5 and the bumps 8 are processed by various flattening means such as a mechanical polishing method, a chemical mechanical polishing method (CMP), and a grinding process to flatten the bumps 8 [FIG. 4D]. At this time, the polishing or grinding conditions are adjusted so that the polishing amount or the grinding amount of the protective film 5 is larger than the etching rate of Cu, and polishing or grinding is performed. It is processed so as to form an arc shape with the center recessed. The degree of the depression is not particularly limited, but may be any degree as long as the underlying insulating film 4 or the like is not exposed from the protective film 5 even after the protective film 5 is uniformly removed in a subsequent step.
　更に、無電解めっき法等を用いてバンプ８にＡｕからなる接合材料９を形成する〔図４Ｅ〕。ここで、無電解めっき法で行う場合は、置換Ａｕめっき浴を用いて所望のめっき厚のＡｕを形成することができる。また、置換Ａｕめっき浴にてＡｕ薄膜を形成した後、置換と還元の併用型のＡｕめっき浴を用いて所望のめっき厚のＡｕ薄膜を形成してもよい。 Further, a bonding material 9 made of Au is formed on the bumps 8 by using an electroless plating method or the like [FIG. 4E]. Here, when the electroless plating method is used, Au having a desired plating thickness can be formed using a substitution Au plating bath. Alternatively, after forming an Au thin film in a substitution Au plating bath, an Au thin film having a desired plating thickness may be formed using a combination of substitution and reduction type Au plating bath.
　その後、ドライエッチング法等にて保護膜５を均一に所定量除去し、バンプ８の先端側を突出させることで、本発明の実施の形態で用いられる半導体素子１及び基板２の平坦化されたＣｕバンプ８とＡｕからなる接合材料９の構造が得られる〔図４Ｆ〕。 Thereafter, the protective film 5 is uniformly removed by a dry etching method or the like, and the tip end side of the bump 8 is protruded, so that the semiconductor element 1 and the substrate 2 used in the embodiment of the present invention are planarized. A structure of the bonding material 9 composed of the Cu bump 8 and Au is obtained [FIG. 4F].
　次に、このバンプ８と接合材料９が形成された半導体素子１と基板２とを用いて、両方の電極３，３の位置が一致するように位置合わせを行う〔図４Ｇ〕。このとき、半導体素子１は、ダイシング加工によって所望のサイズに個片化がなされている。また、半導体素子１の裏面を研磨法等にて加工し、所望の薄さに薄型化してもよい。基板２についても同様に個片化や薄型化を行ってもよい。 Next, using the semiconductor element 1 and the substrate 2 on which the bumps 8 and the bonding material 9 are formed, alignment is performed so that the positions of both the electrodes 3 and 3 coincide [FIG. 4G]. At this time, the semiconductor element 1 is separated into a desired size by dicing. Further, the back surface of the semiconductor element 1 may be processed by a polishing method or the like to reduce the thickness to a desired thickness. Similarly, the substrate 2 may be singulated or thinned.
　その後、第１の実施の形態と同様に加圧、加熱し、半導体素子１と基板２は両方のバンプ８，８の間でＣｕとＡｕとの固溶体層１０が形成され、固溶体層１０を介して接合される。最後に、半導体素子１と基板２との間に、アンダーフィル樹脂層１１を形成し、本実施の形態の半導体装置の構造が得られる〔図４Ｈ〕。 Thereafter, pressurization and heating are performed as in the first embodiment, and a solid solution layer 10 of Cu and Au is formed between the bumps 8 and 8 on the semiconductor element 1 and the substrate 2, and the solid solution layer 10 is interposed therebetween. Are joined. Finally, an underfill resin layer 11 is formed between the semiconductor element 1 and the substrate 2 to obtain the structure of the semiconductor device of the present embodiment [FIG. 4H].
　本実施の形態では、バンプ８と保護膜５との密着性が得られている状態でバンプ８の平坦化加工を行うので、加工時にバンプ８と保護膜５とが剥がれや研磨ダレや研削ダレ等のバンプ形状不良及びバンプ損失を抑制することが可能である。また、保護膜５を形成することにより、半導体素子１及び基板２の回路面に対する保護性を向上させることができ、製造工程中における損傷を抑制することが可能である。 In the present embodiment, since the bump 8 is planarized in a state in which the adhesion between the bump 8 and the protective film 5 is obtained, the bump 8 and the protective film 5 are peeled off during processing, polished, or ground. It is possible to suppress bump shape defects such as the above and bump loss. Further, by forming the protective film 5, it is possible to improve the protection of the circuit surfaces of the semiconductor element 1 and the substrate 2, and it is possible to suppress damage during the manufacturing process.
　（第３の実施の形態）
　図５は、本発明の第３の実施の形態に係る半導体装置の断面図である。図５に示すように、本実施の形態は、半導体素子１と基板２の保護膜５より突出したバンプ８側壁にもＣｕとＡｕとの固溶体層１０が形成されている点において、第１及び第２の実施の形態と相違する。 (Third embodiment)
FIG. 5 is a cross-sectional view of a semiconductor device according to the third embodiment of the present invention. As shown in FIG. 5, this embodiment is different from the first embodiment in that a solid solution layer 10 of Cu and Au is also formed on the side wall of the bump 8 protruding from the protective film 5 of the semiconductor element 1 and the substrate 2. This is different from the second embodiment.
　図６Ａ～図６Ｈは、本発明の第３の実施の形態に係る半導体装置の製造方法を示す工程図である。本実施の形態では、バンプ８の平坦化加工まで第２の実施の形態と同様である〔図６Ａ～図６Ｄ〕。その後、ドライエッチング法等を用いて保護膜５を均一に所定量除去し、バンプ８の先端側を突出させる〔図６Ｅ〕。そして、Ａｕからなる接合材料９をバンプ８の先端に形成する。こうして、本実施の形態における半導体素子１及び基板２のＣｕバンプ８は、平坦化された先端側の面に接合材料９を形成してなる構造が得られる〔図６Ｆ〕。次に、このバンプ８に接合材料９が形成された半導体素子１と基板２とを用いて、対向する両方の電極部の位置が一致するように位置合わせを行う〔図６Ｇ〕。このとき、半導体素子１は、ダイシング加工によって所望のサイズに個片化がなされている。また、半導体素子１の裏面を研磨法等にて加工し所望の薄さに薄型化してもよい。基板２についても同様に個片化や薄型化を行ってもよい。その後、第１の実施の形態と同様に加圧、加熱し、半導体素子１と基板２は両方のバンプ８，８の間でＣｕとＡｕとの固溶体層１０が形成され、その固溶体層１０を介して接合される。最後に、半導体素子１と基板２との間に、アンダーフィル樹脂層１１を形成し本実施形態の半導体装置が得られる〔図６Ｈ〕。 6A to 6H are process diagrams showing a method of manufacturing a semiconductor device according to the third embodiment of the present invention. In the present embodiment, the process up to flattening of the bumps 8 is the same as in the second embodiment (FIGS. 6A to 6D). Thereafter, the protective film 5 is uniformly removed by a predetermined amount using a dry etching method or the like, and the tip side of the bump 8 is projected [FIG. 6E]. Then, a bonding material 9 made of Au is formed at the tip of the bump 8. Thus, the Cu bumps 8 of the semiconductor element 1 and the substrate 2 in the present embodiment have a structure in which the bonding material 9 is formed on the flattened tip side surface [FIG. 6F]. Next, alignment is performed using the semiconductor element 1 having the bonding material 9 formed on the bumps 8 and the substrate 2 so that the positions of both opposing electrode portions coincide with each other [FIG. 6G]. At this time, the semiconductor element 1 is separated into a desired size by dicing. Further, the back surface of the semiconductor element 1 may be processed by a polishing method or the like to be thinned to a desired thickness. Similarly, the substrate 2 may be singulated or thinned. Thereafter, pressurization and heating are performed in the same manner as in the first embodiment, and a solid solution layer 10 of Cu and Au is formed between the bumps 8 and 8 on the semiconductor element 1 and the substrate 2. Are joined. Finally, an underfill resin layer 11 is formed between the semiconductor element 1 and the substrate 2 to obtain the semiconductor device of this embodiment [FIG. 6H].
　本実施の形態では、先に保護膜５を均一に所定量除去しバンプ８を突出させることで、めっきにより接合材料９を形成する領域を先端に連なる先端近傍の側面にも増加させているため、表面積の小さい微細なバンプにおいてもめっき反応の起点ができ易く、Ａｕからなる接合材料９の供給バラツキや未析出を抑制することができる。従って、各バンプ間で安定した接合状態を得ることが可能である。 In the present embodiment, the protective film 5 is first removed uniformly by a predetermined amount and the bumps 8 are projected, so that the region where the bonding material 9 is formed by plating is also increased on the side surface in the vicinity of the tip that continues to the tip. Even in a fine bump having a small surface area, the starting point of the plating reaction can be easily performed, and supply variation and non-deposition of the bonding material 9 made of Au can be suppressed. Therefore, it is possible to obtain a stable bonding state between the bumps.
　また、本実施の形態では、先に保護膜５を均一に所定量除去し、バンプの先端側を突出させた後、Ａｕからなる接合材料９の形成工程を行う。その結果、保護膜５の除去時における接合材料表面への汚染がない。従って、接合材料表面の汚染による接合不良の発生を抑制できるため、信頼性の高い接合構造を得ることが可能である。 In the present embodiment, the protective film 5 is first uniformly removed by a predetermined amount, and the tip end side of the bump is protruded, followed by the step of forming the bonding material 9 made of Au. As a result, there is no contamination on the surface of the bonding material when the protective film 5 is removed. Therefore, since it is possible to suppress the occurrence of bonding failure due to contamination of the bonding material surface, it is possible to obtain a highly reliable bonding structure.
　（第４の実施の形態）
　図７は、本発明の第４の実施の形態に係る半導体装置の断面図である。図７に示すように、本実施の形態において、第１、第２、第３の実施の形態と相違する点は、半導体素子１の電極部に対向する、基板２の電極部がＡｕバンプ１３で構成されている点である。半導体素子１のバンプ８と基板２のＡｕバンプ１３とは、ＣｕとＡｕとの固溶体層１０を介して接合されている。ここで、固溶体層１０は、半導体素子１のＣｕバンプ８から基板２のＡｕバンプ１３に向けＣｕの濃度が均一に傾斜した傾斜層（反応層）である。そして、半導体素子１と基板２との間には、アンダーフィル樹脂層１１が形成されている。 (Fourth embodiment)
FIG. 7 is a sectional view of a semiconductor device according to the fourth embodiment of the present invention. As shown in FIG. 7, the present embodiment is different from the first, second, and third embodiments in that the electrode portion of the substrate 2 facing the electrode portion of the semiconductor element 1 is Au bump 13. It is the point comprised by. The bumps 8 of the semiconductor element 1 and the Au bumps 13 of the substrate 2 are joined via a solid solution layer 10 of Cu and Au. Here, the solid solution layer 10 is an inclined layer (reaction layer) in which the concentration of Cu is uniformly inclined from the Cu bump 8 of the semiconductor element 1 toward the Au bump 13 of the substrate 2. An underfill resin layer 11 is formed between the semiconductor element 1 and the substrate 2.
　本実施の形態では、第１から第３の実施の形態と同様に、ＣｕとＡｕとの固溶体層１０を介して半導体素子１と基板２の電極部同士を接合しており、この固溶体層１０は、半導体素子１側のバンプ８から基板２側のバンプ１３に向けてＣｕの濃度が少なくなるように傾斜した傾斜層（反応層）である。その結果、その接合部においては、元素の不連続部分がなく、機械的強度に優れている。また、拡散反応やエレクトロマイグレーション現象が進行しても、不連続な接合界面とはならないので、不良、クラックなどの起点が生じない。従って、信頼性を向上させることが可能となる。 In the present embodiment, as in the first to third embodiments, the electrode portions of the semiconductor element 1 and the substrate 2 are joined to each other through the solid solution layer 10 of Cu and Au. Is an inclined layer (reaction layer) inclined so that the concentration of Cu decreases from the bump 8 on the semiconductor element 1 side toward the bump 13 on the substrate 2 side. As a result, there is no element discontinuity in the joint, and the mechanical strength is excellent. Further, even if a diffusion reaction or an electromigration phenomenon proceeds, a discontinuous bonding interface does not occur, so that no starting point such as a defect or a crack occurs. Therefore, reliability can be improved.
　図８Ａ～図８Ｅは、本実施の形態で用いられる半導体装置の製造方法を示す工程図である。初めに、回路面上に設けられたＡｌ等からなる電極３と、その電極３上の一部に開口部を有した態様で回路面上を覆うＳｉＯＮやＳｉＯ２等からなる絶縁膜４とを有する基板２を作製又は準備する。この基板２の電極形成側に、スパッタ法等を用いてＴｉ等からなる密着層６とＣｕ等からなる接着層７を、その電極３と絶縁膜４の全面に形成する。そして、スピンコート等によって感光性のレジスト１２を接着層７上に供給し、露光現像することで電極上方のレジスト１２のみを除去し、電極３上に所望の大きさで開口部を形成する。更に、このレジスト１２の開口部に電解めっき法等でバンプ１３となるＡｕを析出させる〔図８Ａ〕。このとき、Ａｕバンプ１３の高さは各電極３間でバラツキが生じてもよい。 8A to 8E are process diagrams showing a method for manufacturing a semiconductor device used in the present embodiment. First, an electrode 3 made of Al or the like provided on the circuit surface and an insulating film 4 made of SiON, SiO 2 or the like covering the circuit surface in a form having an opening on a part of the electrode 3 are provided. A substrate 2 is prepared or prepared. An adhesion layer 6 made of Ti or the like and an adhesive layer 7 made of Cu or the like are formed on the entire surface of the electrode 3 and the insulating film 4 on the electrode forming side of the substrate 2 by sputtering or the like. Then, a photosensitive resist 12 is supplied onto the adhesive layer 7 by spin coating or the like, and only the resist 12 above the electrode is removed by exposure and development, and an opening having a desired size is formed on the electrode 3. Further, Au serving as the bumps 13 is deposited in the openings of the resist 12 by an electrolytic plating method or the like [FIG. 8A]. At this time, the height of the Au bump 13 may vary between the electrodes 3.
　次に、Ａｕバンプ１３の平坦化加工を行う。平坦化加工は、開口部に形成された電極部であるＡｕバンプ１３と、Ａｕバンプ１３以外のレジスト１２とを、機械研磨法、化学機械研磨法（ＣＭＰ）、研削加工等の各種の平坦化加工手段を用いて行う〔図８Ｂ〕。 Next, the Au bump 13 is flattened. In the flattening process, various kinds of flattening such as a mechanical polishing method, a chemical mechanical polishing method (CMP), and a grinding process are performed on the Au bump 13 which is an electrode portion formed in the opening and the resist 12 other than the Au bump 13. This is done using the processing means [FIG. 8B].
　次に、残りのレジスト１２を除去し、Ａｕバンプ１３の下以外に形成されている密着層６と接着層７とをウェットエッチング法等を用いて除去する。こうして、本実施の形態で用いられる基板２を得ることができる。この基板２は、平坦化されたＡｕバンプ１３を電極部として備える構造である〔図８Ｃ〕。 Next, the remaining resist 12 is removed, and the adhesion layer 6 and the adhesion layer 7 formed other than under the Au bumps 13 are removed using a wet etching method or the like. Thus, the substrate 2 used in this embodiment can be obtained. The substrate 2 has a structure including a flattened Au bump 13 as an electrode part [FIG. 8C].
　次に、このＡｕバンプ１３の構造を有する基板２と、第１の実施の形態で示した平坦化されたＣｕバンプ８とそのＣｕバンプ８の先端面に形成されたＡｕからなる接合材料９とを有した半導体素子１とを用いて、両方の電極部の位置が一致するように位置合を行う〔図８Ｄ〕。このとき、半導体素子１は、ダイシング加工によって所望のサイズに個片化がなされている。また、半導体素子１の裏面を研磨法等にて加工し所望の薄さに薄型化してもよい。基板２についても同様に個片化や薄型化を行ってもよい。 Next, the substrate 2 having the structure of the Au bump 13, the planarized Cu bump 8 shown in the first embodiment, and the bonding material 9 made of Au formed on the front end surface of the Cu bump 8; Positioning is performed using the semiconductor element 1 having a position so that the positions of both electrode portions coincide with each other [FIG. 8D]. At this time, the semiconductor element 1 is separated into a desired size by dicing. Further, the back surface of the semiconductor element 1 may be processed by a polishing method or the like to be thinned to a desired thickness. Similarly, the substrate 2 may be singulated or thinned.
　その後、Ｃｕバンプ８の接合材料９面と、Ａｕバンプ１３の先端面とが全て接触する程度に加圧し、Ｃｕバンプ８、接合材料９及びＡｕバンプ１３を所定の温度以上に加熱する。ここで、加熱方法は、基板側を常温又はＣｕとＡｕとの反応が急速に進行しない程度の予備加熱とし、半導体素子１側よりＣｕとＡｕを反応させるための加熱を行ってもよい。 Thereafter, the pressure is applied so that the bonding material 9 surface of the Cu bump 8 and the tip surface of the Au bump 13 are all in contact with each other, and the Cu bump 8, the bonding material 9 and the Au bump 13 are heated to a predetermined temperature or higher. Here, as the heating method, the substrate side may be preheated to room temperature or to the extent that the reaction between Cu and Au does not proceed rapidly, and heating for reacting Cu and Au from the semiconductor element 1 side may be performed.
　次に、この加熱状態を保持することによって基板２のＡｕバンプ１３及び半導体素子１の接合材料９であるＡｕと、半導体素子１のＣｕバンプ８との反応が進み、半導体素子１のＣｕバンプ８と基板２のＡｕバンプ１３との間でＣｕとＡｕとが固溶体化し、両側の電極部は固溶体層１０を介して接合される。最後に、半導体素子１と基板２との間に、樹脂を注入することによりアンダーフィル樹脂層１１を形成して、本発明の第４の実施の形態からなる半導体装置が得られる〔図８Ｅ〕。 Next, by maintaining this heated state, the reaction between the Au bump 13 of the substrate 2 and the Au that is the bonding material 9 of the semiconductor element 1 and the Cu bump 8 of the semiconductor element 1 proceeds, and the Cu bump 8 of the semiconductor element 1. Cu and Au form a solid solution between the Au bumps 13 of the substrate 2 and the electrode portions on both sides are joined via the solid solution layer 10. Finally, an underfill resin layer 11 is formed by injecting a resin between the semiconductor element 1 and the substrate 2 to obtain a semiconductor device according to the fourth embodiment of the present invention [FIG. 8E]. .
　本実施の形態では、半導体素子１の電極部と基板２の電極部の何れか一方のバンプをＣｕよりも変形しやすいＡｕで構成したので、接合時に、より低い実装荷重設定でバンプ表面同士を接触させることができ、その結果、半導体素子１への損傷を抑制することが可能である。 In the present embodiment, since either one of the bumps of the electrode part of the semiconductor element 1 and the electrode part of the substrate 2 is made of Au, which is easier to deform than Cu, the bump surfaces are bonded to each other with a lower mounting load setting at the time of bonding. As a result, damage to the semiconductor element 1 can be suppressed.
　本実施の形態においても、半導体素子１と基板２とを接合した構造を示したが、半導体素子１，１同士の接合や基板２，２同士の接合であってもよい。また、半導体素子１として、第１の実施の形態で示した平坦化されたＣｕバンプ８とＡｕからなる接合材料９の構造を用いたが、第２、第３の実施の形態で示した構造であってもよい。また更に、第１から第３の実施の形態で示した構造を半導体素子１又は基板２に用いる場合、Ａｕからなる接合材料９の供給を行わない構造を採ってもよい。また更に、Ａｕバンプ１３には平坦化処理を行わない構造や、Ａｕバンプ１３の先端側が尖った構造からなる先鋭形状の構造を取り入れてもよい。 Also in the present embodiment, the structure in which the semiconductor element 1 and the substrate 2 are joined is shown. However, the semiconductor elements 1 and 1 may be joined together or the substrates 2 and 2 may be joined together. Further, as the semiconductor element 1, the structure of the planarized Cu bump 8 and the bonding material 9 made of Au shown in the first embodiment is used, but the structure shown in the second and third embodiments is used. It may be. Furthermore, when the structures shown in the first to third embodiments are used for the semiconductor element 1 or the substrate 2, a structure in which the bonding material 9 made of Au is not supplied may be adopted. Still further, the Au bump 13 may be structured to have a sharpened structure composed of a structure in which the planarization process is not performed or a structure in which the tip side of the Au bump 13 is pointed.
　次に、実施例について、本発明の半導体装置の製造方法を示す図６Ａ～図６Ｈの例を参照して説明する。 Next, examples will be described with reference to the examples of FIGS. 6A to 6H showing the method for manufacturing a semiconductor device of the present invention.
　図６Ａ～図６Ｈに示すように、初めに、回路面上に設けられたＡｌ等からなる電極３と、その電極３上の一部に開口部を有した態様で回路面上を覆うＳｉＯＮからなる絶縁膜４とを有する半導体素子１及び基板２を準備した。この半導体素子１及び基板２の電極形成面側に、スパッタ法を用いてＴｉからなる密着層６とＣｕからなる接着層７を、その電極３と絶縁膜４の全面に形成した。そして、スピンコート法によって感光性のレジスト１２を接着層７上に形成し、露光現像することで電極上方のレジスト１２のみを除去し、電極３上に所望の大きさで開口部を形成した。更に、このレジスト１２の開口部に電解めっき法で厚さ８μｍとなるようにバンプ８となるＣｕを析出させた〔図６Ａ〕。ここで、バンプ８の高さは各電極３間で±２μｍのバラツキが生じていた。 As shown in FIGS. 6A to 6H, first, an electrode 3 made of Al or the like provided on the circuit surface, and SiON covering the circuit surface in a form having an opening on a part of the electrode 3 A semiconductor element 1 and a substrate 2 having an insulating film 4 were prepared. An adhesion layer 6 made of Ti and an adhesive layer 7 made of Cu were formed on the entire surface of the electrode 3 and the insulating film 4 by sputtering on the electrode formation surface side of the semiconductor element 1 and the substrate 2. Then, a photosensitive resist 12 was formed on the adhesive layer 7 by spin coating, and only the resist 12 above the electrode was removed by exposure and development, and an opening with a desired size was formed on the electrode 3. Further, Cu serving as the bumps 8 was deposited in the openings of the resist 12 by electrolytic plating so as to have a thickness of 8 μm [FIG. 6A]. Here, the height of the bump 8 was varied by ± 2 μm between the electrodes 3.
　次に、残りのレジスト１２をエッチング法で除去し、バンプ８の下以外に形成されている密着層６と接着層７とをウェットエッチング法で除去した〔図６Ｂ〕。 Next, the remaining resist 12 was removed by an etching method, and the adhesion layer 6 and the adhesive layer 7 formed other than under the bumps 8 were removed by a wet etching method (FIG. 6B).
　次に、バンプ８を覆うように、熱硬化性のポリイミド樹脂をスピンコート法によって供給し、熱硬化させて保護膜５を形成した〔図６Ｃ〕。このとき、バンプ８は最低１μｍ程度の厚さの保護膜５によって覆われていた。 Next, a thermosetting polyimide resin was supplied by a spin coating method so as to cover the bumps 8, and was thermally cured to form the protective film 5 [FIG. 6C]. At this time, the bump 8 was covered with the protective film 5 having a thickness of at least about 1 μm.
　そして、保護膜５とバンプ８を化学機械研磨法を用いてバンプ８の高さが５μｍとなるまで研磨し平坦化を行った〔図６Ｄ〕。ここで、Ｃｕのエッチングレートよりも保護膜５の研磨量の方が多くなるように、スラリーと加工条件を調整し、加工後の保護膜５の表面が隣接するバンプ８，８間で中央が窪んだ円弧状になるようにした。 Then, the protective film 5 and the bumps 8 were polished and planarized by using a chemical mechanical polishing method until the height of the bumps 8 became 5 μm [FIG. 6D]. Here, the slurry and the processing conditions are adjusted so that the polishing amount of the protective film 5 is larger than the etching rate of Cu, and the center of the surface of the protective film 5 after processing is between the adjacent bumps 8 and 8. It was made to become a hollow arc shape.
　その後、ドライエッチング法にて保護膜５を退化させ、バンプ８の先端側を２μｍ突出させた〔図６Ｅ〕。 Thereafter, the protective film 5 was degenerated by a dry etching method, and the tip side of the bump 8 was protruded by 2 μm [FIG. 6E].
　更に、無電解めっき法を用いて突出したバンプ８の表面にＡｕからなる接合材料９を形成することで、平坦化されたＣｕバンプ８の先端面とその先端面に連なる先端近傍の側面にもＡｕからなる接合材料９を形成した〔図６Ｆ〕。この無電解めっき法においては、置換Ａｕめっき浴を用いてＡｕ膜をＣｕバンプ８の先端面とその先端面に連なる先端近傍の側面とに０．０３μｍの厚さで形成した後、置換と還元の併用型のＡｕめっき浴を用いて最終的な接合材料９の厚さである０．１μｍに形成した。 Furthermore, by forming the bonding material 9 made of Au on the surface of the bump 8 protruding using the electroless plating method, the tip surface of the flattened Cu bump 8 and the side surface near the tip connected to the tip surface are also provided. A bonding material 9 made of Au was formed [FIG. 6F]. In this electroless plating method, an Au film is formed with a thickness of 0.03 μm on the tip surface of the Cu bump 8 and the side surface near the tip connected to the tip surface using a substitution Au plating bath, and then substitution and reduction are performed. The final bonding material 9 was formed to a thickness of 0.1 μm using a combination type Au plating bath.
　次に、このバンプ８に接合材料９が形成された半導体素子１と基板２とを用いて、対向する両方の電極部の位置が一致するように位置合わせを行った〔図６Ｇ〕。このとき、半導体素子１は、ダイシング加工によって８ｍｍ□サイズに個片化されたものとし、また研磨法にて半導体素子１の裏面は６００μｍの薄さに薄型化されたものとした。その後、対向する電極部の接合材料９面同士が全て接触するように７５Ｎ／Ｃｈｉｐで加圧し、加熱を行った。このときの加熱条件は、接合部が３００℃となるよう半導体素子１側より加熱を行った。次に、この加熱状態を１５ｓｅｃ間保持することによって、半導体素子１と基板２の両方の接合材料９であるＡｕと両方のバンプ８材料であるＣｕとの反応が進み、両方のバンプ８，８間でＣｕとＡｕとが固溶体化し、形成された固溶体層１０を介して接合された。ここで、接合後の固溶体層１０の状態は、両方のバンプ８，８から接合中心に向かってＣｕの濃度が少なくなるように傾斜し、接合中心のＣｕ濃度がＣｕバンプ８のバルク濃度に対して１０ａｔ％程度となっていた。また、見積もられた固溶体層１０の厚さは０．５μｍ程度であった。最後に、半導体素子１と基板２との間に、アンダーフィル樹脂層１１となる熱硬化性樹脂を基板２が７０℃となる温度で流し込み、１５０℃の環境温度のもと１時間加熱し加熱硬化することで本実施例の半導体装置を得た〔図６Ｈ〕。 Next, alignment was performed using the semiconductor element 1 having the bonding material 9 formed on the bump 8 and the substrate 2 so that the positions of both opposing electrode portions coincided with each other [FIG. 6G]. At this time, it was assumed that the semiconductor element 1 was diced into 8 mm □ size by dicing, and the back surface of the semiconductor element 1 was thinned to 600 μm by a polishing method. Then, it pressurized by 75 N / Chip so that all 9 surfaces of the joining material of the opposing electrode part might contact, and heated. The heating condition at this time was that heating was performed from the semiconductor element 1 side so that the bonding portion became 300 ° C. Next, by maintaining this heating state for 15 seconds, the reaction between Au, which is the bonding material 9 of both the semiconductor element 1 and the substrate 2, and Cu, which is the material of both the bumps 8, proceeds, and both the bumps 8, 8 Cu and Au were formed into a solid solution between them, and were joined via the formed solid solution layer 10. Here, the state of the solid solution layer 10 after the bonding is inclined so that the Cu concentration decreases from both the bumps 8 and 8 toward the bonding center, and the Cu concentration at the bonding center is larger than the bulk concentration of the Cu bump 8. It was about 10at%. Further, the estimated thickness of the solid solution layer 10 was about 0.5 μm. Finally, a thermosetting resin to be the underfill resin layer 11 is poured between the semiconductor element 1 and the substrate 2 at a temperature at which the substrate 2 becomes 70 ° C., and heated by heating at an environmental temperature of 150 ° C. for 1 hour. The semiconductor device of this example was obtained by curing [FIG. 6H].
　なお、この実施例では、接合材料であるＡｕの厚さを０．１μｍ、接合により形成される固溶体層の厚さを０．５μｍとしたが、接合材料の厚さ、バンプのめっき条件による結晶粒の大きさ、及び接合条件などによりそれらの厚さは変動する。 In this embodiment, the thickness of Au as the bonding material is 0.1 μm and the thickness of the solid solution layer formed by bonding is 0.5 μm. However, the crystal depending on the thickness of the bonding material and bump plating conditions is used. Their thickness varies depending on the size of the grains and joining conditions.
　ここで重要なことは、接合材料であるＡｕの厚さとバンプであるＣｕの厚さとの関係である。まず、接合材料であるＡｕの厚さは、接合プロセスにおけるＣｕ表面の酸化防止の機能も併せ持つことから、一方の電極部側で最低０．０３μｍの厚さとすることが好ましい。また、Ａｕの厚さの上限値は、両方の電極部の表面に供給されたＡｕの厚さの総和が１μｍを超える場合、電極またはバンプのＣｕとすべて反応させるために大きなエネルギーを与える必要があること、Ａｕのコストがかかり、生産性や経済的に好ましくないことから規定される。 Here, what is important is the relationship between the thickness of Au as a bonding material and the thickness of Cu as a bump. First, the thickness of Au, which is a bonding material, also has a function of preventing the oxidation of the Cu surface in the bonding process. Therefore, it is preferable that the thickness be at least 0.03 μm on one electrode side. Further, the upper limit of the thickness of Au needs to give a large energy in order to react with all Cu of the electrode or bump when the total thickness of Au supplied to the surfaces of both electrode parts exceeds 1 μm. It is specified because it is expensive and Au is not preferable in terms of productivity and economy.
　ここで、高温保管による電極部の拡散反応の進行が信頼性に与える影響を考慮することが重要であり、長期高温保管において、電極部にはＣｕが残存している必要がある。この観点から、半導体素子１と基板２の両方の電極あるいはバンプ表面に接合材料であるＡｕを０．１μｍ供給した場合において形成される固溶体層の厚さは０．５μｍ程度であったことから、一方の電極側でＣｕの厚さは少なくとも１μｍ以上必要となると考えられる。言い換えると、Ａｕの厚さに対するＣｕの厚さは１：１０以上の比率となり、１：３０以上の比率となることがより好ましい。さらに、本発明は上述した実施の形態のみに限定されるものではなく、既に述べた本発明の要旨を逸脱しない範囲において種々の変更が可能であることは勿論である。 Here, it is important to consider the influence of the progress of the diffusion reaction of the electrode part on the reliability due to high temperature storage, and Cu needs to remain in the electrode part in long-term high temperature storage. From this point of view, the thickness of the solid solution layer formed when 0.1 μm of Au as a bonding material is supplied to both electrodes or bump surfaces of the semiconductor element 1 and the substrate 2 is about 0.5 μm. It is considered that the thickness of Cu is required to be at least 1 μm or more on one electrode side. In other words, the thickness of Cu with respect to the thickness of Au is 1:10 or more, and more preferably 1:30 or more. Furthermore, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention described above.
　この出願は、２００８年３月３１日に出願された日本出願特願２００８－０９００９６を基礎とする優先権を主張し、その開示の全てをここに取り込む。 This application claims priority based on Japanese Patent Application No. 2008-090096 filed on March 31, 2008, the entire disclosure of which is incorporated herein.
　本発明は、特にフリップチップ方式の実装形態を用いた微細ピッチ接合に対応できる、半導体装置、複合回路装置及びそれらの製造方法に適応できる。 The present invention can be applied to a semiconductor device, a composite circuit device, and a manufacturing method thereof that can cope with fine pitch bonding using a flip-chip mounting form.

Claims (23)

  1. 　半導体素子上の第１電極部と基板上の第２電極部とが相互に対向するように電気的に接合された接合部と、
    　前記接合部に存在し、前記第１電極部の構成材料及び前記第２電極部の構成材料の一方又は両方と固溶する接合材料を含む固溶体領域とを有する半導体装置。     A joint part electrically joined so that the first electrode part on the semiconductor element and the second electrode part on the substrate face each other;
    A semiconductor device comprising: a solid solution region including a bonding material which is present in the bonding portion and which forms a solid solution with one or both of the constituent materials of the first electrode portion and the second electrode portion.
  2. 　前記固溶体領域は、前記第１電極部の構成材料と前記第２電極部の構成材料の一方又は両方の濃度が傾斜した傾斜層である、請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the solid solution region is an inclined layer in which the concentration of one or both of the constituent material of the first electrode portion and the constituent material of the second electrode portion is inclined.
  3. 　前記第１電極部の構成材料と前記第２電極部の構成材料がＣｕであり、前記接合材料がＡｕであり、前記固溶体領域がＣｕとＡｕからなる、請求項１又は２に記載の半導体装置。 3. The semiconductor device according to claim 1, wherein the constituent material of the first electrode portion and the constituent material of the second electrode portion are Cu, the bonding material is Au, and the solid solution region is made of Cu and Au. .
  4. 　前記第１電極部の構成材料と前記第２電極部の構成材料は一方がＣｕで他方がＡｕであり、前記固溶体領域がＣｕとＡｕからなる、請求項１又は２に記載の半導体装置。 3. The semiconductor device according to claim 1, wherein one of the constituent material of the first electrode portion and the constituent material of the second electrode portion is Cu and the other is Au, and the solid solution region is made of Cu and Au.
  5. 　前記第１電極部と前記第２電極部の一方又は両方がＣｕバンプであり、前記接合材料がＡｕであり、前記固溶体領域がＣｕバンプとＡｕからなる、請求項１から３のいずれか１項に記載の半導体装置。 One or both of the first electrode part and the second electrode part are Cu bumps, the bonding material is Au, and the solid solution region is made of Cu bumps and Au. A semiconductor device according to 1.
  6. 　前記第１電極部と前記第２電極部は一方がＣｕバンプで他方の構成材料がＡｕであり、前記固溶体領域がＣｕとＡｕからなる、請求項１，２，４のいずれか１項に記載の半導体装置。 5. The first electrode portion and the second electrode portion according to claim 1, wherein one of the first electrode portion and the second electrode portion is a Cu bump and the other constituent material is Au, and the solid solution region is made of Cu and Au. Semiconductor device.
  7. 　前記基板が半導体素子である、請求項１から６のいずれか１項に記載の半導体装置。 The semiconductor device according to claim 1, wherein the substrate is a semiconductor element.
  8. 　前記第１電極部と前記第２電極部の一方又は両方がバンプ構造からなり、隣接する接合部間には前記バンプの高さよりも低く且つ中央が窪んだ保護膜が設けられている、請求項１から７のいずれか１項に記載の半導体装置。 One or both of the first electrode part and the second electrode part have a bump structure, and a protective film that is lower than the height of the bump and has a depressed center is provided between adjacent joints. 8. The semiconductor device according to any one of 1 to 7.
  9. 　前記第１電極部と前記第２電極部の一方又は両方がバンプ構造からなり、前記接合部は、前記バンプの接合部側が平坦化した接合面を持つバンプで形成されてなる、請求項１から８のいずれか１項に記載の半導体装置。 One or both of said 1st electrode part and said 2nd electrode part consist of bump structures, and the said junction part is formed by the bump | vamp with the joint surface where the junction part side of the said bump was planarized. 9. The semiconductor device according to claim 1.
  10. 　前記固溶体領域の構成材料が全率固溶体型の材料からなる、請求項１から９のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 9, wherein a constituent material of the solid solution region is made of a solid solution material.
  11. 　半導体素子上の第１電極部と基板上の第２電極部とが電気的に接合される接合部が固溶体領域を有するように選択された金属材料からなる前記第１電極部と前記第２電極部とを形成し、
    　前記第１電極部と前記第２電極部とが相互に対向するよう位置合せし、
    　前記第１電極部と前記第２電極部とを加圧接触させ、
    　前記加圧接触させた状態で加熱し、
    　前記加熱した状態で保持して前記接合部に固溶体領域を形成する半導体装置の製造方法。     The first electrode portion and the second electrode made of a metal material selected so that a joint portion where the first electrode portion on the semiconductor element and the second electrode portion on the substrate are electrically joined has a solid solution region. Forming part with
    The first electrode portion and the second electrode portion are aligned so as to face each other,
    Pressure-contacting the first electrode part and the second electrode part,
    Heating in the pressure contact state,
    A method for manufacturing a semiconductor device, wherein the solid solution region is formed in the bonded portion while being held in the heated state.
  12. 　前記電極部の形成では、
    　前記半導体素子及び前記基板の一方又は両方の電極を覆うように密着層と接着層とを積層し、
    　前記接着層上にレジストを形成し、
    　電極上方のレジストを除去して開口部を形成し、
    　前記開口部を前記金属材料で埋めて前記電極部を形成し、
    　前記開口部に形成した電極部と該開口部以外のレジストとを加工して該電極部を平坦化し、
    　前記電極部上に前記固溶体領域を形成するための接合材料を供給し、
    　前記平坦化加工後のレジストを除去し、
    　前記電極部以外の前記密着層と前記接着層を除去する請求項１１に記載の半導体装置の製造方法。     In the formation of the electrode part,
    Laminating an adhesion layer and an adhesive layer so as to cover one or both electrodes of the semiconductor element and the substrate,
    Forming a resist on the adhesive layer;
    Remove the resist above the electrode to form an opening,
    Filling the opening with the metal material to form the electrode portion;
    Processing the electrode portion formed in the opening and a resist other than the opening to flatten the electrode portion;
    Supplying a bonding material for forming the solid solution region on the electrode portion;
    Removing the resist after the planarization,
    The method for manufacturing a semiconductor device according to claim 11, wherein the adhesion layer and the adhesive layer other than the electrode portion are removed.
  13. 　前記電極部の形成では、
    　前記半導体素子及び前記基板の一方又は両方の電極を覆うように密着層と接着層とを積層し、
    　前記接着層上にレジストを形成し、
    　電極上方のレジストを除去して開口部を形成し、
    　前記開口部を前記金属材料で埋めて前記電極部を形成し、
    　残りのレジストを除去し、
    　前記電極部以外の前記密着層と前記接着層を除去し、
    　前記電極部を覆うように保護膜を形成し、
    　前記電極部と前記保護膜を加工して該電極部を平坦化し、
    　前記電極部上に前記固溶体領域を形成するための接合材料を供給し、
    　前記保護膜を均一に所定量除去して前記電極部を突出させる請求項１１に記載の半導体装置の製造方法。     In the formation of the electrode part,
    Laminating an adhesion layer and an adhesive layer so as to cover one or both electrodes of the semiconductor element and the substrate,
    Forming a resist on the adhesive layer;
    Remove the resist above the electrode to form an opening,
    Filling the opening with the metal material to form the electrode portion;
    Remove the remaining resist,
    Removing the adhesive layer and the adhesive layer other than the electrode part,
    A protective film is formed so as to cover the electrode part,
    The electrode part and the protective film are processed to flatten the electrode part,
    Supplying a bonding material for forming the solid solution region on the electrode portion;
    The method of manufacturing a semiconductor device according to claim 11, wherein the protective film is uniformly removed by a predetermined amount to protrude the electrode portion.
  14. 　前記電極部の平坦化では、
    　前記レジスト又は保護膜のエッチングレートの方が速く、前記レジスト又は保護膜は前記接合部間の前記電極部の高さよりも低く且つ中央が窪むように加工する、請求項１２又は１３に記載の半導体装置の製造方法。     In the planarization of the electrode part,
    14. The semiconductor device according to claim 12, wherein the etching rate of the resist or the protective film is faster, and the resist or the protective film is processed so as to be lower than a height of the electrode portion between the joint portions and to be depressed in the center. Manufacturing method.
  15. 　前記電極部上への前記接合材料の供給では、無電解めっき法で行う、請求項１２から１４のいずれか１項に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to any one of claims 12 to 14, wherein the bonding material is supplied onto the electrode portion by an electroless plating method.
  16. 　前記電極部がＣｕバンプであり、前記接合材料がＡｕである、請求項１１から１５のいずれか１項に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 11, wherein the electrode portion is a Cu bump, and the bonding material is Au.
  17. 　前記電極部上への前記接合材料の供給では、置換Ａｕめっき浴を用いて前記ＣｕバンプにＡｕの薄膜を形成し、更に置換と還元の併用型のＡｕめっき浴を用いて所望の膜厚に形成する、請求項１６に記載の半導体装置の製造方法。 In supplying the bonding material onto the electrode part, an Au thin film is formed on the Cu bump using a substitution Au plating bath, and further, a desired thickness is obtained using a combination of substitution and reduction type Au plating bath. The method of manufacturing a semiconductor device according to claim 16, which is formed.
  18. 　半導体素子上の第１電極部と基板上の第２電極部とが電気的に接合する接合部が固溶体領域を有するように、一方をＣｕバンプとし、他方の構成材料をＡｕとする、前記第１電極部と前記第２電極部とを形成し、
    　前記第１電極部と前記第２電極部とが相互に対向するよう位置合せする位置合わせし、
    　前記第１電極部と前記第２電極部とを加圧接触させ、
    　前記加圧接触させた状態で加熱し、
    　前記加熱した状態で保持して前記接合部に固溶体領域を形成する半導体装置の製造方法。     The first electrode portion on the semiconductor element and the second electrode portion on the substrate are electrically connected to each other, and one of them is a Cu bump, and the other constituent material is Au, so that the joint portion has a solid solution region. Forming one electrode portion and the second electrode portion;
    Aligning the first electrode part and the second electrode part so that they face each other,
    Pressure-contacting the first electrode part and the second electrode part,
    Heating in the pressure contact state,
    A method for manufacturing a semiconductor device, wherein the solid solution region is formed in the bonded portion while being held in the heated state.
  19. 　前記Ｃｕバンプからなる電極部の形成では、
    　前記半導体素子及び前記基板の一方又は両方の電極を覆うように密着層と接着層とを積層し、
    　前記接着層上にレジストを形成し、
    　電極上方のレジストを除去して開口部を形成し、
    　前記開口部をＣｕで埋めて前記Ｃｕバンプを形成し、
    　前記開口部に形成したＣｕバンプと該開口部以外のレジストとを加工して該電極部を平坦化し、
    　前記平坦化加工後のレジストを除去し、
    　前記Ｃｕバンプ以外の前記密着層と前記接着層を除去する請求項１８に記載の半導体装置の製造方法。     In the formation of the electrode portion made of the Cu bump,
    Laminating an adhesion layer and an adhesive layer so as to cover one or both electrodes of the semiconductor element and the substrate,
    Forming a resist on the adhesive layer;
    Remove the resist above the electrode to form an opening,
    Filling the opening with Cu to form the Cu bump;
    Processing the Cu bump formed in the opening and a resist other than the opening to flatten the electrode part,
    Removing the resist after the planarization,
    The method for manufacturing a semiconductor device according to claim 18, wherein the adhesion layer and the adhesive layer other than the Cu bump are removed.
  20. 　前記Ｃｕバンプからなる電極部の形成では、
    　前記半導体素子及び前記基板の一方又は両方の電極を覆うように密着層と接着層とを積層し、
    　前記接着層上にレジストを形成し、
    　電極上方のレジストを除去して開口部を形成し、
    　前記開口部をＣｕで埋めて前記Ｃｕバンプを形成し、
    　残りのレジストを除去し、
    　前記Ｃｕバンプ以外の前記密着層と前記接着層を除去し、
    　前記Ｃｕバンプを覆うように保護膜を形成し、
    　前記Ｃｕバンプと前記保護膜を加工して該Ｃｕバンプを平坦化し、
    　前記保護膜を均一に所定量除去して前記Ｃｕバンプを突出させる請求項１８に記載の半導体装置の製造方法。     In the formation of the electrode portion made of the Cu bump,
    Laminating an adhesion layer and an adhesive layer so as to cover one or both electrodes of the semiconductor element and the substrate,
    Forming a resist on the adhesive layer;
    Remove the resist above the electrode to form an opening,
    Filling the opening with Cu to form the Cu bump;
    Remove the remaining resist,
    Removing the adhesion layer and the adhesive layer other than the Cu bump,
    A protective film is formed so as to cover the Cu bump,
    Process the Cu bump and the protective film to flatten the Cu bump,
    The method of manufacturing a semiconductor device according to claim 18, wherein the protective film is uniformly removed by a predetermined amount to protrude the Cu bump.
  21. 　前記Ｃｕバンプの平坦化では、
    　前記レジスト又は保護膜のエッチングレートの方が速く、前記レジスト又は保護膜は前記接合部間の前記電極部の高さよりも低く且つ中央が窪むように加工する、請求項１９又は２０に記載の半導体装置の製造方法。     In planarizing the Cu bump,
    21. The semiconductor device according to claim 19, wherein the etching rate of the resist or the protective film is higher, and the resist or the protective film is processed so as to be lower than a height of the electrode part between the joints and to be depressed in the center. Manufacturing method.
  22. 　回路板上の第１電極部と他の回路板上の第２電極部とが相互に対向するように電気的に接合された接合部と、
    　前記接合部に存在し、前記第１電極部の構成材料及び前記第２電極部の構成材料の一方又は両方と固溶する接合材料を含む固溶体領とを有する複合回路装置。     A joint part electrically joined so that the first electrode part on the circuit board and the second electrode part on the other circuit board face each other;
    A composite circuit device having a solid solution region including a bonding material which is present in the bonding portion and which forms a solid solution with one or both of the constituent material of the first electrode portion and the constituent material of the second electrode portion.
  23. 　回路板上の第１電極部と他の回路板上の第２電極部とが電気的に接合する接合部が固溶体領域を有するように選択された金属材料からなる前記第１電極部と前記第２電極部とを形成し、
    　前記第１電極部と前記第２電極部とが相互に対向するよう位置合せし、
    　前記第１電極部と前記第２電極部とを加圧接触させ、
    　前記加圧接触させた状態で加熱し、
    　前記加熱した状態で保持して前記接合部に固溶体領域を形成する複合回路装置の製造方法。     The first electrode portion and the first electrode portion made of a metal material selected so that the joint portion where the first electrode portion on the circuit board and the second electrode portion on the other circuit board are electrically joined has a solid solution region. Forming two electrode parts,
    The first electrode portion and the second electrode portion are aligned so as to face each other,
    Pressure-contacting the first electrode part and the second electrode part,
    Heating in the pressure contact state,
    A method of manufacturing a composite circuit device, which is held in the heated state and forms a solid solution region in the joint.
PCT/JP2009/054544 2008-03-31 2009-03-10 Semiconductor device, composite circuit device, and methods for manufacturing semiconductor device and composite circuit device WO2009122867A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010505517A JPWO2009122867A1 (en) 2008-03-31 2009-03-10 Semiconductor device, composite circuit device and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008090096 2008-03-31
JP2008-090096 2008-03-31

Publications (1)

Publication Number Publication Date
WO2009122867A1 true WO2009122867A1 (en) 2009-10-08

Family

ID=41135254

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2009/054544 WO2009122867A1 (en) 2008-03-31 2009-03-10 Semiconductor device, composite circuit device, and methods for manufacturing semiconductor device and composite circuit device

Country Status (2)

Country Link
JP (1) JPWO2009122867A1 (en)
WO (1) WO2009122867A1 (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011083524A1 (en) * 2010-01-05 2011-07-14 パナソニック株式会社 Semiconductor device, and method for producing same
JP2012204501A (en) * 2011-03-24 2012-10-22 Sony Corp Semiconductor device, electronic device, and semiconductor device manufacturing method
WO2013029656A1 (en) * 2011-08-30 2013-03-07 Ev Group E. Thallner Gmbh Method for permanently bonding wafers by a connecting layer by means of solid-state diffusion or phase transformation
JP2013140936A (en) * 2012-01-03 2013-07-18 ▲き▼邦科技股▲分▼有限公司 Semiconductor package manufacturing method and semiconductor package
JP2014130993A (en) * 2012-11-28 2014-07-10 Waseda Univ Process of manufacturing laminate structure
EP2873091A4 (en) * 2012-07-16 2016-03-30 Micron Technology Inc Pillar on pad interconnect structures, semiconductor dice and die assemblies including such interconnect structures, and related methods
CN105988958A (en) * 2014-09-22 2016-10-05 爱思开海力士有限公司 Semiconductor devices and semiconductor systems including the same
JP2017191945A (en) * 2017-05-25 2017-10-19 千住金属工業株式会社 Mounting method of metal core column
US9865565B2 (en) 2015-12-08 2018-01-09 Amkor Technology, Inc. Transient interface gradient bonding for metal bonds
US10037957B2 (en) 2016-11-14 2018-07-31 Amkor Technology, Inc. Semiconductor device and method of manufacturing thereof
JP2020009997A (en) * 2018-07-12 2020-01-16 上村工業株式会社 Conductive bump, and electroless platinum plating bath

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10790251B2 (en) * 2018-06-20 2020-09-29 Micron Technology, Inc. Methods for enhancing adhesion of three-dimensional structures to substrates

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08227917A (en) * 1994-12-22 1996-09-03 Toshiba Corp Mounting structure of semiconductor element, liquid crystal display and semiconductor device
JPH09252003A (en) * 1996-03-15 1997-09-22 Hitachi Ltd Bump forming method and manufacturing method of semiconductor device having bumps
JP2000068401A (en) * 1998-08-18 2000-03-03 Oki Electric Ind Co Ltd Semiconductor device and manufacture thereof
JP2003234367A (en) * 2002-02-07 2003-08-22 Nec Corp Semiconductor element and its manufacturing method, and semiconductor device and its manufacturing method
JP2003258034A (en) * 2002-03-06 2003-09-12 Mitsubishi Electric Corp Method for manufacturing multilayer wiring base and multilayer wiring base
JP2006245289A (en) * 2005-03-03 2006-09-14 Casio Micronics Co Ltd Semiconductor device and packaging structure

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08227917A (en) * 1994-12-22 1996-09-03 Toshiba Corp Mounting structure of semiconductor element, liquid crystal display and semiconductor device
JPH09252003A (en) * 1996-03-15 1997-09-22 Hitachi Ltd Bump forming method and manufacturing method of semiconductor device having bumps
JP2000068401A (en) * 1998-08-18 2000-03-03 Oki Electric Ind Co Ltd Semiconductor device and manufacture thereof
JP2003234367A (en) * 2002-02-07 2003-08-22 Nec Corp Semiconductor element and its manufacturing method, and semiconductor device and its manufacturing method
JP2003258034A (en) * 2002-03-06 2003-09-12 Mitsubishi Electric Corp Method for manufacturing multilayer wiring base and multilayer wiring base
JP2006245289A (en) * 2005-03-03 2006-09-14 Casio Micronics Co Ltd Semiconductor device and packaging structure

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011142119A (en) * 2010-01-05 2011-07-21 Panasonic Corp Semiconductor device and method of manufacturing the same
CN102656677A (en) * 2010-01-05 2012-09-05 松下电器产业株式会社 Semiconductor device, and method for producing same
WO2011083524A1 (en) * 2010-01-05 2011-07-14 パナソニック株式会社 Semiconductor device, and method for producing same
US8575749B2 (en) 2010-01-05 2013-11-05 Panasonic Corporation Semiconductor device and method for fabricating the same
JP2012204501A (en) * 2011-03-24 2012-10-22 Sony Corp Semiconductor device, electronic device, and semiconductor device manufacturing method
KR101927559B1 (en) 2011-08-30 2018-12-10 에베 그룹 에. 탈너 게엠베하 Method for permanently bonding wafers by a connecting layer by means of solid-state diffusion or phase transformation
WO2013029656A1 (en) * 2011-08-30 2013-03-07 Ev Group E. Thallner Gmbh Method for permanently bonding wafers by a connecting layer by means of solid-state diffusion or phase transformation
CN103548129A (en) * 2011-08-30 2014-01-29 Ev集团E·索尔纳有限责任公司 Method for permanently bonding wafers by a connecting layer by means of solid-state diffusion or phase transformation
US10163681B2 (en) 2011-08-30 2018-12-25 Ev Group E. Thallner Gmbh Method for permanently bonding wafers by a connecting layer by means of solid state diffusion or phase transformation
JP2014529899A (en) * 2011-08-30 2014-11-13 エーファウ・グループ・エー・タルナー・ゲーエムベーハー Permanent wafer bonding method with connecting layer using solid phase diffusion or phase transformation
JP2013140936A (en) * 2012-01-03 2013-07-18 ▲き▼邦科技股▲分▼有限公司 Semiconductor package manufacturing method and semiconductor package
EP2873091A4 (en) * 2012-07-16 2016-03-30 Micron Technology Inc Pillar on pad interconnect structures, semiconductor dice and die assemblies including such interconnect structures, and related methods
JP2014130993A (en) * 2012-11-28 2014-07-10 Waseda Univ Process of manufacturing laminate structure
CN105988958A (en) * 2014-09-22 2016-10-05 爱思开海力士有限公司 Semiconductor devices and semiconductor systems including the same
CN105988958B (en) * 2014-09-22 2019-11-19 爱思开海力士有限公司 Semiconductor devices and semiconductor system including semiconductor devices
US9865565B2 (en) 2015-12-08 2018-01-09 Amkor Technology, Inc. Transient interface gradient bonding for metal bonds
KR102061420B1 (en) * 2015-12-08 2019-12-31 앰코 테크놀로지 인코포레이티드 Transient interface gradient bonding for metal bonds
US10037957B2 (en) 2016-11-14 2018-07-31 Amkor Technology, Inc. Semiconductor device and method of manufacturing thereof
JP2017191945A (en) * 2017-05-25 2017-10-19 千住金属工業株式会社 Mounting method of metal core column
TWI655985B (en) * 2017-05-25 2019-04-11 日商千住金屬工業股份有限公司 Metal core column assembly method
JP2020009997A (en) * 2018-07-12 2020-01-16 上村工業株式会社 Conductive bump, and electroless platinum plating bath
JP7148300B2 (en) 2018-07-12 2022-10-05 上村工業株式会社 Conductive Bump and Electroless Pt Plating Bath

Also Published As

Publication number Publication date
JPWO2009122867A1 (en) 2011-07-28

Similar Documents

Publication Publication Date Title
WO2009122867A1 (en) Semiconductor device, composite circuit device, and methods for manufacturing semiconductor device and composite circuit device
KR100621438B1 (en) Stack chip package using photo sensitive polymer and manufacturing method thereof
KR100609334B1 (en) Stack circuit member gap-filled photo sensitive polymer and method for manufacturing thereof
KR102616760B1 (en) Semiconductor package and fabricating method thereof
TWI593082B (en) Semiconductor device and method of manufactures
TWI692820B (en) Semiconductor device and manufacturing method thereof
KR100488126B1 (en) Semiconductor device and manufacturing method thereof
TWI499009B (en) Device packaging with substrates having embedded lines and metal defined pads
JP5585447B2 (en) Semiconductor device and manufacturing method thereof
US7420273B2 (en) Thinned die integrated circuit package
US20140295620A1 (en) Method of manufacturing semiconductor device having plural semiconductor chips stacked one another
TWI236133B (en) Semiconductor device and manufacturing method of same
US8610269B2 (en) Semiconductor device, method for manufacturing semiconductor device, and circuit device using semiconductor device
TWI381459B (en) Semiconductor device and manufacturing method thereof
JPH10135404A (en) Semiconductor chip module and its manufacture
JP2001237268A (en) Method for mounting semiconductor element and apparatus for manufacturing the same
JP2004165277A (en) Electronic component mounting structure and manufacturing method therefor
JP6656836B2 (en) Mounting structure and method of manufacturing the same
TWI420610B (en) Semiconductor device and manufacturing method therefor
JP7472484B2 (en) Composite wiring board and method for manufacturing the same
TW202322329A (en) Multiple die assembly
WO2020122014A1 (en) Wiring board for semiconductor device, method of manufacturing same, and semiconductor device
US20050074971A1 (en) Semiconductor device and method for fabricating the same
JP4454454B2 (en) Semiconductor element and semiconductor element mounting board on which the semiconductor element is mounted
TW202312374A (en) Stiffener frame for semiconductor device packages

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09726905

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2010505517

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09726905

Country of ref document: EP

Kind code of ref document: A1