JP2004253598A - Method for packaging electronic component - Google Patents

Method for packaging electronic component Download PDF

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Publication number
JP2004253598A
JP2004253598A JP2003042117A JP2003042117A JP2004253598A JP 2004253598 A JP2004253598 A JP 2004253598A JP 2003042117 A JP2003042117 A JP 2003042117A JP 2003042117 A JP2003042117 A JP 2003042117A JP 2004253598 A JP2004253598 A JP 2004253598A
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Prior art keywords
circuit board
bonding
tin
semiconductor chip
electrode group
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JP2003042117A
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Japanese (ja)
Inventor
Keishiro Okamoto
圭史郎 岡本
Masataka Mizukoshi
正孝 水越
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Fujitsu Ltd
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Fujitsu Ltd
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Priority to JP2003042117A priority Critical patent/JP2004253598A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To increase the reliability of junction parts between electrodes of electronic components and electrodes of an electronic circuit board, to secure the reliability of insulation between adjacent electrodes, and to package the electronic components to the electronic circuit board at a low cost. <P>SOLUTION: A method for packaging the electronic components comprises the steps of firstly positioning the electronic components to the electronic circuit board with the use of a conventional positioning device, heating to melt a plurality of first projecting parts composed of a low melting point material formed on the electronic components, contacting the melted first projecting parts to a second projecting part on the electronic circuit board formed by the same material as that of the first projecting parts, and secondly positioning with self-alignment by a stress caused by an integration of the melted first and second projecting parts. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、電子部品の回路基板への実装、より詳しくは半導体チップを回路基板にフリップチップ実装する方法に関する。
【０００２】
【従来の技術】
近年の電子機器の小型化、薄膜化に伴い、電子部品の高密度実装の要求が高まっており、半導体チップなどの電子部品をダイシングで切り出したベアチップの状態でダイレクトに基板に搭載するフリップチップ実装が、用いられてきた。フリップチップ実装に使用する半導体チップの電極上には突起電極が形成されており、突起電極と回路基板上の配線とを電気的に接合する。
【０００３】
フリップチップ実装には、鉛や錫などの低融点金属あるいは低融点金属合金等の所謂半田バンプをチップの実装面に形成していた。一方、チップを実際に実装する電子配線基板等にも、チップの半田バンプと対応する位置に半田バンプを形成し、対応するチップの半田バンプと接触させた後に加熱する。加熱によりチップと基板の半田バンプを溶融させて、たとえ対応する半田バンプ同士が正確に当接していなくても、半導体チップの溶融した半田バンプと対応する回路基板の溶融した半田バンプとが安定な状態の一つの半田バンプになろうとする応力が働くため、自己整合的（セルフアライン的）に的にチップが微動し、回路基板に半導体チップが正確に実装される。
【０００４】
従来は、この半田バンプのセルフアライメント効果を利用してきた。しかしながら、この手法では、半田溶融を利用するため、さらなる高密度実装に伴う多ピン化、狭ピッチ化に対しては限界がある。例えば、隣接する半田バンプ同士が、溶融により繋がってしまう半田ブリッジなどの問題点があった。
【０００５】
そこで、半田溶融を用いない別の実装方法として、圧接接合が利用され始めている。この圧接接合では、例えば、加熱しながら圧着する方法や接合時に超音波をかける方法がある。更に、加熱しながら圧着する時に超音波を併用することによるワイヤボンディング法や、絶縁シートまたは絶縁フィルム、あるいは、導電粒子を分散させた異方性導電シートを介して、バンプ同士を熱圧着する方法、絶縁シートあるいは絶縁フィルムを介して、Ａｕバンプをパッド電極に圧着する方法など多数の方法がある。
【０００６】
また、圧接接合で生じるバンプ直下のＬＳＩ素子へのダメージを低減する接合方法として、半導体チップ上のバンプ表面、および、パッド表面に、原子あるいはイオンのエネルギービームなどのプラズマを照射して、接合面の汚染物を除去して、接合面を活性化した後、接合面同士を密着させて加圧し、固相接合する方法も開発されている。
【０００７】
一方、バンプとパッド間の接合部分の接続信頼性を確保するために、半導体チップと回路基板の間隙に、前述の絶縁シートあるいは絶縁フィルム、または、アンダーフィル材とよばれる液状樹脂を充填し硬化させる方法などの例もある（例えば、特許文献１参照。）。
【０００８】
【特許文献１】
特開２００１−３５８８４号公報（第２頁−第３頁、図１）
【０００９】
【発明が解決しようとする課題】
前記の従来技術を突起電極と回路基板上の配線との接合に用いると、次のような問題が発生する。
【００１０】
導電性の硬化性樹脂を塗布して、接合後に硬化させる方法は、半導体チップの突起電極と回路基板の電極間に導電性粒子を介した接合であるので、直接突起電極と回路基板の電極同士を接合するよりも、接続信頼性が低下するという課題を有する。
【００１１】
また、特開２００１−３５８８４号公報に開示されたように、半導体チップと回路基板の隙間に、絶縁シートや絶縁フィルム、または、アンダーフィル材とよばれる液状樹脂を充填し硬化させる方法は、半導体チップと回路基板との間隔が数１０μｍから５００μｍと狭い場合では、未充填部が発生しやすく、半導体チップの動作が不安定となり、耐湿信頼性が低くなるという問題点がある。
【００１２】
また、絶縁樹脂フィルムを用いずに、半導体チップの電極接合面および基板の電極接合面に原子あるいはイオンのエネルギービームなどのプラズマを照射し、接合面の汚染物をエッチング除去して、接合面を活性化した後、接合面同士を密着させて加圧し固相接合する方法では、半導体チップや回路基板が反りを有する場合、反り矯正のための加圧により、半導体チップへのダメージが大きくなる。
【００１３】
更に、バンプサイズがさらに微細化し、接続ピッチが数〜１０μｍ程度になると、半導体チップと回路基板とのアライメント精度は非常に厳しく１μｍ以下は必要となる。すなわち、通常使用されているフリップチップボンダのアライメント精度５μｍ程度では、バンプ接続後、隣接バンプ間で短絡が生じる。また、１μｍ以下のアライメント精度を実現するためには、設備的に余分なコストがかかり、低コストでの高密度実装が実現できない。
【００１４】
そこで、本発明の目的は、電子部品の電極と電子回路基板の電極との接合部の信頼性を高め、隣接電極間の絶縁信頼性を確保し、低コストで電子部品の電極を回路基板に接続する半導体装置の製造方法を提供することにある。
【００１５】
【課題を解決するための手段】
上記の目的を達成するために、本発明の一つの側面は、電子回路基板上に電子部品を実装する方法であって、電子部品は第１の突起電極群と低融点材料からなる複数の第１の突起部とを有し、電子回路基板は第１の突起電極群に対応する第２の突起電極群と第１の突起部に対応し低融点材料からなる第２の突起部とを有し、その方法は、第１及び第２の突起部を溶融結合する工程と、溶融接合の後、第１の突起電極群と第２の突起電極群とを固相接合する工程とを含むことを特徴とする電子部品の実装方法にある。
【００１６】
この様な実装方法を行なうことにより、第１及び第２の突起部が自己整合的に位置合わせを行なうので、従来通りの接合装置を用いることができる。
【００１７】
【発明の実施の形態】
以下、図面を参照して本発明の実施の形態例を説明する。しかしながら、本発明の保護範囲は、以下の実施の形態例に限定されるものではなく、特許請求の範囲に記載された発明とその均等物にまで及ぶものである。
【００１８】
図１は、本発明の実施の形態例をしめす半導体チップと、その実装面の突起電極と半田バンプ示す上面図である。また、図２は、半導体チップを回路基板に実装する方法を示す図である。以下、図１及び図２を用いて本発明の実施の形態例について説明する。また、同一部分には、同一な符号を用いている。
【００１９】
図１において、半導体チップ１の実装面には、突起電極３が形成され、半導体チップ１の外周４カ所に低融点金属等からなる突起が形成されている。この突起は、例えば無電解めっきされた突起電極３よりも厚い半田バンプ２である。この半田バンプは、公知の方法で形成される。
【００２０】
図２（１）において、回路基板４には、半導体チップ１の突起電極３に対応する基板の突起電極５と、半導体チップ１の半田バンプ２に対応した基板の半田バンプ６が形成されている。回路基板に形成された突起電極５と半田バンプ６の厚みは、ほぼ同等でよい。また、回路基板４の突起電極も無電解めっき法等で形成することができる。半田バンプ２及び６は半導体チップ１や回路基板４と、電気的導通が取られていなくともよい。
【００２１】
一般に、無電解めっき等で形成された突起電極の材質は、酸化しにくく、且つ加工性に富んだ柔らかい金属材料や合金材料が望ましく、高価ではあるが金（Ａｕ）が最も適した材料である。
【００２２】
また、使用される半田材について簡単に説明する。２元合金としては、錫と銀、錫と銅、錫とビスマス、錫とインジウム、錫とアルミ等である。また、３元合金としては、錫と銀と銅、錫と金と亜鉛などが挙げられる。以上列挙した中で、半田材として優れているのは、３元合金である。しかしながら、安価な上取り扱いの容易な錫と銀の２元合金も多用されている。
【００２３】
以上のように準備された半導体チップ１及び回路基板４は、図示しないアルゴンプラズマが照射可能な雰囲気を有するチャンバ内に、搬入され突起電極３を形成した半導体チップ及び回路基板４の突起電極５を設置し、突起電極３及び５の表面にアルゴンプラズマを照射させて、エッチングする。
【００２４】
これにより、突起電極３及び５の酸化膜、水分、及び油脂分等の汚染物質を除去し、突起電極表面をクリーンにし活性化させる。また、電極表面の酸化物を除去する方法として、加熱したカルボン酸、例えば２５０℃の蟻酸蒸気中にて、酸化物を還元することも可能である。
【００２５】
次に、半導体チップ１および回路基板４の突起電極界面の活性状態を維持するため、大気に触れないように前記チャンバを不活性ガスでパージし、半導体チップ１と回路基板４を接合させる装置を含む不活性ガス雰囲気の充填されたチャンバの内に搬送する。搬送中も、半導体チップ１と回路基板４は不活性ガス雰囲気中に保たれ、大気に晒されることはない。これによって、半導体チップと回路基板の突起電極の接合時において、半導体チップおよび回路基板の突起電極表面の活性化状態を維持できる。
【００２６】
半導体チップ１と回路基板４が、接合装置を含むチャンバ内に搬送された後、絶縁樹脂フィルム７を図示しないフィルムローダーから搬送して図２（２）に示すとおり回路基板４の突起電極５上に配置する。この時、回路基板上の半田バンプ６上には、絶縁樹脂フィルムを配置しないよう注意が必要である。
【００２７】
この絶縁樹脂フィルム７は、特に材料を限定しないが、熱硬化性、熱可塑性を有する材料、またはそれらの混合物などが望ましい。
【００２８】
そして、図示しない公知の位置合わせ装置によって、半導体チップ１と回路基板４との突起電極３及び５の第１の位置合わせを行なう。この合わせは、特別高精度な合わせ装置を用いなくともよい。例えば、アライメント精度は５μｍ程度で充分である。
【００２９】
第１の合わせが終了した後、半導体チップ１をヒーター等で加熱する。この時の加熱温度は半田バンプが溶融する温度であればよく、例えば２００℃程度である。この時、半導体チップ１に形成されていた半田バンプ２は溶融して半球形状２’になる。
【００３０】
次に、図２（３）に示すとおり、加熱により、半導体チップの外周部４隅に配置された半田バンプは、溶融して半球形２’となり、対応する回路基板の半田６に接触して、溶融した半田２’及び６が相互に一体となろうとする応力により半導体チップが位置を微動し、自己整合的に第２の位置合わせがなされる。この合わせが行なわれている時は、半導体チップ１に形成された突起電極３は、絶縁樹脂フィルム７には接触していない。従って、半導体チップ１は、微動できる状態にある。
【００３１】
この位置合わせによって、半導体チップ１と回路基板４の対応する突起電極同士３及び５が正確に位置合わせされる。そして、図２（３）に示すように、半導体チップ１を加圧し且つ加熱する。溶融した半田バンプは溶融したまま一体化して、ほぼ球形２’’となる。また、加圧することで、半導体チップ１の突起電極３は、絶縁樹脂フィルム７に挿入されていく。
【００３２】
更に、図２（４）に示すとおり、加圧を続けることで突起電極３は絶縁樹脂フィルムを突き破り、半導体チップの突起電極３と、回路基板４の突起電極５とは接触するに至る。この時の加熱温度は１５０℃以下或いは常温である。また加圧時の雰囲気はアルゴンの他、窒素、酸素を含む気相中とする。また、チャンバ内の圧力は１ａｔｏｍ以下の減圧下としてもよい。
【００３３】
この様な雰囲気内で加圧すると、半導体チップ１および回路基板４の突起電極３及び５は、半導体チップ１及び回路基板４の反りを矯正しながら、絶縁樹脂フィルム７を突き破り、絶縁樹脂フィルムが突起電極の間に入り込むことなしに硬化され、半導体チップの外周部の半田材は、さらに接続を維持しながらつぶれる。そして、半導体チップ１と回路基板４の突起電極同士が、低応力で固相接合され、ほぼ一体の金属プラグ状８になる。この金属プラグ８は、突起電極３と５の結合部が観察できないほど強固に接合される。
【００３４】
また、被接続部品の間に接着フィルムを挟んで加熱・加圧させる際に、付加的に被接続部品に超音波振動を付与してもよい。超音波振動を与えることで、加熱温度を低く抑えることができる。従って、高温加熱による被接続部品のダメージを低減することができる。
【００３５】
更に、本実施の形態例では、半導体チップ１と回路基板４に４カ所の半田バンプを設けたが、３カ所であってもよい。また、フリップチップ実装では、電極の取り出しを突起電極等で行なうが、突起電極等の位置は半導体チップによってまちまちなため、様々な変形例が挙げられる。
【００３６】
図３は、半田バンプと突起電極の配置例（１）を示す図である。また、図４は、半田バンプと突起電極の配置例（２）を示す図である。図３（ａ）は、本実施の形態例での半田バンプ配置方法であり、図３（ｂ）、（ｃ）は共に外周４隅に半田バンプが形成されている例について示している。
【００３７】
また、図４（ｄ）、（ｅ）では半導体チップの外周を突起電極で囲まれて、半導体チップの中央付近に４個の半田バンプが形成される例を示している。更に、図４（ｆ）、（ｇ）では、半田バンプは８個形成されており、半導体チップ１の外周４隅にあると同時にチップ中央付近にも４個形成されている。
【００３８】
これらの半田バンプの形成例は、図３、図４に限定されるものではなく半導体チップ１の電極の配置によって、種々の変形が可能である。
【００３９】
以上、実施の形態例をまとめると以下の付記の通りである。
【００４０】
（付記１）電子回路基板上に電子部品を実装する方法であって、
前記電子部品は第１の突起電極群と低融点材料からなる複数の第１の突起部とを有し、前記電子回路基板は該第１の突起電極群に対応する第２の突起電極群と該第１の突起部に対応し低融点材料からなる第２の突起部とを有し、
前記方法は、
前記第１及び第２の突起部を溶融結合する工程と、
前記溶融接合の後、前記第１の突起電極群と第２の突起電極群とを固相接合する工程と
を含むことを特徴とする電子部品の実装方法。
【００４１】
（付記２）付記１において、
更に、前記溶融結合する工程の前に、前記第２の突起電極群上に絶縁性フィルムを被覆する工程と
前記溶融結合する工程後に、前記電子部品を加圧して前記第１の突起電極群に前記絶縁性フィルムを貫通させ該第１の突起電極と第２の突起電極群とを固相接合させる工程と
を含むことを特徴とする電子部品の実装方法。
【００４２】
（付記３）付記１において、
前記低融点材料が、錫と銀、錫と銅、錫とビスマス、錫とインジウム、錫とアルミの２元合金か、錫と銀と銅、錫と金と亜鉛の３元合金から選択された１つの材料であることを特徴とする電子部品の実装方法。
【００４３】
（付記４）付記１又は２において、
更に、溶融結合する工程前に、第１及び第２の突起電極群をプラズマ雰囲気中に晒し、第１及び第２の突起電極をクリーニングする工程を含むことを特徴とする電子部品の実装方法。
【００４４】
（付記５）付記１において、
更に、溶融結合する工程前に、位置合わせ装置によって電子部品と電子回路基板の位置合わせをする工程を有すること
を特徴とする電子部品の実装方法。
【００４５】
（付記６）付記１において、
前記複数の第１の突起部が前記第１の突起電極群の突起電極よりも大きいことを特徴とする電子部品の実装方法。
【００４６】
（付記７）付記１において、
前記溶融結合する工程が第１の温度で行なわれ、前記固相結合する工程が第１の温度より低い第２の温度で行なわれること
を特徴とする電子部品の実装方法。
【００４７】
（付記８）付記１において、
前記溶融結合する工程が、不活性ガス雰囲気中で行なわれること
を特徴とする電子部品の実装方法。
【００４８】
（付記９）付記１において、
前記第１及び第２の突起電極群の材質が金であること
を特徴とする電子部品の実装方法。
【００４９】
【発明の効果】
以上、本発明によれば、電子部品の電極と電子回路基板の電極との接合部の信頼性を高め、隣接電極間の絶縁信頼性を確保すると共に、低コストで電子部品を電子回路基板に実装することができる。
【図面の簡単な説明】
【図１】本発明の実施の形態例をしめす半導体チップと、その実装面の突起電極と半田バンプ示す上面図である。
【図２】半導体チップを回路基板に実装する方法を示す図である。
【図３】半田バンプと突起電極の配置例（１）を示す図である。
【図４】半田バンプと突起電極の配置例（２）を示す図である。
【符号の説明】
１ 半導体チップ
２ 半導体チップに形成された半田バンプ
３ 半導体チップに形成された突起電極
４ 回路基板
５ 回路基板に形成された突起電極
６ 回路基板に形成された半田バンプ
７ 絶縁樹脂フィルム
８ 固相接合した突起電極[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for mounting electronic components on a circuit board, and more particularly to a method for flip-chip mounting a semiconductor chip on a circuit board.
[0002]
[Prior art]
The demand for high-density mounting of electronic components is increasing with the recent miniaturization and thinning of electronic devices. Flip-chip mounting, in which electronic components such as semiconductor chips are directly mounted on a board in the form of bare chips cut out by dicing. Has been used. A protruding electrode is formed on an electrode of a semiconductor chip used for flip chip mounting, and electrically connects the protruding electrode to a wiring on a circuit board.
[0003]
In flip-chip mounting, a so-called solder bump made of a low melting point metal such as lead or tin or a low melting point metal alloy is formed on the chip mounting surface. On the other hand, also on an electronic wiring board or the like on which a chip is actually mounted, a solder bump is formed at a position corresponding to the solder bump of the chip, and is heated after being brought into contact with the solder bump of the corresponding chip. The solder bumps on the chip and the substrate are melted by heating, so that the molten solder bumps on the semiconductor chip and the corresponding circuit board are stable even if the corresponding solder bumps do not abut correctly. Since a stress acts to become one of the solder bumps in the state, the chip slightly moves in a self-aligned (self-aligned) manner, and the semiconductor chip is accurately mounted on the circuit board.
[0004]
Conventionally, the self-alignment effect of the solder bump has been used. However, in this method, since solder melting is used, there is a limit to increasing the number of pins and narrowing the pitch due to higher density mounting. For example, there is a problem such as a solder bridge in which adjacent solder bumps are connected by melting.
[0005]
Therefore, as another mounting method that does not use solder melting, pressure bonding has begun to be used. In this pressure welding, for example, there is a method of performing pressure bonding while heating or a method of applying ultrasonic waves during bonding. Furthermore, a method of thermocompression bonding of bumps through an insulating sheet or an insulating film, or an anisotropic conductive sheet in which conductive particles are dispersed, using a wire bonding method by using ultrasonic waves at the time of pressing while heating. There are many methods such as a method of pressing an Au bump to a pad electrode via an insulating sheet or an insulating film.
[0006]
As a bonding method for reducing damage to an LSI element immediately below a bump caused by pressure bonding, a bump surface and a pad surface on a semiconductor chip are irradiated with plasma such as an atom or ion energy beam to form a bonding surface. After removing contaminants and activating the bonding surfaces, a method has been developed in which the bonding surfaces are brought into close contact with each other and pressurized to perform solid-phase bonding.
[0007]
On the other hand, in order to ensure the connection reliability of the joint between the bump and the pad, the gap between the semiconductor chip and the circuit board is filled with the above-mentioned insulating sheet or insulating film or liquid resin called underfill material and cured. There is also an example of such a method (for example, see Patent Document 1).
[0008]
[Patent Document 1]
JP 2001-35884 A (Pages 2 to 3, FIG. 1)
[0009]
[Problems to be solved by the invention]
When the above-described conventional technique is used for joining the protruding electrode and the wiring on the circuit board, the following problem occurs.
[0010]
The method of applying a conductive curable resin and curing it after bonding is a bonding via conductive particles between the protruding electrodes of the semiconductor chip and the electrodes of the circuit board, so that the protruding electrodes are directly connected to the electrodes of the circuit board. Has a problem that the connection reliability is reduced as compared with bonding.
[0011]
Further, as disclosed in Japanese Patent Application Laid-Open No. 2001-35884, a method of filling and curing an insulating sheet, an insulating film, or a liquid resin called an underfill material in a gap between a semiconductor chip and a circuit board is disclosed in Japanese Patent Application Laid-Open No. 2001-35884. When the distance between the chip and the circuit board is as narrow as several tens of μm to 500 μm, there is a problem that an unfilled portion is easily generated, the operation of the semiconductor chip becomes unstable, and the humidity resistance reliability is lowered.
[0012]
Also, without using an insulating resin film, the electrode bonding surface of the semiconductor chip and the electrode bonding surface of the substrate are irradiated with plasma such as an energy beam of an atom or an ion, and contaminants on the bonding surface are removed by etching. In the method in which the bonding surfaces are brought into close contact with each other and pressurized after activation, when the semiconductor chip or the circuit board has a warp, the semiconductor chip is greatly damaged by the pressurization for correcting the warp.
[0013]
Further, when the bump size is further miniaturized and the connection pitch becomes about several to 10 μm, the alignment accuracy between the semiconductor chip and the circuit board becomes very strict and 1 μm or less is required. That is, if the alignment accuracy of a commonly used flip chip bonder is about 5 μm, short-circuiting occurs between adjacent bumps after bump connection. Further, in order to realize an alignment accuracy of 1 μm or less, extra cost is required for equipment, and high-density mounting at low cost cannot be realized.
[0014]
Therefore, an object of the present invention is to enhance the reliability of the joint between the electrode of the electronic component and the electrode of the electronic circuit board, secure the insulation reliability between adjacent electrodes, and attach the electrode of the electronic component to the circuit board at low cost. An object of the present invention is to provide a method of manufacturing a semiconductor device to be connected.
[0015]
[Means for Solving the Problems]
In order to achieve the above object, one aspect of the present invention is a method for mounting an electronic component on an electronic circuit board, wherein the electronic component includes a first bump electrode group and a plurality of first and second low-melting materials. The electronic circuit board has a second protruding electrode group corresponding to the first protruding electrode group and a second protruding portion made of a low melting point material corresponding to the first protruding portion. The method includes a step of fusion-bonding the first and second projections and a step of solid-phase bonding the first projection electrode group and the second projection electrode group after fusion bonding. An electronic component mounting method characterized by the following.
[0016]
By performing such a mounting method, the first and second protrusions perform alignment in a self-aligning manner, so that a conventional bonding apparatus can be used.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the scope of protection of the present invention is not limited to the following embodiments, but extends to the inventions described in the claims and their equivalents.
[0018]
FIG. 1 is a top view showing a semiconductor chip according to an embodiment of the present invention, and bump electrodes and solder bumps on its mounting surface. FIG. 2 is a diagram illustrating a method of mounting a semiconductor chip on a circuit board. An embodiment of the present invention will be described below with reference to FIGS. The same reference numerals are used for the same parts.
[0019]
In FIG. 1, a projection electrode 3 is formed on a mounting surface of a semiconductor chip 1, and projections made of a low melting point metal or the like are formed at four locations on the outer periphery of the semiconductor chip 1. The protrusion is, for example, a solder bump 2 which is thicker than the electroless-plated protrusion electrode 3. This solder bump is formed by a known method.
[0020]
In FIG. 2A, on the circuit board 4, projecting electrodes 5 of the substrate corresponding to the projecting electrodes 3 of the semiconductor chip 1 and solder bumps 6 of the substrate corresponding to the solder bumps 2 of the semiconductor chip 1 are formed. . The thicknesses of the bump electrodes 5 and the solder bumps 6 formed on the circuit board may be substantially equal. Also, the protruding electrodes of the circuit board 4 can be formed by an electroless plating method or the like. The solder bumps 2 and 6 need not be electrically connected to the semiconductor chip 1 and the circuit board 4.
[0021]
Generally, the material of the protruding electrode formed by electroless plating or the like is preferably a soft metal material or alloy material that is hardly oxidized and has good workability, and although expensive, gold (Au) is the most suitable material. .
[0022]
In addition, a brief description will be given of the solder material used. Binary alloys include tin and silver, tin and copper, tin and bismuth, tin and indium, tin and aluminum, and the like. Examples of the ternary alloy include tin, silver, and copper, and tin, gold, and zinc. Among the above listed materials, the ternary alloy is excellent as a solder material. However, binary alloys of tin and silver which are inexpensive and easy to handle are also frequently used.
[0023]
The semiconductor chip 1 and the circuit board 4 prepared as described above are loaded into a chamber (not shown) having an atmosphere capable of irradiating argon plasma, and the semiconductor chip having the bump electrode 3 formed thereon and the bump electrode 5 of the circuit board 4 are removed. Then, the surface of the protruding electrodes 3 and 5 is irradiated with argon plasma and etched.
[0024]
As a result, contaminants such as oxide films, water and oils and fats of the bump electrodes 3 and 5 are removed, and the bump electrode surfaces are cleaned and activated. As a method for removing oxides on the electrode surface, the oxides can be reduced in a heated carboxylic acid, for example, in formic acid vapor at 250 ° C.
[0025]
Next, in order to maintain the active state of the protruding electrode interface between the semiconductor chip 1 and the circuit board 4, the chamber is purged with an inert gas so as not to be exposed to the atmosphere, and an apparatus for joining the semiconductor chip 1 and the circuit board 4 is provided. And transported into a chamber filled with an inert gas atmosphere containing the same. During transportation, the semiconductor chip 1 and the circuit board 4 are kept in an inert gas atmosphere and are not exposed to the atmosphere. Thus, the activated state of the surface of the protruding electrodes of the semiconductor chip and the circuit board can be maintained when the protruding electrodes of the semiconductor chip and the circuit board are joined.
[0026]
After the semiconductor chip 1 and the circuit board 4 are conveyed into the chamber including the bonding device, the insulating resin film 7 is conveyed from a film loader (not shown) to be on the projecting electrodes 5 of the circuit board 4 as shown in FIG. To place. At this time, care must be taken not to dispose the insulating resin film on the solder bumps 6 on the circuit board.
[0027]
The material of the insulating resin film 7 is not particularly limited, but is preferably a thermosetting material, a thermoplastic material, or a mixture thereof.
[0028]
Then, first alignment of the projecting electrodes 3 and 5 between the semiconductor chip 1 and the circuit board 4 is performed by a known alignment device (not shown). This alignment does not need to use a special high-precision alignment device. For example, an alignment accuracy of about 5 μm is sufficient.
[0029]
After the first alignment is completed, the semiconductor chip 1 is heated by a heater or the like. The heating temperature at this time may be a temperature at which the solder bump melts, and is, for example, about 200 ° C. At this time, the solder bumps 2 formed on the semiconductor chip 1 are melted into a hemispherical shape 2 '.
[0030]
Next, as shown in FIG. 2C, by heating, the solder bumps arranged at the four corners of the outer peripheral portion of the semiconductor chip are melted into a hemispherical shape 2 ′, and come into contact with the solder 6 of the corresponding circuit board. Then, the position of the semiconductor chip slightly moves due to the stress of the molten solders 2 'and 6 trying to be integrated with each other, and the second alignment is performed in a self-aligned manner. When this alignment is performed, the protruding electrodes 3 formed on the semiconductor chip 1 are not in contact with the insulating resin film 7. Therefore, the semiconductor chip 1 is in a state where it can be finely moved.
[0031]
By this alignment, the corresponding protruding electrodes 3 and 5 of the semiconductor chip 1 and the circuit board 4 are accurately aligned. Then, as shown in FIG. 2C, the semiconductor chip 1 is pressurized and heated. The melted solder bumps are integrated while being melted to form a substantially spherical 2 ″. Also, by applying pressure, the protruding electrodes 3 of the semiconductor chip 1 are inserted into the insulating resin film 7.
[0032]
Further, as shown in FIG. 2D, by continuing to apply pressure, the protruding electrode 3 breaks through the insulating resin film, and the protruding electrode 3 of the semiconductor chip comes into contact with the protruding electrode 5 of the circuit board 4. The heating temperature at this time is 150 ° C. or lower or normal temperature. The atmosphere during pressurization is a gas phase containing nitrogen, oxygen, in addition to argon. Further, the pressure in the chamber may be reduced to 1 atom or less.
[0033]
When pressurized in such an atmosphere, the projecting electrodes 3 and 5 of the semiconductor chip 1 and the circuit board 4 break through the insulating resin film 7 while correcting the warpage of the semiconductor chip 1 and the circuit board 4, and the insulating resin film The solder is hardened without entering between the protruding electrodes, and the solder material on the outer peripheral portion of the semiconductor chip collapses while further maintaining the connection. Then, the protruding electrodes of the semiconductor chip 1 and the circuit board 4 are solid-phase bonded to each other with low stress to form a substantially integrated metal plug shape 8. The metal plug 8 is joined so strongly that the joint between the protruding electrodes 3 and 5 cannot be observed.
[0034]
Further, when heating and pressing with an adhesive film interposed between connected parts, ultrasonic vibration may be additionally applied to the connected parts. By applying ultrasonic vibration, the heating temperature can be kept low. Therefore, damage to the connected component due to high-temperature heating can be reduced.
[0035]
Further, in the present embodiment, four solder bumps are provided on the semiconductor chip 1 and the circuit board 4, but three solder bumps may be provided. Further, in flip-chip mounting, electrodes are taken out by using protruding electrodes or the like. However, since the positions of the protruding electrodes and the like vary depending on the semiconductor chip, there are various modifications.
[0036]
FIG. 3 is a diagram illustrating an arrangement example (1) of solder bumps and protruding electrodes. FIG. 4 is a diagram illustrating an arrangement example (2) of the solder bumps and the protruding electrodes. FIG. 3A shows a method of arranging solder bumps in the present embodiment, and FIGS. 3B and 3C both show an example in which solder bumps are formed at four corners on the outer periphery.
[0037]
FIGS. 4D and 4E show examples in which the outer periphery of the semiconductor chip is surrounded by protruding electrodes, and four solder bumps are formed near the center of the semiconductor chip. Further, in FIGS. 4F and 4G, eight solder bumps are formed, and four solder bumps are formed at the four outer peripheral corners of the semiconductor chip 1 and also near the chip center.
[0038]
The examples of forming these solder bumps are not limited to FIGS. 3 and 4, and various modifications are possible depending on the arrangement of the electrodes of the semiconductor chip 1.
[0039]
As described above, the embodiments are summarized as follows.
[0040]
(Supplementary Note 1) A method of mounting an electronic component on an electronic circuit board,
The electronic component has a first protruding electrode group and a plurality of first protruding portions made of a low melting point material, and the electronic circuit board includes a second protruding electrode group corresponding to the first protruding electrode group. A second projection made of a low-melting material corresponding to the first projection;
The method comprises:
Fusion bonding the first and second projections;
A step of solid-phase bonding the first protruding electrode group and the second protruding electrode group after the fusion bonding.
[0041]
(Supplementary Note 2) In Supplementary Note 1,
Further, before the step of fusion-bonding, after the step of coating an insulating film on the second bump electrode group and after the step of fusion-bonding, the electronic component is pressurized to the first bump electrode group. Mounting the first projecting electrode and the second projecting electrode group in a solid phase by penetrating the insulating film.
[0042]
(Supplementary Note 3) In Supplementary note 1,
The low melting point material is selected from tin and silver, tin and copper, tin and bismuth, tin and indium, tin and aluminum binary alloys, tin and silver and copper, tin and gold and zinc ternary alloys An electronic component mounting method characterized by being one material.
[0043]
(Supplementary Note 4) In Supplementary Note 1 or 2,
The method for mounting an electronic component further includes a step of exposing the first and second protruding electrode groups to a plasma atmosphere and cleaning the first and second protruding electrodes before the step of fusion bonding.
[0044]
(Supplementary Note 5) In Supplementary Note 1,
The method for mounting an electronic component, further comprising a step of positioning the electronic component and the electronic circuit board by a positioning device before the step of fusion bonding.
[0045]
(Supplementary Note 6) In Supplementary Note 1,
The method of mounting an electronic component, wherein the plurality of first protrusions are larger than the protrusion electrodes of the first protrusion electrode group.
[0046]
(Supplementary Note 7) In Supplementary Note 1,
The method of mounting an electronic component, wherein the step of fusion-bonding is performed at a first temperature, and the step of solid-phase bonding is performed at a second temperature lower than the first temperature.
[0047]
(Supplementary Note 8) In supplementary note 1,
The method of mounting an electronic component, wherein the step of melting and bonding is performed in an inert gas atmosphere.
[0048]
(Supplementary Note 9) In Supplementary Note 1,
A method for mounting an electronic component, wherein the material of the first and second protruding electrode groups is gold.
[0049]
【The invention's effect】
As described above, according to the present invention, the reliability of the joint between the electrode of the electronic component and the electrode of the electronic circuit board is increased, the insulation reliability between adjacent electrodes is ensured, and the electronic component is mounted on the electronic circuit board at low cost. Can be implemented.
[Brief description of the drawings]
FIG. 1 is a top view showing a semiconductor chip according to an embodiment of the present invention, and bump electrodes and solder bumps on its mounting surface.
FIG. 2 is a diagram illustrating a method of mounting a semiconductor chip on a circuit board.
FIG. 3 is a diagram showing an arrangement example (1) of solder bumps and protruding electrodes.
FIG. 4 is a diagram showing an arrangement example (2) of solder bumps and protruding electrodes.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 semiconductor chip 2 solder bump formed on semiconductor chip 3 bump electrode 4 formed on semiconductor chip 4 circuit board 5 bump electrode formed on circuit board 6 solder bump formed on circuit board 7 insulating resin film 8 solid phase bonding Protruding electrode

Claims (4)

電子回路基板上に電子部品を実装する方法であって、
前記電子部品は第１の突起電極群と低融点材料からなる複数の第１の突起部とを有し、前記電子回路基板は該第１の突起電極群に対応する第２の突起電極群と該第１の突起部に対応し低融点材料からなる第２の突起部とを有し、
前記方法は、
前記第１及び第２の突起部を溶融結合する工程と、
前記溶融接合の後、前記第１の突起電極群と第２の突起電極群とを固相接合する工程と
を含むことを特徴とする電子部品の実装方法。A method of mounting an electronic component on an electronic circuit board,
The electronic component has a first protruding electrode group and a plurality of first protruding portions made of a low melting point material, and the electronic circuit board includes a second protruding electrode group corresponding to the first protruding electrode group. A second projection made of a low-melting material corresponding to the first projection;
The method comprises:
Fusion bonding the first and second projections;
A step of solid-phase bonding the first protruding electrode group and the second protruding electrode group after the fusion bonding. 請求項１において、
更に、前記溶融結合する工程の前に、前記第２の突起電極群上に絶縁性フィルムを被覆する工程と
前記溶融結合する工程後に、前記電子部品を加圧して前記第１の突起電極群に前記絶縁性フィルムを貫通させ該第１の突起電極と第２の突起電極群とを固相接合させる工程と
を含むことを特徴とする電子部品の実装方法。In claim 1,
Further, before the step of fusion-bonding, after the step of coating an insulating film on the second bump electrode group and after the step of fusion-bonding, the electronic component is pressurized to the first bump electrode group. Mounting the first projecting electrode and the second projecting electrode group in a solid phase by penetrating the insulating film. 請求項１において、
前記低融点材料が、錫と銀、錫と銅、錫とビスマス、錫とインジウム、錫とアルミの２元合金か、錫と銀と銅、錫と金と亜鉛の３元合金から選択された１つの材料であることを特徴とする電子部品の実装方法。In claim 1,
The low melting point material is selected from tin and silver, tin and copper, tin and bismuth, tin and indium, tin and aluminum binary alloys, tin and silver and copper, tin and gold and zinc ternary alloys An electronic component mounting method characterized by being one material. 請求項１又は２において、
更に、溶融結合する工程前に、第１及び第２の突起電極群をプラズマ雰囲気中に晒し、第１及び第２の突起電極をクリーニングする工程を含むことを特徴とする電子部品の実装方法。In claim 1 or 2,
The method for mounting an electronic component further includes a step of exposing the first and second protruding electrode groups to a plasma atmosphere and cleaning the first and second protruding electrodes before the step of fusion bonding.
JP2003042117A 2003-02-20 2003-02-20 Method for packaging electronic component Withdrawn JP2004253598A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017028156A (en) * 2015-07-24 2017-02-02 新光電気工業株式会社 Mounting structure and manufacturing method therefor
JP2018010962A (en) * 2016-07-13 2018-01-18 キヤノン株式会社 Image pick-up device and mounting board thereof
EP3828922A1 (en) * 2019-11-26 2021-06-02 IMEC vzw A method for bonding semiconductor components
US20220216176A1 (en) * 2021-01-04 2022-07-07 Yibu Semiconductor Co., Ltd. Semiconductor Assembly Packaging Method, Semiconductor Assembly and Electronic Device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017028156A (en) * 2015-07-24 2017-02-02 新光電気工業株式会社 Mounting structure and manufacturing method therefor
JP2018010962A (en) * 2016-07-13 2018-01-18 キヤノン株式会社 Image pick-up device and mounting board thereof
EP3828922A1 (en) * 2019-11-26 2021-06-02 IMEC vzw A method for bonding semiconductor components
US11810892B2 (en) 2019-11-26 2023-11-07 Imec Vzw Method of direct bonding semiconductor components
US20220216176A1 (en) * 2021-01-04 2022-07-07 Yibu Semiconductor Co., Ltd. Semiconductor Assembly Packaging Method, Semiconductor Assembly and Electronic Device

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