TW201901825A - Method for manufacturing semiconductor device, and semiconductor device - Google Patents
Method for manufacturing semiconductor device, and semiconductor device Download PDFInfo
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- TW201901825A TW201901825A TW107109278A TW107109278A TW201901825A TW 201901825 A TW201901825 A TW 201901825A TW 107109278 A TW107109278 A TW 107109278A TW 107109278 A TW107109278 A TW 107109278A TW 201901825 A TW201901825 A TW 201901825A
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- Prior art keywords
- solder layer
- connection terminal
- semiconductor device
- solder
- layer
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 119
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title abstract description 16
- 229910000679 solder Inorganic materials 0.000 claims abstract description 187
- 229920005989 resin Polymers 0.000 claims abstract description 37
- 239000011347 resin Substances 0.000 claims abstract description 37
- 229920001187 thermosetting polymer Polymers 0.000 claims abstract description 16
- 238000002844 melting Methods 0.000 claims abstract description 15
- 230000008018 melting Effects 0.000 claims abstract description 15
- 238000007789 sealing Methods 0.000 claims abstract description 6
- 238000010438 heat treatment Methods 0.000 claims abstract description 3
- 239000000758 substrate Substances 0.000 claims description 41
- 239000010949 copper Substances 0.000 claims description 21
- 229910052802 copper Inorganic materials 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 8
- 238000007747 plating Methods 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims 1
- 239000004332 silver Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 177
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 238000003892 spreading Methods 0.000 description 4
- 230000007480 spreading Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000005304 joining Methods 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910020836 Sn-Ag Inorganic materials 0.000 description 2
- 229910020988 Sn—Ag Inorganic materials 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 230000037361 pathway Effects 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910017944 Ag—Cu Inorganic materials 0.000 description 1
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
本發明係關於一種半導體裝置之製造方法及半導體裝置。 The present invention relates to a method of fabricating a semiconductor device and a semiconductor device.
作為覆晶構裝方式，已知有將柱狀電極形成於半導體晶片，再藉由焊料將柱狀電極與電路基板之連接端子接合的方式。柱狀電極由於會以吸收半導體晶片與電路基板之熱膨脹係數差的方式變形，故相較於將半導體晶片之連接電極與電路基板之連接端子直接以焊料接合的構造，可抑制焊料之裂紋，且可使接合部之間距小。然而，於前者之構造，介於柱狀電極與連接端子之間的焊料，因會擴展於連接端子及連接於該連接端子之配線，故為了確保足夠之接合力，而需要擴展於周圍之份量亦被估算在內的焊料量。以往為了確保所需之接合力，而無法減少焊料量，故於使接合部之間距小的方面上有界限。 As a flip chip mounting method, a method in which a columnar electrode is formed on a semiconductor wafer and a columnar electrode and a connection terminal of the circuit board are joined by solder is known. Since the columnar electrode is deformed so as to absorb the difference in thermal expansion coefficient between the semiconductor wafer and the circuit board, the solder can be prevented from being cracked by the structure in which the connection terminals of the connection electrode of the semiconductor wafer and the circuit board are directly joined by solder. The distance between the joints can be made small. However, in the former structure, the solder interposed between the columnar electrode and the connection terminal is extended to the connection terminal and the wiring connected to the connection terminal, so in order to secure a sufficient bonding force, it is necessary to expand the amount of the surrounding portion. The amount of solder that is also estimated. Conventionally, in order to secure the required bonding force, the amount of solder cannot be reduced, so that there is a limit in terms of the small distance between the joint portions.
又，其他亦已知有下述方法：預先於電路基板之連接端子形成焊料，預先將球狀突起電極高頻接合於半導體晶片之連接焊墊，藉由熱壓接將突起電極與連接端子焊接(參照專利文獻1)。 Further, there is also known a method in which solder is formed in advance at a connection terminal of a circuit board, and a ball-shaped bump electrode is bonded to a connection pad of a semiconductor wafer in advance, and the bump electrode and the connection terminal are soldered by thermocompression bonding. (Refer to Patent Document 1).
[先前技術文獻] [Previous Technical Literature]
[專利文獻] [Patent Literature]
專利文獻1：日本專利特開平11一111755號公報 Patent Document 1: Japanese Patent Laid-Open No. 11-111755
於專利文獻1記載之方法，由於突起電極為球狀，故無法縮小接合部之間距。又，亦無法抑制介於突起電極與連接端子之間的焊料擴展於連接端子及連接於該連接端子之配線。因此，即使藉由專利文獻1記載之方法，亦無法縮小接合部之間距。 According to the method described in Patent Document 1, since the protruding electrodes are spherical, the distance between the joint portions cannot be reduced. Further, it is also impossible to suppress solder extending between the bump electrode and the connection terminal from extending to the connection terminal and the wiring connected to the connection terminal. Therefore, even with the method described in Patent Document 1, the distance between the joint portions cannot be reduced.
若根據本發明之第1態樣，則半導體裝置之製造方法具備：將形成於半導體元件柱狀電極之端面的焊料層配置在形成於電路基板之一面的連接端子上，施加超音波將前述焊料層與前述連接端子接合，藉由熱硬化性樹脂將前述半導體元件密封，使前述熱硬化性樹脂硬化，使前述熱硬化性樹脂硬化後，將前述焊料層加熱至較前述焊料層熔點高的溫度，將前述焊料層與前述連接端子接合。 According to a first aspect of the present invention, in a method of manufacturing a semiconductor device, a solder layer formed on an end surface of a columnar electrode of a semiconductor element is disposed on a connection terminal formed on one surface of a circuit board, and ultrasonic waves are applied to apply the solder. The layer is bonded to the connection terminal, and the semiconductor element is sealed by a thermosetting resin to cure the thermosetting resin, and after the thermosetting resin is cured, the solder layer is heated to a temperature higher than a melting point of the solder layer. And bonding the solder layer to the connection terminal.
若根據本發明之第2態樣，則較佳於第1態樣之半導體裝置之製造方法中，前述焊料層具有與前述連接端子之界面的寬度較與前述柱狀電極之界面的寬度小的形狀。 According to a second aspect of the present invention, in the method of fabricating the semiconductor device of the first aspect, the solder layer has a width of an interface with the connection terminal that is smaller than a width of an interface of the columnar electrode. shape.
若根據本發明之第3態樣，則較佳於第1態樣之半導體裝置之製造方法中，前述焊料層之寬度較前述連接端子之寬度小。 According to a third aspect of the present invention, in the method of fabricating the semiconductor device of the first aspect, the width of the solder layer is smaller than a width of the connection terminal.
若根據本發明之第4態樣，則較佳於第1態樣之半導體裝置之製造方法中，前述焊料層與前述連接端子之接合以較前述焊料層之熔點低的溫度進行。 According to a fourth aspect of the present invention, in the method of fabricating the semiconductor device of the first aspect, the bonding between the solder layer and the connection terminal is performed at a temperature lower than a melting point of the solder layer.
若根據本發明之第5態樣，則較佳於第1態樣之半導體裝置之製造方法中，藉由鍍覆形成前述柱狀電極及前述焊料層。 According to the fifth aspect of the present invention, in the method of fabricating the semiconductor device of the first aspect, the columnar electrode and the solder layer are formed by plating.
若根據本發明之第6態樣，則較佳於第1至第5中任一態樣之半導體裝置之製造方法中，前述電路基板於與前述一面對向之另一面具有連接於前述連接端子之焊球裝載部， 具有：於將前述焊料層配置於前述連接端子上前，透過剝離層以支持基板支持前述電路基板，並具有：施加超音波將前述焊料層與前述連接端子接合後，將前述支持基板剝離，及將焊球裝載於前述電路基板之前述另一面的前述焊球裝載部；當加熱至較前述焊料層之熔點高的溫度將前述焊料層與前述連接端子接合時，將前述焊球接合於前述焊球裝載部。 According to a sixth aspect of the present invention, in the method of manufacturing the semiconductor device of any of the first to fifth aspect, the circuit substrate has a connection to the other side of the facing surface. The solder ball loading portion of the terminal has a support layer supporting the circuit board through the peeling layer before the solder layer is disposed on the connection terminal, and having the ultrasonic layer applied to bond the solder layer to the connection terminal Stripping the support substrate and mounting the solder ball on the solder ball mounting portion on the other surface of the circuit board; and when soldering the solder layer to the connection terminal at a temperature higher than a melting point of the solder layer, The solder ball is bonded to the solder ball loading portion.
若根據本發明之第7態樣，則較佳於第6態樣之半導體裝置之製造方法中，將前述焊料層與前述連接端子接合及將前述焊球接合於前述焊球裝載部皆藉由回焊(reflow)進行。 According to a seventh aspect of the present invention, in a method of manufacturing a semiconductor device according to the sixth aspect, the solder layer is bonded to the connection terminal and the solder ball is bonded to the solder ball loading portion. Reflow is performed.
若根據本發明之第8態樣，則較佳於第6態樣之半導體裝置之製造方法中，具有：將前述支持基板剝離前，將密封前述半導體元件之前述熱硬化性樹脂除去，使前述剝離層露出。 According to an eighth aspect of the present invention, in a method of manufacturing a semiconductor device according to the sixth aspect, the method further comprises: removing the thermosetting resin that seals the semiconductor element before the supporting substrate is peeled off, The peeling layer is exposed.
若根據本發明之第9態樣，則半導體裝置具備：具有於端面形成有焊料層之柱狀電極的半導體元件、具有連接端子之電路基板及將前述半導體元件密封之經硬化的密封樹脂，前述焊料層之寬度較前述連接端子之寬度小，前述焊料層之外圍被前述經硬化之樹脂圍繞。 According to a ninth aspect of the present invention, a semiconductor device includes: a semiconductor element having a columnar electrode having a solder layer formed on an end surface; a circuit board having a connection terminal; and a cured sealing resin sealing the semiconductor element, The width of the solder layer is smaller than the width of the aforementioned connection terminal, and the periphery of the solder layer is surrounded by the hardened resin.
若根據本發明之第10態樣，則較佳於第9態樣之半導體裝置中，前述焊料層具有與前述連接端子之界面的寬度較與前述柱狀電極之界面的寬度小的形狀。 According to a tenth aspect of the invention, in the semiconductor device of the ninth aspect, the solder layer has a shape in which a width of an interface with the connection terminal is smaller than a width of an interface of the columnar electrode.
若根據本發明之第11態樣，則較佳於第9態樣之半導體裝置中，前述電路 基板具有連接於前述連接端子之焊球。 According to an eleventh aspect of the present invention, in the semiconductor device of the ninth aspect, the circuit board has a solder ball connected to the connection terminal.
若根據本發明之第12態樣，則較佳於第11態樣之半導體裝置中，前述半導體元件具有沿著相對向之一對側邊的各個側邊排列之複數個前述柱狀電極，前述電路基板之前述焊球具有連接於各個前述柱狀電極之前述焊球，前述焊球較前述柱狀電極配置於更外側。 According to a twelfth aspect of the present invention, in the semiconductor device of the eleventh aspect, the semiconductor device includes a plurality of the columnar electrodes arranged along the respective sides of the pair of sides, the foregoing The solder ball of the circuit board has the solder ball connected to each of the columnar electrodes, and the solder ball is disposed outside the columnar electrode.
若根據本發明之第13態樣，則較佳於第9至第12中任一態樣之半導體裝置中，前述柱狀電極及前述連接端子由銅系金屬形成，前述焊料層由含有銅及銀之金屬形成。 According to a thirteenth aspect of the present invention, in the semiconductor device of any of the ninth to twelfth aspect, the columnar electrode and the connection terminal are formed of a copper-based metal, and the solder layer contains copper and The formation of silver metal.
若根據本發明之第14態樣，則較佳於第13態樣之半導體裝置中，障壁層介於前述柱狀電極與前述焊料層之間。 According to a fourteenth aspect of the present invention, in the semiconductor device of the thirteenth aspect, the barrier layer is interposed between the columnar electrode and the solder layer.
若根據本發明之第15態樣，則較佳於第13態樣之半導體裝置中，前述柱狀電極直接形成於連接在前述半導體元件之內部電路的焊墊上。 According to a fifteenth aspect of the invention, in the semiconductor device of the thirteenth aspect, the columnar electrode is directly formed on a pad connected to an internal circuit of the semiconductor element.
若根據本發明，則可使接合部之間距小。 According to the present invention, the distance between the joint portions can be made small.
1‧‧‧半導體裝置 1‧‧‧Semiconductor device
1A‧‧‧本體 1A‧‧‧ Ontology
2‧‧‧半導體元件 2‧‧‧Semiconductor components
3‧‧‧電路基板 3‧‧‧ circuit board
4‧‧‧樹脂(密封樹脂) 4‧‧‧Resin (sealing resin)
11‧‧‧焊球 11‧‧‧ solder balls
21‧‧‧半導體晶片 21‧‧‧Semiconductor wafer
22‧‧‧柱狀電極 22‧‧‧column electrode
23‧‧‧焊料層 23‧‧‧ solder layer
24‧‧‧鈍化膜 24‧‧‧passivation film
25‧‧‧保護膜 25‧‧‧Protective film
26‧‧‧電極焊墊 26‧‧‧Electrode pads
28‧‧‧障壁層 28‧‧ ‧ barrier layer
31‧‧‧絕緣層 31‧‧‧Insulation
32‧‧‧配線 32‧‧‧Wiring
32a、32b‧‧‧通路 32a, 32b‧‧‧ pathway
33、36‧‧‧連接端子 33, 36‧‧‧ Connection terminals
34‧‧‧外部端子部(焊球裝載部) 34‧‧‧External terminal part (solder ball loading part)
35a‧‧‧配線部 35a‧‧‧Wiring Department
35‧‧‧配線 35‧‧‧Wiring
36‧‧‧連接端子 36‧‧‧Connecting terminal
36a‧‧‧通路 36a‧‧‧ pathway
37‧‧‧配線 37‧‧‧Wiring
37a‧‧‧最下層 37a‧‧‧The lowest level
51‧‧‧絕緣基板 51‧‧‧Insert substrate
52‧‧‧支持基板 52‧‧‧Support substrate
52a‧‧‧剝離層 52a‧‧‧ peeling layer
52b、53、54‧‧‧晶種層 52b, 53, 54‧ ‧ seed layer
61、62、63‧‧‧乾膜阻劑 61, 62, 63‧‧‧ dry film resist
61a、62a、63a‧‧‧開口 61a, 62a, 63a‧‧
64‧‧‧阻焊劑 64‧‧‧ solder resist
71‧‧‧第1凸墊(外部端子部) 71‧‧‧1st convex pad (external terminal part)
72‧‧‧第2凸墊 72‧‧‧2nd convex pad
73‧‧‧第3凸墊(連接端子) 73‧‧‧3rd convex pad (connection terminal)
81‧‧‧第1增層 81‧‧‧1st build-up
81a、82a‧‧‧開口 81a, 82a‧‧‧ openings
82‧‧‧第2增層 82‧‧‧2nd layer
VII、VIII‧‧‧接合區域 VII, VIII‧‧‧ joint area
圖1為表示本發明之半導體裝置的第1實施形態，於厚度方向上切開之側面剖面圖。 Fig. 1 is a side cross-sectional view showing a first embodiment of a semiconductor device according to the present invention, which is cut in the thickness direction.
圖2(a)~(e)為用以說明圖1所圖示之半導體裝置之製造步驟的剖面圖。 2(a) to 2(e) are cross-sectional views for explaining the manufacturing steps of the semiconductor device illustrated in Fig. 1.
圖3(a)~(e)為用以說明接續圖2之半導體裝置之製造步驟的剖面圖。 3(a) to 3(e) are cross-sectional views for explaining the manufacturing steps of the semiconductor device continued from Fig. 2.
圖4(a)~(d)為用以說明接續圖3之半導體裝置之製造步驟的剖面圖。 4(a) to 4(d) are cross-sectional views for explaining the manufacturing steps of the semiconductor device continued from Fig. 3.
圖5(a)~(c)為用以說明接續圖4之半導體裝置之製造步驟的剖面圖。 5(a) to 5(c) are cross-sectional views for explaining the manufacturing steps of the semiconductor device continued from Fig. 4.
圖6(a)~(c)為用以說明接續圖5之半導體裝置之製造步驟的剖面圖。 6(a) to 6(c) are cross-sectional views for explaining the manufacturing steps of the semiconductor device continued from Fig. 5.
圖7為圖5(a)所圖示之接合區域VII的放大剖面圖，係將SEM(掃描式電子顯微鏡，Scanning Electron Microscope)拍攝之照片加以描跡(trace)的示意圖。 Fig. 7 is an enlarged cross-sectional view showing the joint region VII shown in Fig. 5(a), which is a schematic view showing a photograph taken by SEM (Scanning Electron Microscope).
圖8為圖5(b)所圖示之接合區域VIII的放大剖面圖，係將SEM(掃描式電子顯微鏡，Scanning Electron Microscope)拍攝之照片加以描跡的示意圖。 Fig. 8 is an enlarged cross-sectional view showing the joint region VIII shown in Fig. 5(b), which is a schematic view showing a photograph taken by SEM (Scanning Electron Microscope).
圖9為表示本發明之半導體裝置第2實施形態之接合部的放大剖面圖。 Fig. 9 is an enlarged cross-sectional view showing a joint portion of a second embodiment of the semiconductor device of the present invention.
圖10為表示本發明之半導體裝置第3實施形態的剖面圖。 Fig. 10 is a cross-sectional view showing a third embodiment of the semiconductor device of the present invention.
圖11為表示本發明之半導體裝置第4實施形態的剖面圖。 Figure 11 is a cross-sectional view showing a fourth embodiment of the semiconductor device of the present invention.
-第1實施形態- - First embodiment -
以下，參照圖1~圖8，說明本發明之半導體裝置及半導體裝置之製造方法的第1實施形態。 Hereinafter, a first embodiment of a semiconductor device and a method of manufacturing a semiconductor device according to the present invention will be described with reference to Figs. 1 to 8 .
圖1為表示本發明之半導體裝置的第1實施形態，於厚度方向上切開之側面剖面圖。 Fig. 1 is a side cross-sectional view showing a first embodiment of a semiconductor device according to the present invention, which is cut in the thickness direction.
半導體裝置1具有半導體元件2、電路基板3、樹脂4及焊球11。 The semiconductor device 1 includes a semiconductor element 2, a circuit board 3, a resin 4, and a solder ball 11.
半導體元件2具有半導體晶片21、柱狀電極22及焊料層23。電路基板3具有絕緣層31與配線32。配線32具有「形成於絕緣層31上面上之連接端子33」與「從絕緣層31下面露出於外部的外部端子部34」。 The semiconductor element 2 has a semiconductor wafer 21, a columnar electrode 22, and a solder layer 23. The circuit board 3 has an insulating layer 31 and wirings 32. The wiring 32 has "a connection terminal 33 formed on the upper surface of the insulating layer 31" and "an external terminal portion 34 exposed from the lower surface of the insulating layer 31".
半導體晶片21為將半導體基板即晶圓切割而得到之裸半導體晶片，具有形成於主面上之鈍化膜24、形成於鈍化膜24上之由聚醯亞胺等構成的保護膜25以及從設置於各鈍化膜24與保護膜25之開口露出的電極焊墊26。電極焊墊26連接於半導體晶片21之內部積體電路。雖未圖示出平面圖，但鈍化膜24 及保護膜25之開口沿著半導體晶片21相對向之一對側邊或4個側邊各排列有複數個，因此，電極焊墊26亦沿著一對側邊或4個側邊各排列有複數個。 The semiconductor wafer 21 is a bare semiconductor wafer obtained by cutting a semiconductor substrate, that is, a wafer, and has a passivation film 24 formed on the main surface, a protective film 25 made of polyimide or the like formed on the passivation film 24, and a slave device. The electrode pads 26 exposed at the openings of the passivation film 24 and the protective film 25 are provided. The electrode pad 26 is connected to an internal integrated circuit of the semiconductor wafer 21. Although the plan view is not illustrated, the openings of the passivation film 24 and the protective film 25 are arranged along the opposite side or the four sides of the semiconductor wafer 21, and therefore, the electrode pads 26 are also arranged along the same. There are a plurality of sides or four sides arranged.
柱狀電極22形成於各電極焊墊26上，具有高度10μm~30μm之圓筒形狀。柱狀電極例如由銅系金屬形成。 The columnar electrode 22 is formed on each of the electrode pads 26 and has a cylindrical shape having a height of 10 μm to 30 μm. The columnar electrode is formed of, for example, a copper-based metal.
於柱狀電極22之軸方向端面形成有焊料層23。焊料層23例如由Sn-Ag二元系或Sn-Ag-Cu三元系形成。半導體元件2係於晶圓狀態下，藉由鍍覆將柱狀電極22及焊料層23形成於各電極焊墊26上後，再藉由切割分離成一個個而得。 A solder layer 23 is formed on the end surface of the columnar electrode 22 in the axial direction. The solder layer 23 is formed, for example, of a Sn-Ag binary system or a Sn-Ag-Cu ternary system. The semiconductor element 2 is formed in a wafer state, and the columnar electrode 22 and the solder layer 23 are formed on the electrode pads 26 by plating, and then separated by dicing.
樹脂4係由熱硬化性樹脂形成，密封著接合於電路基板3之半導體元件2。樹脂4之外圍側面與電路基板3大致同形狀，形成為大致同尺寸。 The resin 4 is formed of a thermosetting resin, and the semiconductor element 2 bonded to the circuit board 3 is sealed. The peripheral side surface of the resin 4 is substantially the same shape as the circuit board 3, and is formed to have substantially the same size.
各焊料層23接合於連接端子33。又，於外部端子部34接合有焊球11。配線32之外部端子部34側被導引至較柱狀電極22外圍側，各外部端子部34以較柱狀電極22之間距大的間距排列於柱狀電極22之外圍側。亦即，焊球11較柱狀電極22配置於更外側，第1實施形態之半導體裝置1係以扇出封裝(Fan-out Package)之形態例示。另，電路基板3之半導體元件2側相反之面，亦即於圖1中在下面形成有阻焊劑64，焊球11在配置於形成在阻焊劑64之開口內的狀態下接合於外部端子部34。 Each solder layer 23 is bonded to the connection terminal 33. Further, the solder balls 11 are joined to the external terminal portion 34. The external terminal portion 34 side of the wiring 32 is guided to the outer peripheral side of the columnar electrode 22, and each of the external terminal portions 34 is arranged on the outer peripheral side of the columnar electrode 22 at a large pitch from the columnar electrode 22. In other words, the solder ball 11 is disposed outside the columnar electrode 22, and the semiconductor device 1 of the first embodiment is exemplified by a fan-out package. Further, a solder resist 64 is formed on the opposite side of the semiconductor element 2 side of the circuit board 3, that is, in the lower surface of FIG. 1, and the solder ball 11 is bonded to the external terminal portion while being disposed in the opening formed in the solder resist 64. 34.
詳細情形雖會於後文敘述，但半導體元件2之焊料層23與電路基板3之連接端子33係以較焊料層23之熔點低的溫度受到超音波接合。焊料層23之寬度形成為較連接端子33之寬度小。又，焊料層23形成為與連接端子33之接合面即界面的寬度較與柱狀電極22之接合面即界面的寬度小。此處，所謂焊料層23之寬度，係指與焊料層23之間距方向正交之方向的長度，所謂柱狀電極22之寬度，係指與柱狀電極22之間距方向正交之方向的長度。又，雖未圖示，但焊料層23形成為與連接端子33之接合面即界面的間距方向之長度較與柱狀電極22之接合面即界面的間距方向之長度小。 Although the details will be described later, the solder layer 23 of the semiconductor element 2 and the connection terminal 33 of the circuit board 3 are ultrasonically bonded at a temperature lower than the melting point of the solder layer 23. The width of the solder layer 23 is formed to be smaller than the width of the connection terminal 33. Further, the solder layer 23 is formed such that the width of the interface which is the bonding surface with the connection terminal 33 is smaller than the width of the interface which is the bonding surface with the columnar electrode 22. Here, the width of the solder layer 23 is the length in the direction orthogonal to the direction from the solder layer 23, and the width of the columnar electrode 22 means the length in the direction orthogonal to the direction between the columnar electrodes 22. . Further, although not shown, the solder layer 23 is formed such that the length in the pitch direction of the interface which is the bonding surface with the connection terminal 33 is smaller than the length in the pitch direction of the interface which is the bonding surface of the columnar electrode 22.
焊料層23係於被超音波接合在連接端子33後，被樹脂4密封。使樹脂4硬化後，裝載焊球11，藉由回焊將外部端子部34與焊球11接合。此時，焊料層23被加熱至熔點以上，焊料層23與連接端子33受到正式接合。 The solder layer 23 is bonded to the connection terminal 33 by ultrasonic waves, and is sealed by the resin 4. After the resin 4 is cured, the solder ball 11 is loaded, and the external terminal portion 34 is bonded to the solder ball 11 by reflow. At this time, the solder layer 23 is heated to a temperature higher than the melting point, and the solder layer 23 and the connection terminal 33 are formally joined.
於此第1實施形態，焊料層23與連接端子33由於以較焊料層23之熔點低的溫度受到超音波接合，故可抑制焊料層23擴展於連接端子33之接合面。又，焊料層23由於是在被經硬化之樹脂4覆蓋其周圍的狀態下受到正式接合，故於正式接合時，亦可抑制擴展於連接端子33之接合面。因此，即使減少焊料層23之量，亦能夠確保必要之接合力，可使柱狀電極22與連接端子33之接合部的間距小。並且，由於可於將外部端子部34與焊球11接合之回焊時同時進行焊料層23與連接端子33之正式接合，因此，可提升生產性。 In the first embodiment, since the solder layer 23 and the connection terminal 33 are ultrasonically bonded at a temperature lower than the melting point of the solder layer 23, it is possible to suppress the solder layer 23 from spreading over the joint surface of the connection terminal 33. Moreover, since the solder layer 23 is integrally joined in a state in which the solder layer 23 is covered by the cured resin 4, it is possible to suppress the joint surface which spreads over the connection terminal 33 at the time of the main joining. Therefore, even if the amount of the solder layer 23 is reduced, the necessary bonding force can be secured, and the pitch of the joint portion between the columnar electrode 22 and the connection terminal 33 can be made small. Further, since the solder layer 23 and the connection terminal 33 can be simultaneously joined at the time of reflow joining the external terminal portion 34 and the solder ball 11, the productivity can be improved.
接著，說明製造本實施形態之半導體裝置的方法。 Next, a method of manufacturing the semiconductor device of the present embodiment will be described.
圖2(a)~(e)為用以說明圖1所圖示之半導體裝置之製造步驟的剖面圖，圖3(a)~(e)為用以說明接續圖2之半導體裝置之製造步驟的剖面圖，圖4(a)~(d)為用以說明接續圖3之半導體裝置之製造步驟的剖面圖，圖5(a)~(c)為用以說明接續圖4之半導體裝置之製造步驟的剖面圖，圖6(a)~(c)為用以說明接續圖5之半導體裝置之製造步驟的剖面圖。 2(a) to 2(e) are cross-sectional views for explaining the manufacturing steps of the semiconductor device illustrated in Fig. 1, and Figs. 3(a) to (e) are diagrams for explaining the manufacturing steps of the semiconductor device continued from Fig. 2. 4(a) to (d) are cross-sectional views for explaining the manufacturing steps of the semiconductor device continued from FIG. 3, and FIGS. 5(a) to (c) are diagrams for explaining the semiconductor device continued from FIG. FIG. 6(a) to FIG. 6(c) are cross-sectional views for explaining the manufacturing steps of the semiconductor device continued from FIG. 5.
以下，參照圖式，說明本發明之製造方法。 Hereinafter, the manufacturing method of the present invention will be described with reference to the drawings.
關於圖2(a) About Figure 2(a)
準備於玻璃板等絕緣基板51上形成有矽(Si)膜等剝離層52a及晶種層(seed layer)52b之四邊形支持基板52。作為晶種層52b，例如將鈦(Ti)形成作為密合層，並於其上形成銅(Cu)。Ti及Cu例如藉由濺鍍形成。然後，將乾膜阻劑(dry film resist)61層疊於晶種層52b上。 A rectangular support substrate 52 having a peeling layer 52a such as a bismuth (Si) film and a seed layer 52b is formed on the insulating substrate 51 such as a glass plate. As the seed layer 52b, for example, titanium (Ti) is formed as an adhesion layer, and copper (Cu) is formed thereon. Ti and Cu are formed, for example, by sputtering. Then, a dry film resist 61 is laminated on the seed layer 52b.
關於圖2(b) About Figure 2(b)
使用光蝕刻(photolithography)技術，於乾膜阻劑61形成露出晶種層52b之 複數個開口61a。各開口61a設置於待形成外部端子部34之區域內。 A plurality of openings 61a exposing the seed layer 52b are formed in the dry film resist 61 using a photolithography technique. Each of the openings 61a is provided in a region where the external terminal portion 34 is to be formed.
另，於以下之說明中，雖然以於支持基板52上配置2個半導體元件2之情形加以例示，但配置於支持基板52上之半導體元件2的數目並無限制，可為1個或3個以上的任意數目。 In the following description, the case where two semiconductor elements 2 are arranged on the support substrate 52 is exemplified, but the number of the semiconductor elements 2 disposed on the support substrate 52 is not limited, and may be one or three. Any number above.
關於圖2(c) About Figure 2(c)
藉由電鍍，於乾膜阻劑61之各開口61a內形成第1凸墊71。第1凸墊71相當於圖1所圖示之外部端子部34。第1凸墊71係藉由銅(Cu)形成，例如形成為直徑50~500μm，高度5~20μm之圓筒狀。惟，第1凸墊71亦可為多邊形。 The first bump 71 is formed in each opening 61a of the dry film resist 61 by electroplating. The first bump 71 corresponds to the external terminal portion 34 illustrated in Fig. 1 . The first bump 71 is formed of copper (Cu), and is formed, for example, in a cylindrical shape having a diameter of 50 to 500 μm and a height of 5 to 20 μm. However, the first convex pad 71 may also be a polygonal shape.
關於圖2(d) About Figure 2(d)
將乾膜阻劑61剝離，露出晶種層52b及第1凸墊71。 The dry film resist 61 is peeled off to expose the seed layer 52b and the first bump 71.
關於圖2(e) About Figure 2(e)
將第1增層(buildup layer)(層間絕緣層)81層疊於晶種層52b及第1凸墊71上。作為第1增層81，較佳為膜式(film type)。第1增層81於真空中層疊後，進行正式硬化。第1增層81形成為其外圍被配置於支持基板52之外圍的內側。 A first buildup layer (interlayer insulating layer) 81 is laminated on the seed layer 52b and the first bump 71. As the first buildup layer 81, a film type is preferable. After the first build-up layer 81 is laminated in a vacuum, it is subjected to main hardening. The first build-up layer 81 is formed such that its outer periphery is disposed on the inner side of the periphery of the support substrate 52.
關於圖3(a) About Figure 3(a)
於第1增層81形成用以露出各第1凸墊71之開口81a。開口81a例如藉由雷射加工進行。形成開口81a後，進行去膠渣處理(desmear treatment)，將各開口81a內之第1凸墊71表面殘留的殘漬除去。然後，於第1增層81及各第1凸墊71上形成晶種層53。作為晶種層53，例如，藉由無電電鍍形成鈀(Pd)/銅(Cu)積層膜。晶種層53亦可藉由濺鍍法形成Ti/Cu積層膜。 An opening 81a for exposing each of the first projections 71 is formed in the first build-up layer 81. The opening 81a is performed, for example, by laser processing. After the opening 81a is formed, a desmear treatment is performed to remove the residual residue remaining on the surface of the first projection 71 in each opening 81a. Then, a seed layer 53 is formed on the first build-up layer 81 and each of the first bumps 71. As the seed layer 53, for example, a palladium (Pd) / copper (Cu) laminated film is formed by electroless plating. The seed layer 53 can also form a Ti/Cu laminated film by sputtering.
關於圖3(b) About Figure 3(b)
將乾膜阻劑62層疊於晶種層53上，使用光微影(photography)技術，於乾膜阻劑62形成露出晶種層53之一部分的複數個開口62a。各開口62a形成為露出 第1凸墊71。 The dry film resist 62 is laminated on the seed layer 53, and a plurality of openings 62a exposing a portion of the seed layer 53 are formed in the dry film resist 62 using a photolithography technique. Each of the openings 62a is formed to expose the first projection 71.
關於圖3(c) About Figure 3(c)
藉由電鍍，於乾膜阻劑62之各開口62a內的晶種層53上，形成第2凸墊72以及連接第2凸墊72與第1凸墊71之第1再配線及通路(via)32a。另，第1再配線延伸於圖式之深度方向，並未圖示於圖3(c)。第2凸墊72之L/S(線寬度/間隙)為5/5~50/50mm左右。又，第2凸墊72之厚度自第1增層81之上面起算，為8~30μm左右。 The second bump 72 and the first rewiring and via connecting the second bump 72 and the first bump 71 are formed on the seed layer 53 in each opening 62a of the dry film resist 62 by electroplating. ) 32a. Further, the first rewiring extends in the depth direction of the drawing, and is not shown in FIG. 3(c). The L/S (line width/gap) of the second projection 72 is about 5/5 to 50/50 mm. Further, the thickness of the second projection 72 is approximately 8 to 30 μm from the upper surface of the first buildup layer 81.
關於圖3(d) About Figure 3(d)
將乾膜阻劑62剝離，露出第2凸墊72及晶種層53。將從第2凸墊72及第1再配線露出之晶種層53除去。 The dry film resist 62 is peeled off to expose the second bump 72 and the seed layer 53. The seed layer 53 exposed from the second bump 72 and the first rewiring is removed.
關於圖3(e) About Figure 3(e)
於第2凸墊72及第1增層81上形成第2增層82。作為第2增層82，較佳為膜式。第2增層82於真空中層疊後，進行正式硬化。第2增層82形成為其外圍被配置於支持基板52之外圍的內側。 The second buildup layer 82 is formed on the second bump 72 and the first buildup layer 81. As the second buildup layer 82, a film type is preferable. After the second build-up layer 82 is laminated in a vacuum, it is subjected to main hardening. The second build-up layer 82 is formed such that its outer periphery is disposed on the inner side of the periphery of the support substrate 52.
關於圖4(a) About Figure 4(a)
於第2增層82形成用以露出各第2凸墊72之開口82a。開口82a例如藉由雷射加工進行。形成開口82a後，進行去膠渣處理，將各開口82a內之第2凸墊72的表面殘留的殘漬除去。然後，於第2增層82及各第2凸墊72上形成晶種層54。晶種層54，例如藉由無電電鍍形成鈀(Pd)/銅(Cu)積層膜。晶種層54亦可藉由濺鍍法形成Ti/Cu積層膜。 An opening 82a for exposing each of the second projections 72 is formed in the second build-up layer 82. The opening 82a is performed, for example, by laser processing. After the opening 82a is formed, the desmear treatment is performed to remove the residual residue remaining on the surface of the second projection 72 in each opening 82a. Then, a seed layer 54 is formed on the second buildup layer 82 and each of the second bump pads 72. The seed layer 54 is formed, for example, by electroless plating to form a palladium (Pd)/copper (Cu) laminated film. The seed layer 54 can also form a Ti/Cu buildup film by sputtering.
關於圖4(b) About Figure 4(b)
將乾膜阻劑63層疊於晶種層54上，使用光微影技術，於乾膜阻劑63形成露出晶種層54之一部分的複數個開口63a。各開口63a形成為露出第2凸墊72。 The dry film resist 63 is laminated on the seed layer 54, and a plurality of openings 63a exposing a portion of the seed layer 54 are formed in the dry film resist 63 using photolithography. Each of the openings 63a is formed to expose the second projection 72.
關於圖4(c) About Figure 4(c)
藉由電鍍，於乾膜阻劑63之各開口63a內的晶種層54上，形成第3凸墊73以及連接第3凸墊73與第2凸墊72之第2再配線及通路32b。另，第2再配線延伸於圖式之深度方向，並未圖示於圖4(c)。第3凸墊73相當於圖1所圖示之連接端子33。第3凸墊73之L/S(線寬度/間隙)為5/5~50/50mm左右。又，第3凸墊73之厚度從第2增層82之上面起算，為8~30μm左右。 The third bump 73 and the second rewiring and via 32b connecting the third bump 73 and the second bump 72 are formed on the seed layer 54 in each opening 63a of the dry film resist 63 by electroplating. Further, the second rewiring extends in the depth direction of the drawing, and is not shown in FIG. 4(c). The third projection 73 corresponds to the connection terminal 33 illustrated in Fig. 1 . The L/S (line width/gap) of the third projection 73 is about 5/5 to 50/50 mm. Further, the thickness of the third projection 73 is approximately 8 to 30 μm from the upper surface of the second buildup layer 82.
關於圖4(d) About Figure 4(d)
將乾膜阻劑63剝離，露出第3凸墊73及晶種層54。將從第3凸墊73及第2再配線(未圖示)露出之晶種層54除去。 The dry film resist 63 is peeled off to expose the third bump 73 and the seed layer 54. The seed layer 54 exposed from the third bump 73 and the second rewiring (not shown) is removed.
關於圖5(a) About Figure 5(a)
如上述，預先於電極焊墊26上形成柱狀電極22，形成焊料層23形成於柱狀電極22之端面的半導體元件2。 As described above, the columnar electrode 22 is formed in advance on the electrode pad 26, and the semiconductor element 2 in which the solder layer 23 is formed on the end surface of the columnar electrode 22 is formed.
然後，將半導體元件2形成於柱狀電極22之端面的焊料層23配置於第3凸墊73上，進行定位。焊料層23與第3凸墊73之對位，可移動半導體元件2來進行，亦可移動支持基板52來進行。 Then, the solder layer 23 in which the semiconductor element 2 is formed on the end surface of the columnar electrode 22 is placed on the third bump 73 and positioned. The solder layer 23 is aligned with the third bump 73, and the semiconductor element 2 can be moved, or the support substrate 52 can be moved.
然後，藉由超音波接合，將半導體元件2之焊料層23與第3凸墊73接合。超音波接合係以砧支撐支持基板52之下面，將震盪頭(horn)抵接於半導體元件2形成有柱狀電極22之面的相反面，於施予荷重之狀態下施加超音波使之振動。 Then, the solder layer 23 of the semiconductor element 2 is bonded to the third bump 73 by ultrasonic bonding. The ultrasonic bonding supports the lower surface of the support substrate 52 with the anvil, and the horn is abutted against the opposite surface of the surface of the semiconductor element 2 on which the columnar electrode 22 is formed, and the ultrasonic wave is applied to vibrate in a state where the load is applied. .
柱狀電極22藉由鍍銅形成為高度10~30μm，於其軸方向端，藉由鍍覆形成高度10~30μm之焊料層23。另，因長寬比(aspect ratio)之原因，柱狀電極22與焊料層23之合計高度較佳為40~60μm左右。作為焊料層23之材料，使用Sn-Ag，或Sn-3Ag-0.5Cu(SAC305)或者Sn-4Ag-0.5Cu(SAC405)。焊料層23之熔點為220~230℃左右。 The columnar electrode 22 is formed to have a height of 10 to 30 μm by copper plating, and a solder layer 23 having a height of 10 to 30 μm is formed by plating at its axial end. Further, the total height of the columnar electrode 22 and the solder layer 23 is preferably about 40 to 60 μm due to the aspect ratio. As a material of the solder layer 23, Sn-Ag, or Sn-3Ag-0.5Cu (SAC305) or Sn-4Ag-0.5Cu (SAC405) is used. The melting point of the solder layer 23 is about 220 to 230 °C.
焊料層23與第3凸墊73之接合係藉由低溫超音波接合進行，該低溫超音波接合係將接合用支持基板之溫度設定為較焊料層23之熔點低的溫度，例如100 ℃左右(設定值)。亦可於加熱接合用支持基板之同時，將接合頭加熱至100℃左右。 The bonding between the solder layer 23 and the third bump 73 is performed by low-temperature ultrasonic bonding, which sets the temperature of the bonding support substrate to a temperature lower than the melting point of the solder layer 23, for example, about 100 ° C ( Set value). It is also possible to heat the bonding head to about 100 ° C while heating the bonding support substrate.
若以此方式藉由低溫進行超音波接合，則可抑制焊料層23擴展於第3凸墊73之上面上。 If ultrasonic bonding is performed at a low temperature in this manner, it is possible to suppress the solder layer 23 from spreading over the upper surface of the third bump 73.
圖7為圖5(a)所圖示之接合區域VII的放大剖面圖，係將SEM(掃描式電子顯微鏡，Scanning Electron Microscope)拍攝之照片加以描跡的示意圖。如此圖所示，焊料層23形成為與連接端子33之接合面即界面的寬度小於與柱狀電極22之接合面即界面的寬度。又，雖未圖示，但焊料層23形成為與連接端子33之接合面即界面的間距方向之長度小於與柱狀電極22之接合面即界面的間距方向之長度。亦即，焊料層23其與連接端子33之界面具有小於柱狀電極22之端面面積的面積。此表示當藉由超音波接合將焊料層23與連接端子33接合時，焊料層23於接端子33上之擴展受到抑制。亦即，形成於柱狀電極22上之焊料層23的量全部參與和連接端子33之接合。因此，與焊料層會擴展於連接端子33上之以往的連接方法相較之下，可減少形成於柱狀電極22上之焊料層23的量。惟，於此時間點，由於是以低溫之接合，故可能無法確保足夠之接合力。 Fig. 7 is an enlarged cross-sectional view showing the joint region VII shown in Fig. 5(a), showing a photograph taken by SEM (Scanning Electron Microscope). As shown in the figure, the solder layer 23 is formed such that the width of the interface which is the bonding surface with the connection terminal 33 is smaller than the width of the interface which is the bonding surface with the columnar electrode 22. Further, although not shown, the solder layer 23 is formed such that the length of the interface in the direction of the interface with the connection terminal 33 is smaller than the length of the interface between the columnar electrodes 22 and the interface. That is, the solder layer 23 has an interface with the connection terminal 33 having an area smaller than the end surface area of the columnar electrode 22. This indicates that when the solder layer 23 is bonded to the connection terminal 33 by ultrasonic bonding, the expansion of the solder layer 23 on the terminal 33 is suppressed. That is, the amount of the solder layer 23 formed on the columnar electrode 22 is all engaged with the connection of the connection terminal 33. Therefore, the amount of the solder layer 23 formed on the columnar electrode 22 can be reduced as compared with the conventional connection method in which the solder layer spreads over the connection terminal 33. However, at this point of time, due to the low temperature bonding, sufficient bonding force may not be ensured.
關於圖5(b) About Figure 5(b)
藉由環氧樹脂等熱硬化性樹脂4，將接合於第3凸墊73之半導體元件2加以密封。樹脂4覆蓋第2增層82及半導體元件2之上面，且覆蓋成填充於第2增層82與半導體元件2之間。樹脂4亦可覆蓋支持基板52之外圍。圖5(b)係以此種狀態之圖的形態作例示。於此狀態下，將樹脂4加熱至硬化溫度例如150℃左右較高的溫度使之硬化。 The semiconductor element 2 bonded to the third bump 73 is sealed by a thermosetting resin 4 such as an epoxy resin. The resin 4 covers the second build-up layer 82 and the upper surface of the semiconductor element 2, and is covered so as to be filled between the second build-up layer 82 and the semiconductor element 2. The resin 4 may also cover the periphery of the support substrate 52. Fig. 5(b) is exemplified in the form of a diagram in this state. In this state, the resin 4 is heated to a curing temperature of, for example, a relatively high temperature of about 150 ° C to be hardened.
圖8為圖5(b)所圖示之接合區域VIII的放大剖面圖，係將SEM(掃描式電子顯微鏡，Scanning Electron Microscope)拍攝之照片加以描跡的示意圖。 Fig. 8 is an enlarged cross-sectional view showing the joint region VIII shown in Fig. 5(b), which is a schematic view showing a photograph taken by SEM (Scanning Electron Microscope).
將焊料層23與連接端子33低溫超音波接合後，藉由樹脂4密封，使樹指4硬化。藉由此處理，焊料層23之周圍會被經硬化之樹脂4圍繞。因此，於此狀態下，假設即使焊料層23熔融，亦為於連接端子33上之擴展受到抑制的狀態。 After the solder layer 23 is bonded to the connection terminal 33 at a low temperature, the resin is sealed by the resin 4 to harden the tree fingers 4. By this treatment, the periphery of the solder layer 23 is surrounded by the hardened resin 4. Therefore, in this state, it is assumed that even if the solder layer 23 is melted, the expansion on the connection terminal 33 is suppressed.
關於圖5(c) About Figure 5(c)
切割支持基板52之外緣，露出支持基板52之剝離層52a。 The outer edge of the support substrate 52 is cut to expose the peeling layer 52a of the support substrate 52.
關於圖6(a) About Figure 6(a)
將絕緣基板51與樹脂4之自切割部起的外圍側從本體1A剝離。然後，藉由蝕刻將殘留於本體1A之晶種層52b(參照圖2(a))與剝離層52a的一部分除去。另，此處所謂本體1A，係指用上述方法製造之含有第1、第2增層81、82與第1、第2、第3凸墊71、72、73與接合於第3凸墊73之2個半導體元件2的電子零件模組。 The peripheral side of the insulating substrate 51 and the resin 4 from the cut portion is peeled off from the body 1A. Then, the seed layer 52b (see FIG. 2(a)) remaining in the body 1A and a part of the peeling layer 52a are removed by etching. In addition, the term "main body 1A" as used herein refers to the first and second buildup layers 81 and 82 and the first, second, and third projection pads 71, 72, 73 and the third projection pad 73. The electronic component module of the two semiconductor elements 2.
關於圖6(b) About Figure 6(b)
於第1增層81之半導體元件2側相反之面形成阻焊劑64，使用光蝕刻技術，於阻焊劑64形成露出第1凸墊71之開口。第1凸墊71為焊球裝載部即外部端子部34，將焊球11裝載於從各開口露出之外部端子部34。然後，以較焊料層23及焊球11之熔點高的溫度例如260℃左右的溫度進行回焊。藉由回焊，接合焊球11與外部端子部34。又，此時，焊料層23會熔融，焊料層23與連接端子33正式接合。 A solder resist 64 is formed on the surface opposite to the side of the semiconductor element 2 of the first build-up layer 81, and an opening exposing the first bump 71 is formed in the solder resist 64 by photolithography. The first bump 71 is an external terminal portion 34 which is a solder ball mounting portion, and the solder ball 11 is mounted on the external terminal portion 34 exposed from each opening. Then, reflow is performed at a temperature higher than the melting point of the solder layer 23 and the solder ball 11, for example, at a temperature of about 260 °C. The solder ball 11 and the external terminal portion 34 are joined by reflow soldering. Moreover, at this time, the solder layer 23 is melted, and the solder layer 23 is formally joined to the connection terminal 33.
關於圖6(c) About Figure 6(c)
於2個半導體元件2之邊界進行切割，得到各個半導體裝置1。另，於個片化之前，亦可進行測試及打印。 The semiconductor device 1 is obtained by cutting at the boundary between the two semiconductor elements 2. In addition, it can be tested and printed before being sliced.
如上述，藉由回焊，接合焊球11與外部端子部34，且正式接合焊料層23與連接端子33。 As described above, the solder ball 11 and the external terminal portion 34 are bonded by reflow soldering, and the solder layer 23 and the connection terminal 33 are formally joined.
如圖8中說明般，進行回焊前，接合於連接端子33之焊料層23被經硬化之 樹脂4覆蓋著周圍。因此，於回焊時，即使焊料層23熔融，焊料層23於連接端子33之擴展亦會受到經硬化之樹脂4的抑制。因此，可使接合部之間距小，可謀求半導體裝置1之小型化。而且，即便使接合部之間距小，亦可確保接合所需之焊料量，因此，焊料層23之接合力不會下降，可達成可靠性高之接合。 As described in Fig. 8, before the reflow is performed, the solder layer 23 bonded to the connection terminal 33 is covered with the hardened resin 4 to cover the periphery. Therefore, at the time of reflow, even if the solder layer 23 is melted, the expansion of the solder layer 23 at the connection terminal 33 is suppressed by the hardened resin 4. Therefore, the distance between the joint portions can be made small, and the size of the semiconductor device 1 can be reduced. Further, even if the distance between the joint portions is small, the amount of solder required for joining can be ensured. Therefore, the bonding force of the solder layer 23 is not lowered, and a highly reliable joint can be achieved.
以往，作為以銲點凸塊進行之接合方式，已知有C4(Controlled Collapse Chip Connection)方式，但是此方式，接合部間距之極限為100μm左右。相對於此，於上述實施形態，則可使接合部之間距為20~60μm。 Conventionally, a C4 (Controlled Collapse Chip Connection) method has been known as a bonding method using solder bumps. However, the limit of the pitch of the bonding portions is about 100 μm. On the other hand, in the above embodiment, the distance between the joint portions can be 20 to 60 μm.
若根據本發明之第1實施形態，則可達成下述效果。 According to the first embodiment of the present invention, the following effects can be achieved.
(1)施加超音波，將焊料層23與連接端子33接合，藉由熱硬化性樹脂4將半導體元件2密封，使熱硬化性樹脂4硬化，使熱硬化性樹脂4硬化後，將焊料層23加熱至較焊料層23之熔點高的溫度，將焊料層23與連接端子33接合。因此，可抑制焊料層23擴展於連接端子33，即使減少焊料量，亦能確保足夠之接合力。藉此，可使接合部之間距小，因此能夠謀求半導體裝置1之小型化。 (1) Ultrasonic wave is applied, the solder layer 23 is bonded to the connection terminal 33, the semiconductor element 2 is sealed by the thermosetting resin 4, the thermosetting resin 4 is cured, and the thermosetting resin 4 is cured, and then the solder layer is cured. 23 is heated to a temperature higher than the melting point of the solder layer 23, and the solder layer 23 is bonded to the connection terminal 33. Therefore, it is possible to suppress the solder layer 23 from spreading to the connection terminal 33, and it is possible to secure a sufficient bonding force even if the amount of solder is reduced. Thereby, since the distance between the joint portions can be made small, the size of the semiconductor device 1 can be reduced.
施加超音波將焊料層23與連接端子33接合，藉此可抑制焊料層23擴展於周圍。以往，作為抑制焊料層擴展之方法，一直使用將阻焊劑形成於焊料層形成區域之周圍的方法，但是此方法，會增加工時。上述實施形態，由於無須形成阻焊劑，因此，可提升接合之單位時間處理量(throughput)。又，由於對焊料層23與連接端子33進行超音波接合，故無須於接合部使用焊料助焊劑(solder flux)，不用塗布或清洗焊料助焊劑，藉由此因素，亦可提升接合之單位時間處理量。 The application of the ultrasonic waves bonds the solder layer 23 to the connection terminal 33, whereby the solder layer 23 can be prevented from expanding to the periphery. Conventionally, as a method of suppressing expansion of a solder layer, a method of forming a solder resist around a solder layer forming region has been used. However, this method increases man-hours. In the above embodiment, since it is not necessary to form a solder resist, the throughput per unit time of bonding can be improved. Further, since the solder layer 23 and the connection terminal 33 are ultrasonically bonded, it is not necessary to use solder flux in the joint portion, and it is not necessary to apply or clean the solder flux, and the unit time of the bonding can be improved by this factor. Processing volume.
(2)焊料層23具有與連接端子33之界面的寬度較與柱狀電極22之界面的寬度小的形狀。因此，焊料層23與連接端子33之對位存在餘裕空間，能夠提升對位作業之效率。 (2) The solder layer 23 has a shape in which the width of the interface with the connection terminal 33 is smaller than the width of the interface of the columnar electrode 22. Therefore, there is a margin in the alignment between the solder layer 23 and the connection terminal 33, and the efficiency of the alignment operation can be improved.
(3)即便使焊料層23之寬度小於連接端子33之寬度，換言之， 即便使連接端子33之寬度大於焊料層23之寬度，亦可抑制焊料層23擴展於連接端子。藉由使連接端子33之寬度大於焊料層23之寬度，焊料層23與連接端子33之對位存在餘裕空間，藉此亦能夠提升對位作業之效率。 (3) Even if the width of the solder layer 23 is made smaller than the width of the connection terminal 33, in other words, even if the width of the connection terminal 33 is larger than the width of the solder layer 23, the solder layer 23 can be prevented from expanding to the connection terminal. By making the width of the connection terminal 33 larger than the width of the solder layer 23, there is a margin in the alignment between the solder layer 23 and the connection terminal 33, whereby the efficiency of the alignment operation can be improved.
(4)焊料層23與連接端子33之接合，係以較焊料層23之熔點低的溫度進行。因此，可確實地抑制焊料層23擴展於連接端子33。 (4) The bonding of the solder layer 23 and the connection terminal 33 is performed at a temperature lower than the melting point of the solder layer 23. Therefore, it is possible to surely suppress the solder layer 23 from spreading to the connection terminal 33.
(5)當將焊料層23與連接端子33正式接合時，同時將焊球11接合於焊球裝載部(外部端子部)34。因此，可減少製造步驟，提升生產性。 (5) When the solder layer 23 and the connection terminal 33 are formally joined, the solder ball 11 is simultaneously bonded to the solder ball mounting portion (external terminal portion) 34. Therefore, manufacturing steps can be reduced and productivity can be improved.
-第2實施形態- - Second embodiment -
圖9為表示本發明之半導體裝置第2實施形態之接合部的放大剖面圖。 Fig. 9 is an enlarged cross-sectional view showing a joint portion of a second embodiment of the semiconductor device of the present invention.
第2實施形態具有障壁層28介於焊料層23與柱狀電極22之間的構造。作為障壁層28之材料，例如可舉鎳。藉由設置障壁層28，可抑制形成柱狀電極22之銅擴散於焊料層23內，抑制形成Cu3Sn。由於Cu3Sn之體積較Sn單質小，故會因生成Cu3Sn而於焊料層23內形成空隙，而有可能會於焊料層23產生裂紋。因此，藉由設置障壁層28，可提升接合之可靠性。障壁層28較佳與柱狀電極22及焊料層23一樣藉由鍍覆形成。 The second embodiment has a structure in which the barrier layer 28 is interposed between the solder layer 23 and the columnar electrode 22. As a material of the barrier layer 28, nickel is mentioned, for example. By providing the barrier layer 28, it is possible to suppress diffusion of copper forming the columnar electrode 22 into the solder layer 23 and suppress formation of Cu 3 Sn. Since the volume of Cu 3 Sn is smaller than that of Sn, a void is formed in the solder layer 23 due to the formation of Cu 3 Sn, and cracks may occur in the solder layer 23 . Therefore, by providing the barrier layer 28, the reliability of the bonding can be improved. The barrier layer 28 is preferably formed by plating like the columnar electrode 22 and the solder layer 23.
第2實施形態之其他構造與第1實施形態相同。因此，於第2實施形態，亦達成與第1實施形態同樣之效果。 The other structure of the second embodiment is the same as that of the first embodiment. Therefore, in the second embodiment, the same effects as those in the first embodiment are achieved.
-第3實施形態- - Third embodiment -
圖10為表示本發明之半導體裝置第3實施形態的剖面圖。 Fig. 10 is a cross-sectional view showing a third embodiment of the semiconductor device of the present invention.
第3實施形態具有透過通路36a將連接端子36連接於配線35最上層之配線部35a的構造。亦即，於配線35之配線部35a上形成增層，於該增層設置開口，形成通路36a及連接端子36。 In the third embodiment, the connection terminal 36 is connected to the wiring portion 35a of the uppermost layer of the wiring 35 through the transmission path 36a. That is, a build-up layer is formed on the wiring portion 35a of the wiring 35, and an opening is formed in the build-up layer to form the via 36a and the connection terminal 36.
第3實施形態之其他構造與第1實施形態相同。因此，於第3實施形態，亦達成與第1實施形態同樣之效果。 The other structure of the third embodiment is the same as that of the first embodiment. Therefore, in the third embodiment, the same effects as those of the first embodiment are achieved.
-第4實施形態- - Fourth embodiment -
圖11為表示本發明之半導體裝置第4實施形態的剖面圖。 Figure 11 is a cross-sectional view showing a fourth embodiment of the semiconductor device of the present invention.
第4實施形態具有下述構造：配線37之最下層37a具有焊球裝載部即外部端子部與連接於該外部端子部之配線部。此構造相較於圖1所示之第1實施形態，可將「為最下層之導體層的外部端子部34」與「最下層之增層」省略，其中該「最下層之增層」形成連接於該外部端子部34之通路。 The fourth embodiment has a structure in which the lowermost layer 37a of the wiring 37 has an external terminal portion which is a solder ball mounting portion and a wiring portion that is connected to the external terminal portion. Compared with the first embodiment shown in FIG. 1, this structure can omit "the outer terminal portion 34 of the lowermost conductor layer" and the "addition layer of the lowermost layer", wherein the "lower layer buildup" is formed. A path connected to the external terminal portion 34.
第4實施形態之其他構造與第1實施形態相同。因此，於第4實施形態，亦可達成與第1實施形態同樣之效果。並且，於第4實施形態，可減少製造步驟，提升生產性，且能謀求半導體裝置1之薄型化。 The other structure of the fourth embodiment is the same as that of the first embodiment. Therefore, in the fourth embodiment, the same effects as those of the first embodiment can be achieved. Further, in the fourth embodiment, the number of manufacturing steps can be reduced, the productivity can be improved, and the thickness of the semiconductor device 1 can be reduced.
另，於上述各實施形態，係使支持基板52為將剝離層52a形成於玻璃板等絕緣基板51上之構造來作例示。然而，支持基板52例如亦可為下述構造：將鉑(Pt)層呈厚度大致均一狀地形成於附SiO2之Si基板的構造，或使用Si基板代替絕緣基板51，於該Si基板形成有剝離層52a的構造。又，剝離層52a可為於Si膜上積層有數nm之鐵(Fe)等金屬膜的構造。 Further, in each of the above embodiments, the support substrate 52 is exemplified as a structure in which the peeling layer 52a is formed on an insulating substrate 51 such as a glass plate. However, the support substrate 52 may have, for example, a structure in which a platinum (Pt) layer is formed in a substantially uniform thickness on a Si substrate to which SiO 2 is attached, or a Si substrate is used instead of the insulating substrate 51, and the Si substrate is formed. There is a configuration of the peeling layer 52a. Further, the release layer 52a may have a structure in which a metal film such as iron (Fe) is laminated on the Si film.
又，亦可使用附有鎳(Ni)膜之不銹鋼(SUS)基板作為支持基板52。 Further, a stainless steel (SUS) substrate with a nickel (Ni) film may be used as the support substrate 52.
於上述各實施形態，雖然為使用四邊形絕緣基板即面板級四邊形基板之製造方法，但本發明亦可使用晶圓級(wafer level)基板(使用晶圓作為支持基板)來製造。晶圓級基板有時為圓形狀基板。 In each of the above embodiments, a method of manufacturing a panel-level quadrilateral substrate which is a quadrilateral insulating substrate is used. However, the present invention can also be manufactured using a wafer level substrate (using a wafer as a supporting substrate). The wafer level substrate is sometimes a circular shaped substrate.
於上述各實施形態中，雖以扇出封裝(Fan-out Package)之形態例示，但本發明亦可為扇入封裝(Fan-in Package)，主要可應用於所有藉由焊料層將柱狀電極與連接端子接合之覆晶構裝。 In the above embodiments, the fan-out package is exemplified, but the present invention may also be a fan-in package, and is mainly applicable to all columns by a solder layer. The flip chip is bonded to the connection terminal.
於上述實施形態，半導體裝置1雖以具有1個半導體元件2之構造的形態例示。然而，半導體裝置1亦可為具有複數個半導體元件2之構造。於該情形時，半導體裝置1所含之半導體元件2可具有不同之功能或形狀。又，半導 體裝置1除了半導體元件2外，亦可還具有感測器或電阻、電容器、線圈等被動元件。 In the above embodiment, the semiconductor device 1 is exemplified in a configuration having one semiconductor element 2. However, the semiconductor device 1 may also have a configuration in which a plurality of semiconductor elements 2 are provided. In this case, the semiconductor element 2 included in the semiconductor device 1 may have a different function or shape. Further, the semiconductor device 1 may have a passive element such as a sensor or a resistor, a capacitor, or a coil in addition to the semiconductor element 2.
上述中，雖說明了各種實施形態及變形例，但本發明並不限定於此等內容。於本發明之技術思想的範圍內可考慮之其他態樣亦包含於本發明之範圍內。 In the above, various embodiments and modifications have been described, but the present invention is not limited thereto. Other aspects that may be considered within the scope of the technical idea of the present invention are also included in the scope of the present invention.
下述優先權基礎案之揭示內容被引用於本案。 The disclosure of the following priority basis is cited in this case.
日本專利申請2017年第89947號(2017年4月28日申請) Japanese Patent Application No. 89947 (applied on April 28, 2017)
Claims (15)
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| Application Number | Priority Date | Filing Date | Title |
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| JPJP2017-089947 | 2017-04-28 | ||
| JP2017089947A JP6534700B2 (en) | 2017-04-28 | 2017-04-28 | Semiconductor device manufacturing method |
| PCT/JP2018/008866 WO2018198544A1 (en) | 2017-04-28 | 2018-03-07 | Method for manufacturing semiconductor device, and semiconductor device |
| ??PCT/JP2018/008866 | 2018-03-07 |
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| TW201901825A true TW201901825A (en) | 2019-01-01 |
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| TW107109278A TW201901825A (en) | 2017-04-28 | 2018-03-19 | Method for manufacturing semiconductor device, and semiconductor device |
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| JP (1) | JP6534700B2 (en) |
| TW (1) | TW201901825A (en) |
| WO (1) | WO2018198544A1 (en) |
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| JPH0637143A (en) * | 1992-07-15 | 1994-02-10 | Toshiba Corp | Semiconductor device and manufacture thereof |
| US7642135B2 (en) * | 2007-12-17 | 2010-01-05 | Skyworks Solutions, Inc. | Thermal mechanical flip chip die bonding |
| JP2013131623A (en) * | 2011-12-21 | 2013-07-04 | Murata Mfg Co Ltd | Semiconductor device and manufacturing method of the same |
| JP6006523B2 (en) * | 2012-04-27 | 2016-10-12 | 新光電気工業株式会社 | Connection structure, wiring board unit, electronic circuit component unit, and electronic apparatus |
| JP2014168791A (en) * | 2013-03-01 | 2014-09-18 | Hitachi Chemical Co Ltd | Flux film, flip-chip connection method, and semiconductor device |
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| JP6534700B2 (en) | 2019-06-26 |
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