TW201620135A - 鰭式場效電晶體裝置結構及其形成方法 - Google Patents

鰭式場效電晶體裝置結構及其形成方法 Download PDF

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TW201620135A
TW201620135A TW104132973A TW104132973A TW201620135A TW 201620135 A TW201620135 A TW 201620135A TW 104132973 A TW104132973 A TW 104132973A TW 104132973 A TW104132973 A TW 104132973A TW 201620135 A TW201620135 A TW 201620135A
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layer
fin
transistor
dielectric layer
forming
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TW104132973A
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TWI587511B (zh
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陳建穎
程潼文
張哲誠
倪俊龍
林志忠
林志翰
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台灣積體電路製造股份有限公司
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Abstract

本揭露提供一種鰭式場效電晶體裝置結構及其形成方法。鰭式場效電晶體包括基板以及延伸高於基板的第一鰭式結構與第二鰭式結構。鰭式場效電晶體亦包括形成於第一鰭式結構之上的第一電晶體及形成於第二鰭式結構之上的第二電晶體。鰭式場效電晶體亦包括層間介電層結構形成於第一電晶體與第二電晶體之間的一末端對末端間距(end-to-end gap)之中，且此末端對末端間距具有一寬度為約20nm至約40nm。

Description

鰭式場效電晶體裝置結構及其形成方法
本揭露係有關於一種半導體結構，且特別有關於一種鰭式場效電晶體裝置結構及其形成方法。
半導體裝置使用於各種電子應用中，舉例而言，諸如個人電腦、手機、數位相機以及其他電子設備。半導體裝置的製造通常是藉由在半導體基板上依序沉積絕緣層或介電層材料、導電層材料以及半導體層材料，接著使用微影製程圖案化所形成的各種材料層，藉以在此半導體基板之上形成電路零件及組件。通常在單一個半導體晶圓上製造數十個或數百個積體電路。藉由沿著切割線切割積體電路，可將位在晶圓上的晶粒單粒化。接著將個別的晶粒分別封裝在多晶片模組中或其它類型的封裝結構中。
隨著半導體工業進展到nm技術製程節點，為了追求更高裝置密度、更高性能與更低成本，在製造與設計兩方面皆面臨挑戰，因此三維設計開始發展，例如鰭式場效電晶體(fin field effect transistor,FinFET)。鰭式場效電晶體具有從基板延伸出來之薄形垂直「鰭」。鰭式場效電晶體的通道形成於垂直鰭之中。閘極位於鰭之上。鰭式場效電晶體之優點可包括降低 短通道效應與較高的電流通量。
雖然現有的鰭式場效電晶體裝置及其製造方法已普遍足以達成預期的目標，然而卻無法完全滿足所有需求。
本揭露提供一種鰭式場效電晶體裝置結構，包括：基板及延伸高於基板的第一鰭式結構與一第二鰭式結構；形成於第一鰭式結構之上的第一電晶體及形成於第二鰭式結構之上的第二電晶體；以及層間介電層結構形成於第一電晶體與第二電晶體之間的一末端對末端間距(end-to-end gap)之中，其中此末端對末端間距具有一寬度為約10nm至約50nm。
本揭露亦提供一種鰭式場效電晶體裝置結構，包括：基板及形成於基板之上的隔離結構；第一鰭式結構埋設於隔離結構之中；第一電晶體形成於第一鰭式結構之上；第二電晶體形成於第一鰭式結構與隔離結構上；層間介電層結構形成於第一電晶體與第二電晶體之間的一末端對末端間距(end-to-end gap)之中，其中末端對末端間距具有一寬度為約10nm至約50nm。
本揭露又提供一種鰭式場效電晶體裝置結構之形成方法，包括：提供基板；形成第一鰭式結構及第二鰭式結構，其中第一鰭式結構及第二鰭式結構延伸高於基板；形成介電層於第一鰭式結構及第二鰭式結構之上；形成多晶矽層、硬罩幕層及光阻層於介電層之上；圖案化光阻層，以形成第一溝槽於光阻層之中，其中第一溝槽具有第一寬度；順應性地形成塗覆層於第一溝槽之中，以形成第二溝槽於光阻層之中，其中第二 溝槽具有小於第一寬度之第二寬度；使用光阻層作為罩幕而圖案化硬罩幕層；使用此硬罩幕層作為罩幕而圖案化多晶矽層，以形成介於第一電晶體與第二電晶體之間的末端對末端間距(end-to-end gap)，其中末端對末端間距具有第三寬度，且第三寬度小於第一寬度。
11‧‧‧第一蝕刻製程
13‧‧‧第二蝕刻製程
15‧‧‧第三蝕刻製程
100‧‧‧鰭式場效電晶體裝置結構
102‧‧‧基板
104‧‧‧鰭式結構
104a‧‧‧第一鰭式結構
104b‧‧‧第二鰭式結構
106‧‧‧閘極介電層
108‧‧‧隔離結構
110‧‧‧閘極電極
112‧‧‧通道區域
114‧‧‧源極區域
116‧‧‧汲極區域
300a‧‧‧第一電晶體
300b‧‧‧第二電晶體
302‧‧‧介電層
304‧‧‧多晶矽層
306a‧‧‧第一硬罩幕層
306b‧‧‧第二硬罩幕層
308‧‧‧光阻層
308a‧‧‧第一光阻層
308b‧‧‧第二光阻層
310‧‧‧塗覆層
320‧‧‧層間介電層結構
350、352、354‧‧‧溝槽
400a‧‧‧第一電晶體
400b‧‧‧第二電晶體
400c‧‧‧第三電晶體
400d‧‧‧第四電晶體
W1‧‧‧第一寬度
W2‧‧‧第二寬度
W3‧‧‧第三寬度
W4‧‧‧第四寬度
W5‧‧‧第五寬度
W6‧‧‧第六寬度
S1‧‧‧末端距離
根據以下的詳細說明並配合所附圖式做完整揭露。應注意的是，根據本產業的一般作業，圖示並未必按照比例繪製。事實上，可能任意的放大或縮小元件的尺寸，以做清楚的說明。
第1圖為繪示依據本揭露之一些實施例之鰭式場效電晶體裝置結構之立體透視圖。
第2圖為繪示依據本揭露之一些實施例之鰭式場效電晶體結構之俯視圖。
第3A-3I圖為繪示依據本揭露之一些實施例之形成鰭式場效電晶體結構之各個製程階段之剖面圖。
第4A-4G圖為繪示依據本揭露之一些實施例之形成鰭式場效電晶體結構之各個製程階段之剖面圖。
以下的揭露內容提供許多不同的實施例或範例以實施本案的不同特徵。以下的揭露內容敘述各個構件及其排列方式的特定範例，以簡化說明。當然，這些特定的範例並非用以限定。例如，若是本揭露書敘述了一第一特徵形成於一第二特徵之上或上方，即表示其可能包含上述第一特徵與上述第二 特徵是直接接觸的實施例，亦可能包含了有附加特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與第二特徵可能未直接接觸的實施例。另外，以下揭露書不同範例可能重複使用相同的參考符號及/或標記。這些重複係為了簡化與清晰的目的，並非用以限定所討論的不同實施例及/或結構之間有特定的關係。
下文描述實施例的各種變化。藉由各種視圖與所繪示之實施例，類似的元件標號用於標示類似的元件。應可理解的是，可在所述方法之前、之間或之後實施額外的操作步驟，且在所述方法的其他實施例中，部分的操作步驟可以被取代或省略。
本揭露提供形成鰭式場效電晶體(fin field effect transistor,FinFET)裝置結構之實施例。第1圖為繪示依據本揭露之一些實施例之鰭式場效電晶體結構100之立體透視圖。
鰭式場效電晶體結構100包括基板102。基板102可以由矽或其他半導體材料所組成。另外，基板102可包括其他元素半導體，例如，鍺。在一些實施例中，基板102由化合物半導體所組成，例如，碳化矽(silicon carbide,SiC)、砷化鎵(gallium arsenic,GaAs)、砷化銦(indium arsenide,InAs)或磷化銦(indium phosphide,InP)。在一些實施例中，基板102由合金半導體所組成，例如矽鍺(Silicon germanium,SiGe)、矽碳化鍺(silicon germanium carbide,SiGeC)、砷磷化鎵(gallium arsenic phosphide,GaAsP)或磷化鎵銦(gallium indium phosphide,GaInP)。在一些實施例中，基板102包括磊晶層。舉例而言， 基板102具有位於塊狀半導體上的磊晶層。
鰭式場效電晶體結構100更包括一或多個鰭式結構104(例如矽鰭)，且鰭式結構104自基板102延伸。鰭式結構104可視需要地包括鍺(Ge)。鰭式結構104可藉由合適製程而形成，例如微影製程與蝕刻製程。在一些實施例中，使用乾式蝕刻或電漿製程蝕刻基板102而得到鰭式結構104。
形成隔離結構108以環繞鰭式結構104，且隔離結構108可包括，例如，淺溝隔離結構(shallow trench isolation,STI)。在一些實施例中，鰭式結構104的下部份被隔離結構108所圍繞，且鰭式結構104的上部份突出於隔離結構108，如第1圖所示。換言之，鰭式結構104之一部份埋設於隔離結構108之中。隔離結構108用於避免電性干擾或串音干擾(crosstalk)。
鰭式場效電晶體結構100更包括一閘極堆疊結構，此閘極堆疊結構包括閘極電極110與閘極介電層106。閘極堆疊結構形成於鰭式結構104的中心部份之上。在一些實施例中，多個閘極堆疊結構形成於鰭式結構104之上。閘極結構之中可包括多層其他的膜層，例如蓋層、界面層、間隔組件及/或其他合適的特徵。
閘極介電層106可包括介電材料，例如氧化矽、氮化矽、氮氧化矽、具有高介電常數(high-k)之介電材料，或上述之組合。高介電常數之介電材料的例子可包括：氧化鉿(hafnium oxide)、氧化鋯(zirconium oxide)、氧化鋁(aluminum oxide)、二氧化鉿-氧化鋁合金(hafnium dioxide-alumina alloy)、氧化矽鉿(hafnium silicon oxide)、氮氧化矽鉿(hafnium silicon oxynitride)、氧化鉭鉿(hafnium tantalum oxide)、氧化鈦鉿(hafnium titanium oxide)、氧化鋯鉿(hafnium zirconium oxide)、類似的材料或上述之組合。
閘極電極110可包括多晶矽或金屬。金屬包括氮化鉭(tantalum nitride,TaN)、矽化鎳(nickel silicon,NiSi)、矽化鈷(cobalt silicon,CoSi)、鉬(molybdenum,Mo)、銅(copper,Cu)、鎢(tungsten,W)、鋁(aluminum,Al)、鈷(cobalt,Co)、鋯(zirconium,Zr)、鉑(platinum,Pt)或其他合適的材料。閘極電極110可由閘極後製(gate last)製程(或閘極取代製程)所形成。在一些實施例中，閘極堆疊結構包括其他膜層，例如界面層、蓋層、擴散/阻障層或其他合適的膜層。
鰭式結構104包括被閘極電極110與閘極介電層106所包圍或圍繞的通道區域112。可摻雜鰭式結構104，以提供合適的通道給n型鰭式場效電晶體結構(n型金屬氧化物半導體裝置)或p型鰭式場效電晶體結構(p型金屬氧化物半導體裝置)。可使用合適的製程摻雜鰭式結構104，例如，離子佈植製程(ion implantation process)、擴散製程(diffusion process)、退火製程(annealing process)、其他合適的製程或上述之組合。鰭式結構104包括源極區域114與汲極區域116介於通道區域112之間。鰭式場效電晶體結構100可以是微處理器、記憶體胞器(例如，靜態隨機存取記憶體(Static Random-Access Memory,SRAM))及/或其他積體電路。
第2圖為繪示依據本揭露之一些實施例之鰭式場效電晶體結構100之俯視圖。鰭式場效電晶體結構100包括多個 鰭式結構104與多個閘極電極110。閘極電極110橫越於鰭式結構104之上。鰭式場效電晶體結構100被隔離結構108所包圍。
如第2圖所示，鰭式結構104實質上彼此平行。閘極電極110也可彼此平行且實質上垂直於鰭式結構104。在一些實施例中，當從俯視角度觀察時，閘極電極110也可稱為閘極電極線。
第一電晶體300a形成於第一鰭式結構104a之上，且第二電晶體300b形成於第二鰭式結構104b之上。在一些實施例中，第一電晶體300a與第二電晶體300b之間的第三寬度W3為約10nm至約50nm。
第3A-3H圖為繪示依據本揭露之一些實施例之形成鰭式場效電晶體結構100之各個製程階段之剖面圖。第3A-3H圖係沿著第2圖之AA’剖線而繪製。
請參照第3A圖，第一鰭式結構104a與第二鰭式結構104b形成於基板102之上。在一些實施例中，藉由沉積並且圖案化硬罩幕層(未繪示)於基板102之上，以蝕刻基板102，而形成第一鰭式結構104a與第二鰭式結構104b。硬罩幕層形成一圖案，此圖案覆蓋一部份基板102。之後，蝕刻基板102，在被硬罩幕層所覆蓋的區域之間形成溝槽。如此一來，第一鰭式結構104a與第二鰭式結構104b形成於溝槽之間。
之後，沉積介電材料(例如，氧化矽)於溝槽之中，覆蓋第一鰭式結構104a與第二鰭式結構104b。平坦化介電層至第一鰭式結構104a與第二鰭式結構104b或硬罩幕層的頂表面，接著蝕刻介電層至低於第一鰭式結構104a與第二鰭式結構 104b的頂表面。如此一來，第一鰭式結構104a與第二鰭式結構104b的上部份突出於隔離結構108之上，且第一鰭式結構104a與第二鰭式結構104b的下部份受到隔離結構108所圍繞或覆蓋。
另外，在一些其他實施例中，首先形成隔離結構108於基板102之上。形成介於隔離結構108之間的溝槽，以暴露出基板102。例如，藉由使用磊晶製程在溝槽之中成長半導體材料，以形成第一鰭式結構104a與第二鰭式結構104b，其中半導體材料包括，例如，矽、矽鍺或其他合適的材料。當第一鰭式結構104a與第二鰭式結構104b成長至所需高度，蝕刻隔離結構108至低於第一鰭式結構104a與第二鰭式結構104b的頂表面。如此一來，第一鰭式結構104a與第二鰭式結構104b的一部份突出於隔離結構108之上。
如第3A圖所示，介電層302與多晶矽層304依序形成於第一鰭式結構104a、第二鰭式結構104b以及隔離結構108之上。之後，第一硬罩幕層306a與第二硬罩幕層306b形成於多晶矽層304之上。第一硬罩幕層306a可由氧化矽、氮化矽、氮氧化矽或其他合適的材料所組成。第二硬罩幕層306b可由氧化矽、氮化矽、氮氧化矽或其他合適的材料所組成。藉由圖案化製程形成第一硬罩幕層306a與第二硬罩幕層306b。上述圖案化製程包括微影製程與蝕刻製程。微影製程包括光阻塗佈(例如旋轉塗佈)、軟烘烤(soft baking)、光罩對準、曝光、曝光後烘烤(post-exposure baking)、光阻顯影、潤洗、乾燥(例如硬烘烤(hard baking))。蝕刻製程包括乾式蝕刻製程、濕式蝕刻製程或 上述之組合。
依據本揭露之一些實施例，在形成第一硬罩幕層306a與第二硬罩幕層306b之後，形成第一光阻層308a與第二光阻層308b於第二硬罩幕層306b之上，如第3B圖所示。
在一些實施例中，第一光阻層308a是富含碳之膜層(carbon-rich layer)，例如碳化矽(SiC或SixC)。在一些實施例中，第二光阻層308b是富含矽之膜層(silicon-rich layer)，例如氧化矽(SiOx)、氮化矽(SixNy)或氮氧化矽(SiON)。
之後，圖案化第一光阻層308a與第二光阻層308b，以形成溝槽350於第一光阻層308a與第二光阻層308b之中。溝槽350具有第一寬度W1。在一些實施例中，第一寬度W1為約40nm至約80nm。
依據本揭露之一些實施例，在形成溝槽350之後，順應性地形成塗覆層310於溝槽350之中與第二光阻層308b之上，如第3C圖所示。塗覆層310是含氟高分子層(fluorine-containing polymer)。塗覆層310係用於降低溝槽350之寬度。在形成塗覆層310之後，溝槽350具有降低的第二寬度W2。因此，第二寬度W2小於第一寬度W1。
可藉由使用塗覆氣體之塗覆製程形成塗覆層310。在一些實施例中，塗覆製程是電漿製程。塗覆氣體包括含氟氣體，例如四氟甲烷(tetrafluoromethane,CF4)、二氟甲烷(difluoromethane,CH2F2)、六氟化硫(sulfur hexafluoride,SF6)、三氟化氮(nitrogen trifluoride,NF3)、其他合適的氣體或上述之組合。塗覆氣體的流速為約0.1sccm至約100sccm。使 用於電漿製程之偏壓從0V~1000V。使用於電漿製程之電源為約500Watt至約1500Watt。
塗覆層310之覆蓋厚度與塗覆時間相關。塗覆時間為1秒至約50秒。如果塗覆時間太久，則塗覆層310會完全填滿溝槽350，因此，將無法力用溝槽350之圖案對其下方各層進行圖案化。如果塗覆時間太短，則塗覆層310會太薄而無法降低溝槽350之尺寸。
需注意的是，為避免一些不想要的殘餘物(來自於光阻層308a與308b)殘留於溝槽350之中，在形成塗覆層310之前，對溝槽350進行預清潔製程。當清潔溝槽350時，可避免因為形成於溝槽350中之殘餘物所造成的線末端橋接(line-end bridge)問題。
利用含氟氣體進行預清潔製程。含氟氣體包括四氟甲烷(tetrafluoromethane,CF4)、六氟化硫(sulfur hexafluoride,SF6)、三氟化氮(nitrogen trifluoride,NF3)或上述之組合。在一些實施例中，進行預清潔製程之時間為約1秒至約20秒。
依據本揭露之一些實施例，在溝槽350中形成塗覆層310之後，進行第一蝕刻製程11，以移除位於第二光阻層308b上的一部份塗覆層310，如第3D圖所示。在一些實施例中，第一蝕刻製程11是乾式蝕刻製程。
需注意的是，移除位於第二光阻層308b上的一部份塗覆層310，但是留下位於溝槽350側壁與底部的塗覆層310。殘留的塗覆層310係用於降低溝槽350之寬度。殘留的塗覆層310之上部份受到輕微地蝕刻。因此，塗覆層310之頂表面 並未平行於第二光阻層308b之頂表面。
之後，依據本揭露之一些實施例，進行第二乾式蝕刻製程13，以移除塗覆層310的一部份與第二光阻層308b，如第3E圖所示。在一些實施例中，第二蝕刻製程13也是乾式蝕刻製程。
依據本揭露之一些實施例，在第二蝕刻製程13之後，進行第三蝕刻製程15，以移除塗覆層310、第一光阻層308a、一部份之第一硬罩幕層306a、一部份之第二硬罩幕層306b，如第3F圖所示。在一些實施例中，第三蝕刻製程15也是乾式蝕刻製程。
需注意的是，藉由第三蝕刻製程15選擇性地蝕刻溝槽350之底部。此外，蝕刻直接位於塗覆層310下方之第二硬罩幕層306b的部份之後，以暴露一部份的第一硬罩幕層306a。之後，移除暴露的第一硬罩幕層306a。第一硬罩幕層306a是蝕刻停止層。
結果，如第3F圖所示，圖案化第一硬罩幕層306a與第二硬罩幕層306b，以形成溝槽352。溝槽352具有第三寬度W3。第三寬度W3略小於第二寬度W2，且第三寬度W3仍然小於第一寬度W1。在一些實施例中，第三寬度W3為約10nm至約50nm。
依據本揭露之一些實施例，在溝槽352形成之後，使用第一硬罩幕層306a與第二硬罩幕層306b作為罩幕，以圖案化介電層302與多晶矽層304，如第3G圖所示。如此一來，形成溝槽354於多晶矽層304之中。換言之，溝槽354稱為末端對末 端間距(end-to-end gap)。
之後，依據本揭露之一些實施例，移除第一硬罩幕層306a與第二硬罩幕層306b，並且填充介電材料至溝槽354(或稱為末端對末端間距)之中與多晶矽層304之上，如第3H圖所示。
在填充介電材料之後，藉由平坦化製程移除位於溝槽354以外的一部份介電材料，平坦化製程可包括，例如，化學機械研磨製程(chemical mechanical polishing process,CMP)。如此一來，形成層間介電層(inter-layer dielectric,ILD)結構320。
之後，依據本揭露之一些實施例，移除多晶矽層304與介電層302，並且形成閘極介電層106與閘極電極110於鰭式結構104之上，如第3I圖所示。在一些實施例中，閘極介電層106是高介電常數材料，且閘極電極110是金屬閘極電極。在一些實施例中，形成高介電常數材料/金屬閘極電極(HK/MG)堆疊結構於鰭式結構104之上。
金屬閘極電極包括n型功函數金屬或p型功函數金屬。n型功函數金屬可包括鎢(tungsten,W)、銅(copper,Cu)、鈦(titanium,Ti)、銀(silver,Ag)、鋁(aluminum,Al)、鈦鋁合金(titanium aluminum alloy,TiAl)、氮化鈦鋁(titanium aluminum nitride,TiAlN)、碳化鉭(tantalum carbide,TaC)、碳氮化鉭(tantalum carbon nitride,TaCN)、氮化矽鉭(tantalum silicon nitride,TaSiN)、錳(manganese,Mn)或鋯(zirconium,Zr)。p型功函數金屬可包括氮化鈦(titanium nitride(TiN)、氮化鎢 (tungsten nitride,WN)、氮化鉭(tantalum nitride,TaN)或釕(ruthenium,Ru)。金屬閘極藉由物理氣相沉積(PVD)製程、化學氣相沉積(CVD)製程、電鍍(plating)製程、無電電鍍(electroless plating)製程或其他合適的製程所形成。
在層間介電層結構320的左側，第一電晶體300a由閘極介電層106、閘極電極110與源極/汲極(未繪示)所組成。在層間介電層結構320的右側，第二電晶體300b由閘極介電層106、閘極電極110與源極/汲極(未繪示)所組成。第一電晶體300a與第二電晶體300b位於層間介電層結構320的相對兩側側壁上。在一些實施例中，第一電晶體300a是n型金屬氧化物半導體場效電晶體(NMOSFET)，且第二電晶體300b是p型金屬氧化物半導體場效電晶體(PMOSFET)。
如第3I圖所示，層間介電層結構320之側壁具有一底部份與一頂部份，閘極介電層106覆蓋層間介電層結構320之側壁的底部份，以及閘極電極110覆蓋層間介電層結構320之側壁的頂部份。
在一些實施例中，層間介電層結構320具有第三寬度W3為約20nm至約40nm。換言之，由第一電晶體300a與第二電晶體300b之間的末端對末端關鍵尺寸(end-to-end critical dimension,CD)係由第三寬度所定義。
在一些實施例中，介於層間介電層結構320之側壁與第一鰭式結構104a之側壁之間的末端距離(end cap distance)S1為約0.01nm至約50nm。
需注意的是，隨著鰭式場效電晶體裝置結構100尺 寸之縮減，控制末端對末端關鍵尺寸變得更加困難。因此，本揭露使用塗覆層310用於控制末端對末端關鍵尺寸。
利用塗覆層310使溝槽350之寬度從第一寬度W1降低成第二寬度W2。藉由使用較小的第二寬度W2，以使溝槽354形成於多晶矽層304之中，且溝槽354具有第三寬度W3小於第一寬度W1。因此，能夠獲得較小的末端對末端關鍵尺寸(例如第3H圖中的第三寬度W3)。此外，多晶矽層304之輪廓更加垂直。
此外，當末端對末端關鍵尺寸(例如第3H圖中的第三寬度W3)變小的時候，末端距離S1會變大。較大的末端距離S1有助於形成高介電常數材料/金屬閘極電極(HK/MG)堆疊結構。
第4A-4F圖為繪示依據本揭露之一些實施例之形成鰭式場效電晶體結構100之各個製程階段之剖面圖。第4A-4F圖係沿著第2圖之BB’剖線而繪製。
請參照第4A圖，鰭式結構104與隔離結構108形成於基板102之上。鰭式結構104之一部份突出於隔離結構108之上。介電層302與多晶矽層304依序形成於鰭式結構104與隔離結構108之上。之後，第一硬罩幕層306a與第二硬罩幕層306b形成於多晶矽層304之上。
依據本揭露之一些實施例，在形成第二硬罩幕層306b之後，形成光阻層308於硬罩幕層306b之上，如第4B圖所示。光阻層308是單層或是多層。
之後，圖案化光阻層308，以形成溝槽350於光阻層308之中。可形成一或多個溝槽350。可依據實際應用調整溝 槽350之數目。溝槽350具有第四寬度W4。在一些實施例中，第四寬度W4為約40nm至約80nm。
依據本揭露之一些實施例，在形成溝槽350於光阻層308之中後，順應性地形成塗覆層310於溝槽350之中與光阻層308之上，如第4C圖所示。
塗覆層310是含氟高分子層。塗覆層310用於降低溝槽350之寬度。在形成塗覆層310之後，溝槽350具有降低的第五寬度W5。因此，第五寬度W5小於第四寬度W4。
在一些實施例中，可藉由使用塗覆氣體之電漿製程形成塗覆層310。塗覆氣體包括含氟氣體，例如四氟甲烷(tetrafluoromethane,CF4)、二氟甲烷(difluoromethane,CH2F2)、六氟化硫(sulfur hexafluoride,SF6)、三氟化氮(nitrogen trifluoride,NF3)、其他合適的氣體或上述之組合。
依據本揭露之一些實施例，在形成塗覆層310之後，藉由數個蝕刻製程，蝕刻光阻層308、一部份之第一硬罩幕層306a與一部份之第二硬罩幕層306b，如第4D圖所示。如此一來，形成一或多個溝槽352於第一硬罩幕層306a與第二硬罩幕層306b之中。溝槽352具有第六寬度W6，第六寬度W6稍微小於第五寬度W5。
之後，依據本揭露之一些實施例，使用第一硬罩幕層306a與第二硬罩幕層306b作為罩幕，以圖案化介電層302與多晶矽層304，如第4E圖所示。如此一來，形成溝槽354(或稱末端對末端間距(end-to-end gap)於多晶矽層304之中。
之後，依據本揭露之一些實施例，移除第一硬罩 幕層306a與第二硬罩幕層306b，填充介電材料於溝槽354之中與多晶矽層304之上，如第4F圖所示。
在填充溝槽354之後，藉由平坦化製程，例如化學機械研磨製程(CMP)移除位於溝槽354以外的一部份介電材料。如此一來，形成層間介電層(ILD)結構320。
之後，依據本揭露之一些實施例，移除多晶矽層304與介電層302，並且形成閘極介電層106與閘極電極110於鰭式結構104之上，如第4G圖所示。在一些實施例中，閘極介電層106是高介電常數材料，且閘極電極110是金屬閘極電極。在一些實施例中，形成高介電常數材料/金屬閘極電極(HK/MG)堆疊結構於鰭式結構104之上。
如第4G圖所示，閘極介電層106與閘極電極110分成四部份，且分別形成第一電晶體400a、第二電晶體400b、第三電晶體400c、第四電晶體400d。第一電晶體400a由閘極介電層106與閘極電極110所組成，且第二電晶體400b由閘極介電層106與閘極電極110所組成。
層間介電層結構320位於第一電晶體400a與第二電晶體400b之間。此外，層間介電層結構320位於第三電晶體400c與第四電晶體400d之間。
在一些實施例中，介於第一電晶體400a與第二電晶體400b之間的第六寬度W6為約10nm至約50nm。換言之，末端對末端關鍵尺寸(end-to-end critical dimension,CD)由第六寬度W6所定義。
需注意的是，圖案化光阻層308具有寬度為第四寬 度W4的溝槽350，且在形成塗覆層310於溝槽350之後，溝槽350具有降低的第五寬度W5。圖案化光阻層308用於圖案化其下方的第一硬罩幕層306a與第二硬罩幕層306b。一旦溝槽350具有降低的第五寬度W5，形成於第一硬罩幕層306a與第二硬罩幕層306b中的溝槽352也具有降低的第六寬度W6。然後，與溝槽350原本的第四寬度W4相比，溝槽354也具有降低的第六寬度W6。因此，藉由調整塗覆層310之厚度，以控制末端對末端關鍵尺寸(end-to-end critical dimension,CD)(或第六寬度W6)。此外，藉由上述蝕刻製程(例如，第三蝕刻製程15)選擇性地移除多晶矽層304，多晶矽層304之輪廓更加垂直。
本揭露提供形成鰭式場效電晶體結構之實施例。第一鰭式結構與第二鰭式結構形成於基板上。第一電晶體形成於第一鰭式結構之上，以及第二鰭式結構形成於第二鰭式結構之上。層間介電層(ILD)結構形成於第一電晶體與第二電晶體之間。由層間介電層結構之寬度定義介於第一電晶體與第二電晶體之間的末端對末端關鍵尺寸(end-to-end critical dimension,CD)。層間介電層結構之寬度由形成於層間介電層結構之中的第一溝槽所定義，且第一溝槽間接由光阻層中的第二溝槽所定義，其中光阻層形成於硬罩幕層與鰭式結構之上。藉由形成塗覆層於第二溝槽之中，降低第二溝槽之寬度，且因此間接降低層間介電層結構之寬度。因此，可藉由調整塗覆層之厚度始末端對末端關鍵尺寸受到良好的控制。
再者，因為降低末端對末端關鍵尺寸，末端距離(end cap distance,S1)足夠形成高介電常數材料/金屬閘極電極 (HK/MG)堆疊結構。此外，可獲得閘極結構的垂直輪廓。此外，在形成塗覆層之前，對第二溝槽進行預清潔製程以移除殘餘物，並且因此避免線末端橋接問題(line-end bridge problem)。
在一些實施例中，本揭露提供一種鰭式場效電晶體裝置結構。鰭式場效電晶體包括基板以及延伸高於基板的第一鰭式結構與第二鰭式結構。鰭式場效電晶體亦包括形成於第一鰭式結構之上的第一電晶體及形成於第二鰭式結構之上的第二電晶體。鰭式場效電晶體亦包括層間介電層結構形成於第一電晶體與第二電晶體之間的一末端對末端間距(end-to-end gap)之中，且此末端對末端間距具有一寬度為約10nm至約50nm。
在一些實施例中，本揭露提供一種鰭式場效電晶體裝置結構。鰭式場效電晶體包括基板及形成於基板之上的隔離結構。鰭式場效電晶體亦包括第一鰭式結構埋設於隔離結構之中，以及第一電晶體形成於第一鰭式結構之上。鰭式場效電晶體亦包括第二電晶體形成於第一鰭式結構與隔離結構上。鰭式場效電晶體亦包括層間介電層結構形成於第一電晶體與第二電晶體之間的一末端對末端間距(end-to-end gap)之中，其中末端對末端間距具有一寬度為約10nm至約50nm。
在一些實施例中，本揭露有關於一種鰭式場效電晶體裝置結構之形成方法。此方法包括提供基板並且形成第一鰭式結構及第二鰭式結構，其中第一鰭式結構及第二鰭式結構延伸高於基板。此方法亦包括形成介電層於第一鰭式結構及第二鰭式結構之上，並且形成多晶矽層、硬罩幕層及光阻層於介 電層之上。此方法亦包括圖案化光阻層，以形成第一溝槽於光阻層之中，其中第一溝槽具有第一寬度。此方法亦包括順應性地形成塗覆層於第一溝槽之中，以形成第二溝槽於光阻層之中，其中第二溝槽具有小於第一寬度之第二寬度。此方法亦包括使用光阻層作為罩幕而圖案化硬罩幕層，並且使用此硬罩幕層作為罩幕而圖案化多晶矽層，以形成介於第一電晶體與第二電晶體之間的末端對末端間距(end-to-end gap)。此末端對末端間距具有第三寬度，且第三寬度小於第一寬度。
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以從各個方面更佳地了解本揭露。本技術領域中具有通常知識者應可理解，且可輕易地以本揭露為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本揭露的發明精神與範圍。在不背離本揭露的發明精神與範圍之前提下，可對本揭露進行各種改變、置換或修改。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧鰭式場效電晶體裝置結構
102‧‧‧基板
104‧‧‧鰭式結構
106‧‧‧閘極介電層
108‧‧‧隔離結構
110‧‧‧閘極電極
112‧‧‧通道區域
114‧‧‧源極區域
116‧‧‧汲極區域

Claims (10)

  1. 一種鰭式場效電晶體裝置結構，包括：一基板；一第一鰭式結構與一第二鰭式結構，延伸高於該基板；一第一電晶體，形成於該第一鰭式結構之上；一第二電晶體，形成於該第二鰭式結構之上；以及一層間介電層結構，形成於該第一電晶體與該第二電晶體之間的一末端對末端間距(end-to-end gap)之中，其中該末端對末端間距具有一寬度為約10nm至約50nm。
  2. 如申請專利範圍第1項所述之鰭式場效電晶體裝置結構，更包括：一隔離結構，形成於該基板之上，其中該第一鰭式結構之一上部份與該第二鰭式結構之一上部份自該隔離結構突出；其中該第一電晶體包括：一第一閘極介電層，形成於該第一鰭式結構之一頂表面與側壁上；以及一第一閘極電極，形成於該第一閘極介電層之上；其中該第二電晶體包括：一第二閘極介電層，形成於該第二鰭式結構之一頂表面與側壁上；以及一第二閘極電極，形成於該第二閘極介電層之上。
  3. 如申請專利範圍第2項所述之鰭式場效電晶體裝置結構，其中該層間介電層結構之一側壁具有一底部份與一頂部 份，該第一閘極介電層覆蓋該層間介電層結構之該側壁之該底部份，且該第一閘極電極覆蓋該層間介電層結構之該側壁之該頂部份。
  4. 一種鰭式場效電晶體裝置結構，包括：一基板；一隔離結構，形成於該基板之上；一第一鰭式結構，埋設於該隔離結構之中；一第一電晶體，形成於該第一鰭式結構之上；一第二電晶體，形成於該第一鰭式結構與該隔離結構上；以及一層間介電層結構，形成於該第一電晶體與該第二電晶體之間的一末端對末端間距(end-to-end gap)之中，其中該末端對末端間距具有一寬度為約10nm至約50nm。
  5. 如申請專利範圍第4項所述之鰭式場效電晶體裝置結構，其中該第一電晶體包括：一第一閘極介電層，形成於該第一鰭式結構之一頂表面與側壁上，其中該層間介電層結構之一側壁具有一底部份與一頂部份，該第一閘極介電層覆蓋該層間介電層結構之該側壁之該底部份，且該第一閘極電極覆蓋該層間介電層結構之該側壁之該頂部份；以及一第一閘極電極，形成於該第一閘極介電層之上；其中該第二電晶體包括：一第二閘極介電層，形成於該第二鰭式結構之一頂表面與側壁上；以及 一第二閘極電極，形成於該第二閘極介電層之上。
  6. 如申請專利範圍第4項所述之鰭式場效電晶體裝置結構，更包括：一第二鰭式結構，形成相鄰於該第一鰭式結構；一第三電晶體，形成於該隔離結構與該第二鰭式結構之上；以及該層間介電層結構形成於該第二電晶體與該第三電晶體之間的一末端對末端間距(end-to-end gap)之中，其中該末端對末端間距具有一寬度為約10nm至約50nm。
  7. 一種鰭式場效電晶體裝置結構之形成方法，包括：提供一基板；形成一第一鰭式結構及一第二鰭式結構，其中該第一鰭式結構及該第二鰭式結構延伸高於該基板；形成一介電層於該第一鰭式結構及該第二鰭式結構之上；形成一多晶矽層、一硬罩幕層及一光阻層於該介電層之上；圖案化該光阻層，以形成一第一溝槽於該光阻層之中，其中該第一溝槽具有一第一寬度；順應性地形成一塗覆層於該第一溝槽之中，以形成一第二溝槽於該光阻層之中，其中該第二溝槽具有小於該第一寬度之一第二寬度；使用該光阻層作為罩幕而圖案化該硬罩幕層；以及使用該硬罩幕層作為罩幕而圖案化該多晶矽層，以形成介於該第一電晶體與該第二電晶體之間的一末端對末端間距(end-to-end gap)，其中該末端對末端間距具有一第三寬度， 且該第三寬度小於該第一寬度。
  8. 如申請專利範圍第7項所述之鰭式場效電晶體裝置結構之形成方法，在形成該塗覆層於該第一溝槽中之前，更包括：使用一含氟氣體清潔該光阻層，其中該含氟氣體包括四氟甲烷(CF4)、六氟化硫(SF6)、三氟化氮(NF3)或上述之組合。
  9. 如申請專利範圍第7項所述之鰭式場效電晶體裝置結構之形成方法，其中形成該光阻層包括：形成一第一光阻層於該硬罩幕層之上，其中該第一光阻層是富含碳之層；以及形成一第二光阻層於該第一光阻層之上，其中該第二光阻層是富含矽之層；其中形成該硬罩幕層包括：形成一第一硬罩幕層於該多晶矽層之上；以及形成一第二硬罩幕層於該第一硬罩幕層之上。
  10. 如申請專利範圍第7項所述之鰭式場效電晶體裝置結構之形成方法，其中形成該塗覆層於該第一溝槽之中包括使用一塗覆製程，且藉由使用一含氟氣體進行該塗覆製程，其中該塗覆製程之塗覆時間為約1秒至約30秒。
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