JP5102720B2 - 基板処理方法 - Google Patents
基板処理方法 Download PDFInfo
- Publication number
- JP5102720B2 JP5102720B2 JP2008215180A JP2008215180A JP5102720B2 JP 5102720 B2 JP5102720 B2 JP 5102720B2 JP 2008215180 A JP2008215180 A JP 2008215180A JP 2008215180 A JP2008215180 A JP 2008215180A JP 5102720 B2 JP5102720 B2 JP 5102720B2
- Authority
- JP
- Japan
- Prior art keywords
- gas
- opening
- substrate processing
- processing method
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000758 substrate Substances 0.000 title claims description 82
- 238000003672 processing method Methods 0.000 title claims description 47
- 238000005530 etching Methods 0.000 claims description 68
- 238000000034 method Methods 0.000 claims description 51
- 230000008021 deposition Effects 0.000 claims description 30
- 239000000203 mixture Substances 0.000 claims 3
- 239000007789 gas Substances 0.000 description 142
- 229920002120 photoresistant polymer Polymers 0.000 description 47
- 235000012431 wafers Nutrition 0.000 description 42
- 229910052581 Si3N4 Inorganic materials 0.000 description 33
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 33
- 238000000151 deposition Methods 0.000 description 29
- 230000000694 effects Effects 0.000 description 17
- 239000004065 semiconductor Substances 0.000 description 16
- 230000006870 function Effects 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 7
- 238000003860 storage Methods 0.000 description 6
- 238000004380 ashing Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000009832 plasma treatment Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 238000009499 grossing Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 238000005299 abrasion Methods 0.000 description 1
- 230000003044 adaptive effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000002952 polymeric resin Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- 230000002195 synergetic effect Effects 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
Description
請求項7記載の基板処理方法は、請求項1乃至6の何れか1項に記載の基板処理方法において、前記シュリンクエッチングステップの後に、前記デポ性ガス、SF 6 ガス、Arガス及びN 2 ガスの混合ガスから生成されたプラズマ又は前記デポ性ガス、Arガス及びN 2 ガスの混合ガスから生成されたプラズマによって、前記マスク層及び前記中間層の開口幅を縮小させつつ、前記処理対象層をエッチングする処理対象層エッチングステップを有することを特徴とする。
請求項8記載の基板処理方法は、請求項7記載の基板処理方法において、前記デポ性ガス、SF 6 ガス、Arガス及びN 2 ガスの混合ガスの流量比は、1:2:6:2であることを特徴とする。
請求項9記載の基板処理方法は、請求項7記載の基板処理方法において、前記デポ性ガス、Arガス及びN 2 ガスの混合ガスの流量比は、1:6:2であることを特徴とする。
請求項10記載の基板処理方法は、請求項1乃至9の何れか1項に記載の基板処理方法において、前記処理対象層は、SiN膜であることを特徴とする。
置されたオペレーションパネル42を備える。オペレーションパネル42は、例えばLCD(Liquid Crystal Display)からなる表示部を有し、該表示部は基板処理システム10の各構成要素の動作状況を表示する。
12,13,14 プロセスモジュール
50 シリコン基材
51 SiN膜
52 反射防止膜(BARC膜)
53 フォトレジスト膜
54 開口部
55 デポ
Claims (10)
- 処理対象層、中間層及びマスク層が順に積層され、前記マスク層は前記中間層の一部を露出させる開口部を有する基板を処理する基板処理方法であって、
一般式CxHyFz(x、y、zは、正の整数)で表わされるデポ性ガス及びSF6ガスを、混合比が1:4〜1:9となるように混合した混合ガスから生成されたプラズマによって前記マスク層の前記開口部の側壁面にデポを堆積させて前記開口部の開口幅を縮小させると共に、前記中間層をエッチングして前記縮小したマスク層の開口部に対応する開口部を形成するシュリンクエッチングステップを有することを特徴とする基板処理方法。 - 前記デポ性ガスは、CH3Fガスであることを特徴とする請求項1記載の基板処理方法。
- 前記シュリンクエッチングステップにおいて、前記基板に50W乃至150Wのバイアス電力を印加させることを特徴とする請求項1又は2記載の基板処理方法。
- 前記シュリンクエッチングステップにおける処理時間は、1分乃至2分であることを特徴とする請求項1乃至3のいずれか1項に記載の基板処理方法。
- 前記シュリンクエッチングステップにおいて、前記基板を収容するチャンバ内圧力を1.3Pa(10mTorr)乃至6.5Pa(50mTorr)に調整することを特徴とする請求項1乃至4のいずれか1項に記載の基板処理方法。
- 前記シュリンクエッチングステップにおいて、エッチングされる前記中間層は、前記マスク層の下方に積層された反射防止膜であることを特徴とする請求項1乃至5のいずれか1項に記載の基板処理方法。
- 前記シュリンクエッチングステップの後に、前記デポ性ガス、SF 6 ガス、Arガス及びN 2 ガスの混合ガスから生成されたプラズマ又は前記デポ性ガス、Arガス及びN 2 ガスの混合ガスから生成されたプラズマによって、前記マスク層及び前記中間層の開口幅を縮小させつつ、前記処理対象層をエッチングする処理対象層エッチングステップを有することを特徴とする請求項1乃至6の何れか1項に記載の基板処理方法。
- 前記デポ性ガス、SF 6 ガス、Arガス及びN 2 ガスの混合ガスの流量比は、1:2:6:2であることを特徴とする請求項7記載の基板処理方法。
- 前記デポ性ガス、Arガス及びN 2 ガスの混合ガスの流量比は、1:6:2であることを特徴とする請求項7記載の基板処理方法。
- 前記処理対象層は、SiN膜であることを特徴とする請求項1乃至9の何れか1項に記載の基板処理方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008215180A JP5102720B2 (ja) | 2008-08-25 | 2008-08-25 | 基板処理方法 |
KR1020090077488A KR101534350B1 (ko) | 2008-08-25 | 2009-08-21 | 기판 처리 방법 |
US12/545,144 US8329050B2 (en) | 2008-08-25 | 2009-08-21 | Substrate processing method |
TW098128381A TWI482217B (zh) | 2008-08-25 | 2009-08-24 | Substrate handling method |
CN200910168595.0A CN101661228B (zh) | 2008-08-25 | 2009-08-25 | 基板处理方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008215180A JP5102720B2 (ja) | 2008-08-25 | 2008-08-25 | 基板処理方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010050376A JP2010050376A (ja) | 2010-03-04 |
JP5102720B2 true JP5102720B2 (ja) | 2012-12-19 |
Family
ID=41696786
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008215180A Expired - Fee Related JP5102720B2 (ja) | 2008-08-25 | 2008-08-25 | 基板処理方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8329050B2 (ja) |
JP (1) | JP5102720B2 (ja) |
KR (1) | KR101534350B1 (ja) |
CN (1) | CN101661228B (ja) |
TW (1) | TWI482217B (ja) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5107842B2 (ja) * | 2008-09-12 | 2012-12-26 | 東京エレクトロン株式会社 | 基板処理方法 |
JP5180121B2 (ja) * | 2009-02-20 | 2013-04-10 | 東京エレクトロン株式会社 | 基板処理方法 |
CN103400799B (zh) * | 2013-08-14 | 2016-03-30 | 上海华力微电子有限公司 | 接触孔的刻蚀方法 |
KR101623654B1 (ko) * | 2014-11-25 | 2016-05-23 | 아주대학교산학협력단 | 플라즈마 가스를 사용한 실리콘 기판 식각방법 |
US9508719B2 (en) * | 2014-11-26 | 2016-11-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin field effect transistor (FinFET) device with controlled end-to-end critical dimension and method for forming the same |
JP6919975B2 (ja) | 2017-04-14 | 2021-08-18 | キャタピラー エス エー アール エル | 作業機械のキャブ抜止構造 |
JP6925202B2 (ja) * | 2017-08-30 | 2021-08-25 | 東京エレクトロン株式会社 | エッチング方法およびエッチング装置 |
US10727045B2 (en) * | 2017-09-29 | 2020-07-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for manufacturing a semiconductor device |
CN110119072B (zh) * | 2018-02-06 | 2021-05-14 | 志圣科技(广州)有限公司 | 曝光组件及曝光装置 |
US10741452B2 (en) * | 2018-10-29 | 2020-08-11 | International Business Machines Corporation | Controlling fin hardmask cut profile using a sacrificial epitaxial structure |
US20210125875A1 (en) * | 2019-10-29 | 2021-04-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method |
US11264287B2 (en) * | 2020-02-11 | 2022-03-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with cut metal gate and method of manufacture |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4707218A (en) * | 1986-10-28 | 1987-11-17 | International Business Machines Corporation | Lithographic image size reduction |
JPH0212915A (ja) * | 1988-06-30 | 1990-01-17 | Sharp Corp | 窒化珪素絶縁膜の加工方法 |
DE4317623C2 (de) * | 1993-05-27 | 2003-08-21 | Bosch Gmbh Robert | Verfahren und Vorrichtung zum anisotropen Plasmaätzen von Substraten und dessen Verwendung |
JP3672900B2 (ja) | 2002-09-11 | 2005-07-20 | 松下電器産業株式会社 | パターン形成方法 |
JP4455936B2 (ja) * | 2003-07-09 | 2010-04-21 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置の製造方法とエッチングシステム |
KR100632658B1 (ko) | 2004-12-29 | 2006-10-12 | 주식회사 하이닉스반도체 | 반도체 소자의 금속배선 형성방법 |
JP2006203035A (ja) * | 2005-01-21 | 2006-08-03 | Tokyo Electron Ltd | プラズマエッチング方法 |
JP2005210134A (ja) * | 2005-02-14 | 2005-08-04 | Matsushita Electric Ind Co Ltd | パターン形成方法 |
JP4640006B2 (ja) * | 2005-07-13 | 2011-03-02 | パナソニック株式会社 | プラズマディスプレイパネルの製造方法 |
US7323410B2 (en) * | 2005-08-08 | 2008-01-29 | International Business Machines Corporation | Dry etchback of interconnect contacts |
US7531461B2 (en) * | 2005-09-14 | 2009-05-12 | Tokyo Electron Limited | Process and system for etching doped silicon using SF6-based chemistry |
JP2007194284A (ja) * | 2006-01-17 | 2007-08-02 | Tokyo Electron Ltd | プラズマ処理方法、プラズマ処理装置、及び記憶媒体 |
-
2008
- 2008-08-25 JP JP2008215180A patent/JP5102720B2/ja not_active Expired - Fee Related
-
2009
- 2009-08-21 US US12/545,144 patent/US8329050B2/en active Active
- 2009-08-21 KR KR1020090077488A patent/KR101534350B1/ko active IP Right Grant
- 2009-08-24 TW TW098128381A patent/TWI482217B/zh active
- 2009-08-25 CN CN200910168595.0A patent/CN101661228B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
US8329050B2 (en) | 2012-12-11 |
CN101661228B (zh) | 2014-05-14 |
TW201025440A (en) | 2010-07-01 |
TWI482217B (zh) | 2015-04-21 |
US20100048026A1 (en) | 2010-02-25 |
KR20100024356A (ko) | 2010-03-05 |
JP2010050376A (ja) | 2010-03-04 |
CN101661228A (zh) | 2010-03-03 |
KR101534350B1 (ko) | 2015-07-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5102720B2 (ja) | 基板処理方法 | |
KR101549264B1 (ko) | 기판 처리 방법 | |
JP5180121B2 (ja) | 基板処理方法 | |
JP5248902B2 (ja) | 基板処理方法 | |
JP2010283213A (ja) | 基板処理方法 | |
JP5524362B2 (ja) | 基板処理方法 | |
JP5604063B2 (ja) | 基板処理方法及び記憶媒体 | |
JP5107842B2 (ja) | 基板処理方法 | |
KR101699547B1 (ko) | 기판 처리 방법 및 기억 매체 | |
JP5484363B2 (ja) | 基板処理方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20110822 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120515 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120522 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120719 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120925 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120928 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20151005 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5102720 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |