CN105633083B - 具有可控端到端临界尺寸的鳍式场效应晶体管(FinFET)器件及其形成方法 - Google Patents

具有可控端到端临界尺寸的鳍式场效应晶体管(FinFET)器件及其形成方法 Download PDF

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CN105633083B
CN105633083B CN201510437327.XA CN201510437327A CN105633083B CN 105633083 B CN105633083 B CN 105633083B CN 201510437327 A CN201510437327 A CN 201510437327A CN 105633083 B CN105633083 B CN 105633083B
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layer
forming
fin
width
finfet
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CN105633083A (zh
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陈建颖
程潼文
张哲诚
倪俊龙
林志忠
林志翰
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了鳍式场效应晶体管(FinFET)器件结构以及用于形成FinFET器件结构的方法。FinFET器件结构包括衬底以及在衬底之上延伸的第一鳍结构和第二鳍结构。FinFET器件结构也包括形成在第一鳍结构上的第一晶体管和形成在第二鳍结构上的第二晶体管。FinFET器件结构还包括在第一晶体管和第二晶体管之间的端到端间隙中形成的层间介电(ILD)结构，并且端到端间隙具有在从约20nm至约40nm的范围内的宽度。本发明的实施例还涉及具有可控端到端临界尺寸的鳍式场效应晶体管(FinFET)器件及其形成方法。

Description

具有可控端到端临界尺寸的鳍式场效应晶体管(FinFET)器件 及其形成方法
技术领域
本发明的实施例涉及集成电路，更具体地，涉及具有可控端到端临界尺寸的鳍式场效应晶体管(FinFET)器件及其形成方法。
背景技术
半导体器件用于各种电子应用中，诸如个人计算机、手机、数码相机和其他电子设备。通常通过在半导体衬底上方依次沉积绝缘或介电层、导电层和半导体材料层以及使用光刻图案化各个材料层以在材料层上形成电路组件和元件来制造半导体器件。在单个半导体晶圆上通常制造许多集成电路，并且通过沿着划线在集成电路之间锯切来分割晶圆上的单独的管芯。
随着半导体工业已经进入到纳米技术工艺节点以追求更高的器件密度、更高的性能和更低的成本，来自制造和设计问题的挑战已经导致了诸如鳍式场效应晶体管(FinFET)的三维设计的发展。FinFET制造为具有从衬底延伸的薄垂直“鳍”(或鳍结构)。在该垂直鳍中形成FinFET的沟道。在鳍上方提供栅极。FinFET的优势可以包括减少短沟道效应以及更高的电流。
虽然现有的FinFET器件和制造FinFET器件的方法对于它们的预期目的通常已经足够，但是它们不是在所有方面都已完全令人满意。
发明内容
本发明的实施例提供了一种鳍式场效应晶体管(FinFET)器件结构，包括：衬底；第一鳍结构和第二鳍结构，在所述衬底之上延伸；第一晶体管，形成在所述第一鳍结构上；第二晶体管，形成在所述第二鳍结构上；以及层间介电(ILD)结构，形成在所述第一晶体管和所述第二晶体管之间的端到端间隙中，其中，所述端到端间隙具有在从约10nm至约50nm的范围内的宽度。
本发明的另一实施例提供了一种鳍式场效应晶体管(FinFET)器件结构，包括：衬底；隔离结构，形成在所述衬底上；第一鳍结构，嵌入在所述隔离结构中；第一晶体管，形成在所述第一鳍结构上；第二晶体管，形成在所述第一鳍结构和所述隔离结构上；层间介电(ILD)结构，形成在所述第一晶体管和所述第二晶体管之间的端到端间隙中，其中，所述端到端间隙具有在从约10nm至约50nm的范围内的宽度。
本发明的又一实施例提供了一种用于形成鳍式场效应晶体管(FinFET) 器件结构的方法，包括：提供衬底；形成第一鳍结构和第二鳍结构，所述第一鳍结构和所述第二鳍结构在所述衬底之上延伸；在所述第一鳍结构和所述第二鳍结构上形成介电层；在所述介电层上形成多晶硅层、硬掩模层和光刻胶层；图案化所述光刻胶层以在所述光刻胶层中形成第一沟槽，其中，所述第一沟槽具有第一宽度；在所述第一沟槽中共形地形成涂层以在所述光刻胶层中形成第二沟槽，其中，所述第二沟槽具有第二宽度，并且所述第二宽度小于所述第一宽度；通过将所述光刻胶层用作掩模来图案化所述硬掩模层；通过将所述硬掩模层用作掩模来图案化所述多晶硅层以在所述第一鳍结构和所述第二鳍结构之间形成端到端间隙，其中，所述端到端间隙具有第三宽度，并且所述第三宽度小于所述第一宽度。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1示出了根据本发明的一些实施例的鳍式场效应晶体管(FinFET) 器件结构的立体图示。
图2示出了根据本发明的一些实施例的鳍式场效应晶体管(FinFET) 器件结构的顶视图。
图3A至图3I示出了根据本发明的一些实施例的形成鳍式场效应晶体管(FinFET)器件结构的各个阶段的截面图示。
图4A至图4G示出了根据本发明的一些实施例的形成鳍式场效应晶体管(FinFET)器件结构的各个阶段的截面图示。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
描述了实施例的一些变化。贯穿各个视图和说明性实施例，相同的参考标号用于表示相同的元件。应该理解，可以在方法之前、期间和之后提供额外的操作，并且对于方法的其他实施例，可以代替或消除描述的一些操作。
提供了用于形成鳍式场效应晶体管(FinFET)器件结构的实施例。图 1示出了根据本发明的一些实施例的鳍式场效应晶体管(FinFET)器件结构100的立体图示。
FinFET器件结构100包括衬底102。衬底102可以由硅或其他半导体材料制成。可选地或额外地，衬底102可以包括诸如锗的其他元素半导体材料。在一些实施例中，衬底102由诸如碳化硅、砷化镓、砷化铟或磷化铟的化合物半导体制成。在一些实施例中，衬底102由诸如硅锗、碳化硅锗、磷砷化镓或磷化镓铟的合金半导体制成。在一些实施例中，衬底102 包括外延层。例如，衬底102具有位于块状半导体上面的外延层。
FinFET器件结构100也包括从衬底102延伸的一个或多个鳍结构104 (例如，Si鳍)。鳍结构104可以可选择地包括锗。可以通过使用诸如光刻和蚀刻工艺的合适的工艺形成鳍结构104。在一些实施例中，使用干蚀刻或等离子体工艺从衬底102蚀刻鳍结构104。
形成诸如浅沟槽隔离(STI)结构的隔离结构108以围绕鳍结构104。如图1所示，在一些实施例中，隔离结构108围绕鳍结构104的下部，并且鳍结构104的上部从隔离结构108突出。换句话说，鳍结构104的部分嵌入隔离结构108中。隔离结构108防止电干扰或串扰。
FinFET器件结构100还包括栅极堆叠结构，栅极堆叠结构包括栅电极 110和栅极介电层106。栅极堆叠结构形成在鳍结构104的中心部分上方。在一些实施例中，在鳍结构104上方形成多个栅极堆叠结构。在栅极结构中也可以存在许多其他层，例如，覆盖层、界面层、间隔件元件和/或其他合适的部件。
栅极介电层106可以包括诸如氧化硅、氮化硅、氮氧化硅的介电材料、具有高介电常数(高k)的介电材料或它们的组合。高k介电材料的实例包括氧化铪、氧化锆、氧化铝、二氧化铪-氧化铝合金、氧化铪硅、氮氧化铪硅、氧化铪钽、氧化铪钛、氧化铪锆等或它们的组合。
栅电极110可以包括多晶硅或金属。金属包括氮化钽(TaN)、硅化镍(NiSi)、硅化钴(CoSi)、钼(Mo)、铜(Cu)、钨(W)、铝(Al)、钴(Co)、锆(Zr)、铂(Pt)或其他适用的材料。可以以后栅极工艺(或栅极替换工艺)形成栅电极110。在一些实施例中，栅极堆叠结构包括诸如界面层、覆盖层、扩散/阻挡层或其他适用的层的额外的层。
鳍结构104包括由栅电极110和栅极介电层106围绕或包裹的沟道区 112。可以掺杂鳍结构104以提供用于n型FinFET(NMOS器件)或p型FinFET(PMOS器件)的合适的沟道。可以使用诸如离子注入工艺、扩散工艺、退火工艺、其他适用的工艺或它们的组合的合适的工艺掺杂鳍结构 104。鳍结构104包括源极区114和漏极区116，沟道区112位于源极区114 和漏极区116之间。FinFET器件100可以是包括在微处理器、存储器单元 (例如，静态随机存取存储器(SRAM))和/或其他集成电路中的器件。
图2示出了根据本发明的一些实施例的鳍式场效应晶体管(FinFET) 器件结构100的顶视图。FinFET器件结构100包括多个鳍结构104和多个栅电极110。栅电极110横越在鳍结构104上方。隔离结构108围绕FinFET器件结构100。
如图2所示，鳍结构104可以基本上彼此平行。栅电极110也可以彼此平行并且基本上垂直于鳍结构104。在一些实施例中，当从顶视图看时，栅电极110也称为栅电极线。
在第一鳍结构104a上形成第一晶体管300a，并且在第二鳍结构104b 上形成第二晶体管300b。在一些实施例中，第一晶体管300a和第二晶体管 300b之间的第三宽度(W3)在从约10nm至约50nm的范围内。
图3A至图3I示出了根据本发明的一些实施例的形成鳍式场效应晶体管(FinFET)器件结构100的各个阶段的截面图示。图3A至图3I是沿着图2的线AA’截取的截面图示。
参照图3A，在衬底102上方形成第一鳍结构104a和第二鳍结构104b。在一些实施例中，通过在衬底102上沉积和图案化硬掩模层(未示出)来蚀刻衬底102以形成第一鳍结构104a和第二鳍结构104b。硬掩模层形成覆盖部分衬底102的图案。然后，蚀刻衬底102以在由硬掩模层覆盖的区域之间形成沟槽。结果，第一鳍结构104a和第二鳍结构104b形成在沟槽之间。
然后，在沟槽内沉积介电材料(例如，氧化硅)，从而覆盖第一鳍结构104a和第二鳍结构104b。向下平坦化介电材料至第一鳍结构104a和第二鳍结构104b的顶面或硬掩模层的顶面，以及然后蚀刻介电材料至位于第一鳍结构104a和第二鳍结构104b的顶面下方的水平面处。结果，第一鳍结构104a和第二鳍结构104b的上部突出于隔离结构108之上，并且第一鳍结构104a和第二鳍结构104b的下部由隔离结构108围绕和覆盖。
可选地，在一些其他实施例中，首先在衬底102上方形成隔离结构108。在隔离结构108之间形成沟槽以暴露衬底102。然后，例如通过使用外延工艺在沟槽中生长诸如硅、硅锗或其他适用的材料的半导体材料以形成第一鳍结构104a和第二鳍结构104b。在第一鳍结构104a和第二鳍结构104b 生长至期望的高度之后，向下蚀刻隔离结构108至位于第一鳍结构104a和第二鳍结构104b的顶面下方的水平面处。结果，第一鳍结构104a和第二鳍结构104b的部分突出于隔离结构108之上。
如图3A所示，在第一鳍结构104a、第二鳍结构104b和隔离结构108 上依次形成介电层302和多晶硅层304。然后，在多晶硅层304上方形成第一硬掩模层306a和第二硬掩模层306b。第一硬掩模层306a可以由氧化硅、氮化硅、氮氧化硅或其他适用的材料制成。第二硬掩模层306b可以由氧化硅、氮化硅、氮氧化硅或其他适用的材料制成。通过图案化工艺形成第一硬掩模层306a和第二硬掩模层306b。图案化工艺包括光刻工艺和蚀刻工艺。光刻工艺包括光刻胶涂布(例如，旋涂)、软烘烤、掩模对准、曝光、曝光后烘烤、显影光刻胶、冲洗和干燥(例如，硬烘烤)。蚀刻工艺包括干蚀刻工艺或湿蚀刻工艺。
如图3B所示，根据本发明的一些实施例，在形成第一硬掩模层306a 和第二硬掩模层306b之后，在第二硬掩模层306b上形成第一光刻胶层308a 和第二光刻胶层308b。
在一些实施例中，第一光刻胶层308a是诸如碳化硅(SiC或SixC)的富碳层。在一些实施例中，第二光刻胶层308b是诸如氧化硅(SiOx)、氮化硅(SixNy)或氮氧化硅(SiON)的富硅层。
然后，图案化第一光刻胶层308a和第二光刻胶层308b以在第一光刻胶层308a和第二光刻胶层308b中形成沟槽350。沟槽具有第一宽度W1。在一些实施例中，第一宽度W1在从约40nm至约80nm的范围内。
如图3C所示，根据本发明的一些实施例，在形成沟槽350之后，在沟槽350中和在第二光刻胶层308b上共形地形成涂层310。涂层310是含氟聚合物。涂层310配置为减小沟槽350的宽度。在形成涂层310之后，沟槽350具有减小的第二宽度W2。因此，第二宽度W2小于第二宽度W1。
通过使用涂布气体的涂布工艺形成涂层310。在一些实施例中，涂布工艺是等离子体工艺。涂布气体包括诸如四氟甲烷(CF4)、二氟甲烷(CH2F2)、六氟化硫(SF6)、三氟化氮(NF3)、其他适用的气体或它们的组合的含氟气体。涂布气体的流量在从约0.1sccm至约100sccm的范围内。在等离子体工艺中使用的偏压在从0V至100V的范围内。在等离子体工艺中使用的功率在从约500瓦至约1500瓦的范围内。
涂层310的涂布厚度取决于涂布时间。涂布时间在从约1秒至约50秒的范围内。如果涂布时间太长，则涂层310可能完全地填充沟槽350，并且因此不能使用沟槽350的图案图案化下面的层。如果涂布时间太短，则涂层310太薄而不能减小沟槽350的尺寸。
应该注意，为了防止一些不想要的残留物(来自光刻胶层308a或308b) 保留在沟槽350中，在形成涂层310之前，对沟槽350实施预清洗工艺。当清洗沟槽350时，避免了可能由形成在沟槽350中的残留物导致的线端桥接问题。
通过使用含氟气体实施预清洗工艺。含氟气体包括四氟甲烷(CF4)、六氟化硫(SF6)、三氟化氮(NF3)、其他适用的气体或它们的组合。在一些实施例中，实施预清洗工艺的持续时间在从约1s至约20s的范围内。
如图3D所示，根据本发明的一些实施例，在沟槽350中形成涂层310 之后，实施第一蚀刻工艺11以去除涂层310的位于第二光刻胶层308b上的部分。在一些实施例中，第一蚀刻工艺11是干蚀刻工艺。
应该注意，去除涂层310的位于第二光刻胶层308b上的部分，但是保留涂层310的形成在沟槽350的侧壁和底部上的部分。剩余的涂层310用于使沟槽350的宽度变窄。稍微蚀刻位于沟槽350的侧壁上的剩余的涂层 310的顶部。因此，涂层310的顶面不平行于第二光刻胶层308b的顶面。
然后，如图3E所示，根据本发明的一些实施例，实施第二蚀刻工艺 13以去除涂层310的部分和第二光刻胶层308b。在一些实施例中，第二蚀刻工艺13也是干蚀刻工艺。
如图3F所示，根据本发明的一些实施例，在第二蚀刻工艺13之后，实施第三蚀刻工艺15以去除涂层310、第一光刻胶层308a、部分第一硬掩模层306a和部分第二硬掩模层306b。在一些实施例中，第三蚀刻工艺15 是干蚀刻工艺。
应该注意，通过第三蚀刻工艺15选择性地蚀刻沟槽350的底部。此外，然后蚀刻第二硬掩模层306b的直接位于涂层310下方的部分以暴露部分第一硬掩模层306a。然后，去除暴露的第一硬掩模层306a。第一硬掩模层306a 是蚀刻停止层。
结果，如图3F所示，图案化第一硬掩模层306a和第二硬掩模层306b 以形成沟槽352。沟槽352具有第三宽度W3。第三宽度W3稍微大于第二宽度W2，并且第三宽度W3仍小于第一宽度W1。在一些实施例中，第三宽度W3在从约10nm至约50nm的范围内。
如图3G所示，根据本发明的一些实施例，在形成沟槽352之后，通过将第一硬掩模层306a和第二硬掩模层306b用作掩模来图案化介电层302 和多晶硅层304。结果，在多晶硅层304中形成沟槽354。换句话说，沟槽 354称为端到端间隙。
然后，如图3H所示，根据本发明的一些实施例，去除作为掩模的位于多晶硅层304上的第一硬掩模层306a和第二硬掩模层306b，并且在沟槽 354(或所谓的端到端间隙)内填充介电材料。
在填充介电材料之后，通过诸如化学机械抛光工艺(CMP)的平坦化工艺去除介电材料的位于沟槽354外部的部分。结果，形成层间介电(ILD) 结构320。
然后，如图3I所示，根据本发明的一些实施例，去除多晶硅层304和介电层302，并且在鳍结构104上形成栅极介电层106和栅电极110。在一些实施例中，栅极介电层106是高介电常数(高k)介电层，并且栅电极 110是金属栅电极。换句话说，在鳍结构104上形成HK/MG堆叠结构。
金属栅电极包括n型功函金属或p型功函金属。n型功函金属包括钨 (W)、铜(Cu)、钛(Ti)、银(Ag)、铝(Al)、钛铝合金(TiAl)、氮化钛铝(TiAlN)、碳化钽(TaC)、碳氮化钽(TaCN)、氮化钽硅(TaSiN)、锰(Mn)或锆(Zr)。P型功函金属包括氮化钛(TiN)、氮化钨(WN)、氮化钽(TaN)或钌(Ru)。通过物理汽相沉积(PVD)工艺、化学汽相沉积(CVD)工艺、镀工艺、化学镀工艺或其他适用的工艺形成金属栅极。
在ILD结构320的左侧上，第一晶体管300a由栅极介电层106、栅电极110和源极/漏极(未示出)构成。在ILD结构320的右侧上，第二晶体管300b由栅极介电层106、栅电极110和另一源极/漏极(未示出)构成。第一晶体管300a和第二晶体管300b位于ILD结构320的相对侧壁上。在一些实施例中，第一晶体管300a是n型金属氧化物半导体场效应晶体管(NMOSFET)，并且第二晶体管300b是p型金属氧化物半导体场效应晶体管(PMOSFET)。
如图3I所示，ILD结构320的侧壁具有底部和顶部，栅极介电层106 覆盖ILD结构320的侧壁的底部，并且栅电极110覆盖ILD结构320的侧壁的顶部。
在一些实施例中，ILD结构320具有在从约20nm至约40nm的范围内的第三宽度W3。换句话说，第一晶体管300a和第二晶体管300b之间的端到端临界尺寸(CD)由第三宽度W3限定。
在一些实施例中，ILD结构320的侧壁和第一鳍结构104a的侧壁之间的端盖距离(S1)在从约0.01nm至约50nm的范围内。
应该注意，随着鳍式场效应晶体管(FinFET)器件结构100的尺寸减小，控制端到端临界尺寸(CD)变得更加困难。因此，本发明使用涂层来控制端到端临界尺寸(CD)。
涂层310用于将沟槽350的宽度从第一宽度W1减小到第二宽度W2。通过使用较小的第二宽度W2，在多晶硅层304中获得具有第三宽度W3的沟槽354，第三宽度W3小于第一宽度W1。因此，实现了较小的端到端临界尺寸(CD)(诸如图3H中的第三宽度W3)。此外，多晶硅层304的轮廓更加垂直。
此外，当端到端临界尺寸(CD)(诸如图3H中的第三宽度W3)更小时，端盖距离(S1)变得更大。更大的端盖距离(S1)有益于形成HK/MG 堆叠结构。
图4A至图4G示出了根据本发明的一些实施例的形成鳍式场效应晶体管(FinFET)器件结构100的各个阶段的截面图示。图4A至图4G是沿着图2的线BB’截取的截面图示。
参照图4A，在衬底102上形成鳍结构104和隔离结构108。鳍结构104 的部分突出于隔离结构108之上。在鳍结构104和隔离结构108上依次形成介电层302和多晶硅层304。然后，在多晶硅层304上方形成第一硬掩模层306a和第二硬掩模层306b。
如图4B所示，根据本发明的一些实施例，在形成第二硬掩模层306b 之后，在第二硬掩模层306b上形成光刻胶层308。光刻胶层308是单个层或多个层。
然后，图案化光刻胶层308以在光刻胶层308中形成沟槽350。可以形成一个或多个沟槽350。可以根据实际应用调整沟槽350的数量。沟槽 350具有第四宽度W4。在一些实施例中，第四宽度W4在从约40nm至约 80nm的范围内。
如图4C所示，根据本发明的一些实施例，在光刻胶层308中形成沟槽 350之后，在沟槽350中和在光刻胶层308上共形地形成涂层310。
涂层310是含氟聚合物。涂层310配置为减小沟槽350的宽度。在形成涂层310之后，沟槽350具有减小的第五宽度W5。因此，第五宽度W5小于第四宽度W4。
在一些实施例中，通过使用涂布气体的等离子体工艺形成涂层310。涂布气体包括诸如四氟甲烷(CF4)、二氟甲烷(CH2F2)、六氟化硫(SF6)、三氟化氮(NF3)、其他适用的气体或它们的组合的含氟气体。
如图4D所示，根据本发明的一些实施例，在形成涂层310之后，通过多个蚀刻工艺蚀刻光刻胶层308、涂层310、部分第一硬掩模层306a和部分第二硬掩模层306b。结果，在第一硬掩模层306a和第二硬掩模层306b 中形成一个或多个沟槽352。沟槽352具有第六宽度W6，第六宽度W6稍微大于第五宽度W5。
然后，如图4E所示，根据本发明的一些实施例，通过将第一硬掩模层 306a和第二硬掩模层306b用作掩模来图案化介电层302和多晶硅层304。结果，在多晶硅层304中形成沟槽354(或称为端到端间隙)。
然后，如图4F所示，根据本发明的一些实施例，去除作为掩模的位于多晶硅层304上的第一硬掩模层306a和第二硬掩模层306b，并且在沟槽 354内填充介电材料。
在填充沟槽354之后，通过诸如化学机械抛光工艺(CMP)的平坦化工艺去除位于沟槽354外部的过量的介电材料的部分。结果，形成层间介电(ILD)结构320。
然后，如图4G所示，根据本发明的一些实施例，去除多晶硅层304 和介电层302，并且在鳍结构104上形成栅极介电层106和栅电极110。在一些实施例中，栅极介电层106是高介电常数(高k)介电层，并且栅电极110是金属栅电极。换句话说，在鳍结构104上形成HK/MG堆叠结构。
如图4G所示，栅极介电层106和栅电极110分成四个部分，并且分别形成第一晶体管400a、第二晶体管400b、第三晶体管400c和第四晶体管 400d。第一晶体管400a由栅极介电层106和栅电极110构成，并且第二晶体管400b由栅极介电层106和栅电极110构成。
ILD结构320位于第一晶体管400a和第二晶体管400b之间。此外，ILD 结构320位于第三晶体管400c和第四晶体管400d之间。
在一些实施例中，第一晶体管400a和第二晶体管400b之间的第六宽度(W6)在从约10nm至约50nm的范围内。换句话说，两个晶体管之间的端到端临界尺寸(CD)由第六宽度W6限定。
应该注意，图案化的光刻胶层308具有宽度为第四宽度W4的沟槽350，并且在沟槽350中形成涂层310之后，沟槽350具有减小的第五宽度W5。图案化的光刻胶层308用于图案化下面的第一硬掩模层306a和第二硬掩模层306b。一旦沟槽350具有减小的第五宽度W5，在第一硬掩模层306a和第二硬掩模层306b中形成的沟槽352也具有减小的第六宽度W6。然后，与沟槽350的原始的第四宽度W4相比，沟槽354也具有减小的第六宽度 W6。因此，通过调整涂层310的厚度控制端到端临界尺寸(CD)(或第六宽度W6)。此外，由于通过上述蚀刻工艺(诸如第三蚀刻工艺15)选择性地蚀刻多晶硅层304，多晶硅层304的轮廓更加垂直。
提供了用于形成鳍式场效应晶体管(FinFET)器件结构的实施例。在衬底上形成第一鳍结构和第二鳍结构。在第一鳍结构上形成第一晶体管，并且在第二鳍结构上形成第二晶体管。在第一晶体管和第二晶体管之间形成层间介电(ILD)结构。第一晶体管和第二晶体管之间的端到端临界尺寸 (CD)由ILD结构的宽度限定。ILD结构的宽度由在ILD结构中形成的第一沟槽限定，并且第一沟槽由光刻胶层中的第二沟槽间接限定，光刻胶层形成在硬掩模层和鳍结构上。通过在第二沟槽中形成涂层，第二沟槽的宽度减小，并且因此ILD结构的宽度间接地减小。因此，通过调整涂层的涂布厚度良好地控制端到端临界尺寸(CD)。
此外，由于端到端临界尺寸减小，端盖距离足够大以形成HK/MG结构。此外，获得栅极结构的垂直轮廓。此外，在形成涂层之前，对第二沟槽实施预清洗工艺以去除残留物，并且因此避免了线端桥接问题。
在一些实施例中，提供了一种鳍式场效应晶体管(FinFET)器件结构。FinFET器件结构包括衬底以及在衬底之上延伸的第一鳍结构和第二鳍结构。FinFET器件结构也包括形成在第一鳍结构上的第一晶体管和形成在第二鳍结构上的第二晶体管。FinFET器件结构还包括在第一晶体管和第二晶体管之间的端到端间隙中形成的层间介电(ILD)结构，并且端到端间隙具有在从约10nm至约50nm的范围内的宽度。
在上述FinFET器件结构中，其中，所述第一晶体管是n型金属氧化物半导体场效应晶体管(NMOSFET)，并且所述第二晶体管是p型金属氧化物半导体场效应晶体管(PMOSFET)。
在上述FinFET器件结构中，还包括：隔离结构，形成在所述衬底上，其中，所述第一鳍结构的上部和所述第二鳍结构的上部从所述隔离结构突出。
在上述FinFET器件结构中，其中，所述第一晶体管包括：第一栅极介电层，形成在所述第一鳍结构的顶面和侧壁上；和第一栅电极，形成在所述第一栅极介电层上；以及其中，所述第二晶体管包括：第二栅极介电层，形成在所述第二鳍结构的顶面和侧壁上；和第二栅电极，形成在所述第二栅极介电层上。
在上述FinFET器件结构中，其中，所述第一晶体管包括：第一栅极介电层，形成在所述第一鳍结构的顶面和侧壁上；和第一栅电极，形成在所述第一栅极介电层上；以及其中，所述第二晶体管包括：第二栅极介电层，形成在所述第二鳍结构的顶面和侧壁上；和第二栅电极，形成在所述第二栅极介电层上，其中，所述ILD结构的侧壁具有底部和顶部，所述第一栅极介电层覆盖所述ILD结构的侧壁的所述底部，并且所述第一栅电极覆盖所述ILD结构的侧壁的所述顶部。
在上述FinFET器件结构中，其中，所述第一晶体管包括：第一栅极介电层，形成在所述第一鳍结构的顶面和侧壁上；和第一栅电极，形成在所述第一栅极介电层上；以及其中，所述第二晶体管包括：第二栅极介电层，形成在所述第二鳍结构的顶面和侧壁上；和第二栅电极，形成在所述第二栅极介电层上，其中，所述第一栅极介电层和所述第二栅极介电层是高k 介电层，并且所述第一栅电极和所述第二栅电极是金属栅电极。
在一些实施例中，提供了一种鳍式场效应晶体管(FinFET)器件结构。FinFET器件结构包括衬底和形成在衬底上的隔离结构。FinFET器件结构也包括嵌入在隔离结构中的第一鳍结构和形成在第一鳍结构上的第一晶体管。FinFET器件结构还包括形成在第一鳍结构和隔离结构上的第二晶体管。FinFET器件结构包括在第一晶体管和第二晶体管之间的端到端间隙中形成的层间介电(ILD)结构，并且端到端间隙具有在从约10nm至约50nm 的范围内的宽度。
在上述FinFET器件结构中，其中，所述第一晶体管包括：第一栅极介电层，形成在所述第一鳍结构上；和第一栅电极，形成在所述第一栅极介电层上；以及其中，所述第二晶体管包括：第二栅极介电层，形成在所述第一鳍结构和所述隔离结构上；和第二栅电极，形成在所述第二栅极介电层上。
在上述FinFET器件结构中，其中，所述第一晶体管包括：第一栅极介电层，形成在所述第一鳍结构上；和第一栅电极，形成在所述第一栅极介电层上；以及其中，所述第二晶体管包括：第二栅极介电层，形成在所述第一鳍结构和所述隔离结构上；和第二栅电极，形成在所述第二栅极介电层上，其中，所述第一栅极介电层和所述第二栅极介电层是高k介电层，并且所述第一栅电极和所述第二栅电极是金属栅电极。
在上述FinFET器件结构中，其中，所述第一晶体管包括：第一栅极介电层，形成在所述第一鳍结构上；和第一栅电极，形成在所述第一栅极介电层上；以及其中，所述第二晶体管包括：第二栅极介电层，形成在所述第一鳍结构和所述隔离结构上；和第二栅电极，形成在所述第二栅极介电层上，其中，所述ILD结构的侧壁具有底部和顶部，所述第一栅极介电层覆盖所述ILD结构的侧壁的所述底部，并且所述第一栅电极覆盖所述ILD 结构的侧壁的所述顶部。
在上述FinFET器件结构中，还包括：第二鳍结构，邻近所述第一鳍结构形成；第三晶体管，形成在所述隔离结构和所述第二鳍结构上；以及层间介电(ILD)结构，形成在所述第二晶体管和所述第三晶体管之间的第二端到端间隙中，其中，所述第二端到端间隙具有在从约10nm至约50nm的范围内的宽度。
在一些实施例中，提供了一种用于形成鳍式场效应晶体管器件结构的方法。该方法包括提供衬底和形成在衬底之上延伸的第一鳍结构和第二鳍结构。该方法也包括在第一鳍结构和第二鳍结构上形成介电层以及在介电层上形成多晶硅层、硬掩模层和光刻胶层。该方法也包括图案化光刻胶层以在光刻胶层中形成第一沟槽，并且第一沟槽具有第一宽度。该方法包括在第一沟槽中共形地形成涂层以在光刻胶层中形成第二沟槽，并且第二沟槽具有第二宽度，并且第二宽度小于第一宽度。该方法还包括通过将光刻胶层用作掩模来图案化硬掩模层，以及通过将硬掩模用作掩模来图案化多晶硅层以在第一鳍结构和第二鳍结构之间形成端到端间隙。端到端间隙具有第三宽度，并且第三宽度小于第一宽度。
在上述方法中，还包括：在所述端到端间隙中形成层间介电(ILD)结构。
在上述方法中，其中，所述第三宽度在从约10nm至约50nm的范围内。
在上述方法中，其中，在所述第一沟槽中形成所述涂层之前，还包括：通过含氟气体清洗所述光刻胶层。
在上述方法中，其中，在所述第一沟槽中形成所述涂层之前，还包括：通过含氟气体清洗所述光刻胶层，其中，所述含氟气体包括四氟甲烷(CF4)、六氟化硫(SF6)、三氟化氮(NF3)或它们的组合。
在上述方法中，其中，形成所述光刻胶层包括：在所述硬掩模层上形成第一光刻胶层，其中，所述第一光刻胶层是富碳层；以及在所述第一光刻胶层上形成第二光刻胶层，其中，所述第二光刻胶层是富硅层。
在上述方法中，其中，在所述第一沟槽中形成所述涂层包括使用涂布工艺，并且通过使用含氟气体实施所述涂布工艺。
在上述方法中，其中，在所述第一沟槽中形成所述涂层包括使用涂布工艺，并且通过使用含氟气体实施所述涂布工艺，其中，所述涂布工艺的涂布时间在从约1秒至约50秒的范围内。
在上述方法中，其中，形成所述硬掩模层包括：在所述多晶硅层上形成第一硬掩模层；以及在所述第一硬掩模层上形成第二硬掩模层。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (9)

1.一种用于形成鳍式场效应晶体管(FinFET)器件结构的方法，包括：
提供衬底；
形成第一鳍结构和第二鳍结构，所述第一鳍结构和所述第二鳍结构在所述衬底之上延伸；
在所述第一鳍结构和所述第二鳍结构上形成介电层；
在所述介电层上形成多晶硅层、硬掩模层和光刻胶层；
图案化所述光刻胶层以在所述光刻胶层中形成第一沟槽，其中，所述第一沟槽具有第一宽度；
在所述第一沟槽中共形地形成涂层以在所述光刻胶层中形成第二沟槽，其中，所述第二沟槽具有第二宽度，并且所述第二宽度小于所述第一宽度；
通过将所述光刻胶层用作掩模来图案化所述硬掩模层；
通过将所述硬掩模层用作掩模来图案化所述多晶硅层以在所述第一鳍结构和所述第二鳍结构之间形成端到端间隙，其中，所述端到端间隙具有第三宽度，并且所述第三宽度小于所述第一宽度。
2.根据权利要求1所述的用于形成鳍式场效应晶体管(FinFET)器件结构的方法，还包括：
在所述端到端间隙中形成层间介电(ILD)结构。
3.根据权利要求1所述的用于形成鳍式场效应晶体管(FinFET)器件结构的方法，其中，所述第三宽度在从10nm至50nm的范围内。
4.根据权利要求1所述的用于形成鳍式场效应晶体管(FinFET)器件结构的方法，在所述第一沟槽中形成所述涂层之前，还包括：
通过含氟气体清洗所述光刻胶层。
5.根据权利要求4所述的用于形成鳍式场效应晶体管(FinFET)器件结构的方法，其中，所述含氟气体包括四氟甲烷(CF4)、六氟化硫(SF6)、三氟化氮(NF3)或它们的组合。
6.根据权利要求1所述的用于形成鳍式场效应晶体管(FinFET)器件结构的方法，其中，形成所述光刻胶层包括：
在所述硬掩模层上形成第一光刻胶层，其中，所述第一光刻胶层是富碳层；以及
在所述第一光刻胶层上形成第二光刻胶层，其中，所述第二光刻胶层是富硅层。
7.根据权利要求1所述的用于形成鳍式场效应晶体管(FinFET)器件结构的方法，其中，在所述第一沟槽中形成所述涂层包括使用涂布工艺，并且通过使用含氟气体实施所述涂布工艺。
8.根据权利要求7所述的用于形成鳍式场效应晶体管(FinFET)器件结构的方法，其中，所述涂布工艺的涂布时间在从1秒至50秒的范围内。
9.根据权利要求1所述的用于形成鳍式场效应晶体管(FinFET)器件结构的方法，其中，形成所述硬掩模层包括：
在所述多晶硅层上形成第一硬掩模层；以及
在所述第一硬掩模层上形成第二硬掩模层。
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