TW201442230A - 異質結構功率電晶體以及製造異質結構半導體裝置的方法 - Google Patents

異質結構功率電晶體以及製造異質結構半導體裝置的方法 Download PDF

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TW201442230A
TW201442230A TW103105818A TW103105818A TW201442230A TW 201442230 A TW201442230 A TW 201442230A TW 103105818 A TW103105818 A TW 103105818A TW 103105818 A TW103105818 A TW 103105818A TW 201442230 A TW201442230 A TW 201442230A
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layer
active layer
ohmic contact
gate
gate dielectric
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TWI656644B (zh
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Jamal Ramdani
Michael Murphy
John Paul Edwards
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Power Integrations Inc
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Abstract

一種異質結構半導體裝置，包含一第一主動層和佈置於該第一主動層上之一第二主動層。一二維電子氣層被形成於該第一主動層與該第二主動層之間。一AlSiN鈍化層被佈置於該第二主動層上。一第一歐姆接觸點和一第二歐姆接觸點電性連接至該第二主動層。該第一歐姆接觸點和該第二歐姆接觸點橫向間隔開，一閘極被佈置於該第一歐姆接觸點與該第二歐姆接觸點之間。

Description

異質結構功率電晶體以及製造異質結構半導體裝置的方法
本發明概言之係關於高電壓場效電晶體(field effect transistor；FET)，更具體而言，係關於高電子遷移率電晶體(high-electron-mobility transistor；HEMT)及異質結構場效電晶體(heterostructure field-effect transistor；HFET)，且係關於製造此種功率電晶體裝置之方法。
一種類型之高電壓場效電晶體係為異質結構場效電晶體(HFET)，亦被稱為異質結或高電子遷移率電晶體(HEMT)。基於氮化鎵(GaN)及其他寬帶隙III-IV直接躍遷半導體材料(direct transitional semiconductor material)之HFET，諸如碳化矽(SiC)，因其超越矽基裝置之優越物理性質而被有利地用於某些電子裝置中。例如，GaN和AlGaN/GaN電晶體一般因由GaN基材料和裝置結構提供之高電子遷移率、高擊穿電壓、和高飽和電子速度特性而被用於高速切換和高功率應用中(例如功率開關和功率轉換器)。由於HFET之物理性質，HFET可以遠快於在相同電壓下傳導相同電流之其他半導體開關之方式改變狀態，且寬帶隙可改善HFET在高溫之效能。
GaN基HFET裝置通常藉由磊晶生長(epitaxial growth)被製造於形成為薄盤(thin disk)或晶圓(wafer)形式之基板半導體材料(諸如矽、藍寶石和碳化矽)上。用於直接在該半導體材料中形成電子裝置(例如電晶體)之製造步驟常常被稱為前端工序(front-end-of-line；FEOL)處理。在HFET之FEOL處理過程中，該晶圓可以被從各種機器移動，以建立該裝置結構之各種材料層。但因為GaN係為壓電材料，故GaN基HFET裝置在FEOL處理期間易於發生電荷累積(正的或負的)。例如，電荷累積可係由在半導體之表面上涉及沈積或生長電介質層之鈍化工藝導致的。可藉由將該晶圓之表面與環境中之電性和化學狀況隔離來利用鈍化提供電穩定性。比如，在HFET製造期間暴露至空氣可導致發生表面反應(諸如氧化)，此可影響該HFET裝置之總體效能。
根據本發明之一態樣，提供一種異質結構功率電晶體，該異質結構功率電晶體包含：一第一主動層；一第二主動層，被佈置於該第一主動層上，一二維電子氣層形成於該第一主動層與該第二主動層之間；一包含氮化鋁矽(AlSiN)之鈍化層，被佈置於該第二主動層上；一閘極；一第一歐姆接觸點和一第二歐姆接觸點，電性連接至該第二主動層，該第一歐姆接觸點和該第二歐姆接觸點橫向間隔開，該閘極被佈置於該第一歐姆接觸點與該第二歐姆接觸點之間。
根據本發明之另一態樣，提供一種用於製造異質結構半導體裝置之方法，該方法包含：在一基板上形成一第一主動層；在該第一主動層上形成一第二主動層，該第一主動層和該第二主動層具有不同之帶隙， 以使得其間形成一二維電子氣層；在該第二主動層上形成一包含氮化鋁矽(AlSiN)之鈍化層，該鈍化層具有一第一厚度；形成一第一歐姆接觸點和一第二歐姆接觸點，其各自皆豎向延伸穿過該鈍化層，該第一歐姆接觸點和該第二歐姆接觸點橫向間隔開，且電性連接至該第二主動層；以及在該第一歐姆接觸點與該第二歐姆接觸點間之橫向位置處形成一閘極。
102‧‧‧第一主動層
104‧‧‧電荷層
106‧‧‧第二主動層
108‧‧‧鈍化層
112‧‧‧閘極
114‧‧‧源極歐姆接觸點
116‧‧‧汲極歐姆接觸點
202‧‧‧第一主動層
204‧‧‧二維電子氣層
206‧‧‧第二主動層
208‧‧‧鈍化/第一閘極電介質層
210‧‧‧第二閘極電介質層
212‧‧‧閘極
214‧‧‧源極歐姆接觸點
216‧‧‧汲極歐姆接觸點
302‧‧‧第一主動層
304‧‧‧二維電子氣層
306‧‧‧第二主動層
308‧‧‧鈍化/第一閘極電介質層
310‧‧‧第二閘極電介質層
312‧‧‧閘極
314‧‧‧源極歐姆接觸點
316‧‧‧汲極歐姆接觸點
318‧‧‧上鈍化層
402~416‧‧‧步驟
502~516‧‧‧步驟
參照下列圖描述本發明之非限制性和非窮舉性實施方案，其中在各個視圖中，相同之參考編號指代相同之部分，除非另有規定。
第1圖係為具有一鈍化結構之一示例性半導體裝置之剖視側視圖。
第2圖係為具有另一鈍化結構之一示例性半導體裝置之剖視側視圖。
第3圖係為具有又一鈍化結構之一示例性半導體裝置之剖視側視圖。
第4圖係為例示用於製造一半導體裝置結構之一示例性處理流程之流程圖。
第5圖係為例示用於製造一半導體裝置結構之另一示例性處理流程之流程圖。
在此等附圖之所有幾個視圖中，對應之參考字符指示對應之部件。熟習此項技術者應意識到，此等圖中之元件係為了簡化和清楚而例示的，且未必按比例繪製。例如，此等圖中之一些元件之尺寸相對於其他元件可被誇大，以幫助增進對本發明之多種實施例之理解。而且，常常不繪示在商業上可行之實施例中有用或必要之普通但廣為理解之元件，以免妨礙觀看本發明之此等多種實施例。
在下列描述中，闡述了眾多具體細節，以提供對本發明之透徹理解。然而應明瞭，對於此項技術中之通常知識者，無需採用該具體細節來實踐本發明。在其他情況下，未詳細描述眾所習知之材料或方法，以免模糊本發明。
本說明書通篇提及「一個實施例」、「一實施例」、「一個實例」或「一實例」意指，結合該實施例或實例描述之特定特徵、結構或特性被包含於本發明之至少一個實施例中。因而，在本說明書通篇各個地方出現之片語「在一個實施例中」、「在一實施例中」、「一個實例」或「一實例」未必皆指代相同之實施例或實例。此外，該等特定特徵、結構或特性可以任何合適之組合和/或子組合被結合於一或多個實施例或實例中。該等特定特徵、結構或特性可被包含於一積體電路、一電子電路、一組合邏輯電路或提供所述功能之其他合適之部件中。另外，應意識到，隨此提供之此等圖係為了向此項技術中之通常知識者解釋，且繪圖未必按比例繪製。
在下面之描述中，為瞭解釋而使用一示例性HFET。然而，應意識到，本發明之實施例可與其他類型之場效電晶體(諸如金屬氧化物半導體FET(MOSFET)或金屬絕緣體半導體FET(MISFET)裝置)一起使用。
如上面所述，在製造過程期間，表層電荷(sheet charge)可以積累於HFET裝置之晶圓上。為對抗所積累之表面電荷(surface charge)之作用，且為保護該等HFET裝置不受其他環境狀況影響，可使用一或多個電介質材料層作為保護HFET之表面之鈍化層。
根據本發明之一些實施例，揭露一種GaN基HFET裝置結構 及其製造方法，其利用一種基於氮化鋁矽(AlSiN)之新材料組合來鈍化一HFET裝置之一GaN表面。在一個實施例中，該AlSiN層在該HFET裝置中用作一鈍化層和一閘極電介質。與傳統之鈍化材料相比，當用於本文描述之HFET結構中時，AlSiN之較寬帶隙可使切換期間之電流崩塌(current collapse)最小化、減少閘極洩漏以及提供增強之閘極可靠性和穩定性。
在一個實施例中，該HFET裝置具有一第一主動層和一第二主動層，二者之間形成有一二維電子氣層(two-dimensional electron gas layer)。由AlSiN(例如AlSi3N4)形成之一鈍化層被佈置於該第二主動層上。該AlSiN鈍化層亦可用作一第一閘極電介質層。(在本揭露內容中，此雙功能層亦被稱為一鈍化/第一閘極電介質層。)在又一實施例中，一第二閘極電介質層被佈置於該第一閘極電介質層上。在一個實例中，氧化鋁(Al2O3)被用於第二閘極電介質層。在另一些實施例中，一或多個附加之層被形成於該第二閘極電介質層之上。一閘極構件被佈置於該AlSiN鈍化層上方。該裝置之歐姆接觸點(ohmic contact)(源極和汲極)向下延伸至該第二主動層。
第1圖例示一示例性半導體裝置(即HFET裝置)100之剖視側視圖，半導體裝置100包含：一第一主動層102，亦被稱為一通道層；一第二主動層106，亦被稱為一阻擋層(barrier layer)或施主層(donor layer)；一鈍化層108；一閘極112；以及一源極歐姆接觸點114和一汲極歐姆接觸點116。源極歐姆接觸點114和汲極歐姆接觸點116被示出為豎向向下延伸穿過鈍化層108，以電性連接至第二主動層106。如圖所示，源極歐姆接觸點114和汲極歐姆接觸點116橫向間隔開，且閘極114被佈置於源極歐姆接觸點114 與汲極歐姆接觸點116之間。
第1圖中進一步顯示電荷層104，其形成於第一主動層102與第二主動層106之間。電荷層104有時被稱為二維電子氣(2DEG)層104。2DEG層104界定用於該HFET裝置之橫向導電通道。2DEG層104係因該二主動層間之帶隙差異而形成。尤其，2DEG層104係因該二主動層之間自發的壓電極化作用之變化而形成的。因而，被捕獲於由第一主動層102與第二主動層106間之帶隙差異造成之一量子阱中之電子在兩個(水平)維度上自由地橫向移動，但在第三(豎直)維度中受到嚴格限制。
在本揭露內容之上下文中，術語「原位(in-situ)」係指在單個工具或反應腔內執行之處理，而不將該晶圓暴露至該工具或腔外部之環境。進一步，術語「非原位(ex-situ)」可指不在單個工具中執行之處理。在另一實施例中，在分別形成第一主動層102和第二主動層106之後，可使用金屬-有機化學氣相分解(MOCVD)來形成鈍化層108。換言之，鈍化層108可分別與第一主動層102和第二主動層106原位沈積。
應意識到，第一主動層102通常被佈置於由若干不同材料(諸如藍寶石(Al2O3)、矽(Si)、GaN或碳化矽(SiC))中之任何一種形成之基板(未示出)之上。在一個實施例中，第一主動層102包含一磊晶GaN層。為避免可能之晶格失配和/或熱膨脹係數差異之問題，一或多個附加之層可被佈置於第一主動層102與下面之基板之間。例如，一可選之薄成核層可被形成於該基板與第一主動層102之間。在另一些實例中，第一主動層102可包含含有其他III族元素之多種氮化物之不同半導體材料。另外，在形成第二主動層106之前，可在第一主動層102頂上形成AlN薄(約1nm)層。第一 主動層102可被生長或沈積於該基板上。
第二主動層106被佈置於第一主動層102上。在第1圖之實例中，第二主動層106包含氮化鋁鎵(AlGaN)。在另一些實例中，不同之III族氮化物半導體材料(諸如氮化鋁銦(AlInN)和氮化鋁銦鎵(AlInGaN))可被用於第二主動層106。在另一些實施例中，第二主動層106之材料可係為非化學計量化合物(non-stoichiometric compound)。在此種材料中，各元素之比例不易用普通整數來表達。例如，第二主動層106可係為III族非化學計量氮化物半導體材料，諸如AlXGa1-XN，其中0<X<1。在一個實施方式中，第二主動層106包含具有約20奈米(nm)厚之厚度之AlGaN(Al 25%)。在形成鈍化層108之前，可視需要在第二主動層106頂上形成一薄的(約1nm)GaN終止層。第二主動層106可以被生長或沈積於第一主動層102上。
如第1圖中所示，鈍化層108被佈置於第二主動層106上。如上面所討論，在一個實施例中，鈍化層108包含氮化鋁矽(AlSiN)。在一個實例中，鈍化層108之厚度可在1奈米至10奈米(nm)厚之近似範圍內。進一步，在一個實施方式中，鈍化層108係為基本5-10%之鋁(Al)對氮化矽(SiN)，且被形成為1奈米至10奈米厚。如先前所討論，鈍化層108可分別與第一主動層102和第二主動層106原位沈積，且被用來鈍化此等GaN基主動層。在一個實例中，鈍化層108具有與使用MOCVD原位生長之層相似之純度、密度和強度特性。例如，與非原位生長之層相比，原位生長之層通常具有更高之純度、更高之強度和更高之密度。進一步，鈍化層108亦可以被用作閘極電介質層。
鈍化層108將閘極112與第二主動層106分隔開。如圖所示， 閘極112被佈置於鈍化層108頂上。在一個實施例中，閘極112包含金鎳(NiAu)合金。在另一實施例中，閘極112包含鈦金(TiAu)合金或鉬金(MoAu)合金。在另一些實例中，閘極112可包含一閘極電極和一閘極場板。在運作中，閘極112控制各自之源極歐姆接觸點114和汲極歐姆接觸點116間之向前導通路徑。在第1圖之實例中，位於鈍化層108上方且朝著歐姆汲極接觸點116橫向延伸之閘極112之部分用作閘極場板，其用以減輕邊緣(最靠近歐姆汲極接觸點116)處之電場強度。
歐姆接觸點114和116被佈置為穿過鈍化電介質層108，以接觸第二主動層106。歐姆接觸點114係為源極接觸點之一實例，而歐姆接觸點116係為汲極接觸點之一實例。在一個實施例中，歐姆接觸點114和116可藉由在鈍化層108中蝕刻開口、然後進行金屬沈積和退火步驟而形成。
如圖所示，第1圖例示製造過程中在剛剛形成閘極112以及歐姆金屬接觸點114和116之後之一點處之裝置結構，歐姆金屬接觸點114和116分別構成GaN HFET裝置100之源極電極和汲極電極。第1圖顯示直接形成於鈍化層108上之歐姆金屬接觸點114和116。在另一些實施例中，歐姆金屬接觸點114和116可被形成於豎向向下延伸至第二主動層106中之凹陷中。在又一些實施例中，歐姆金屬接觸點114和116可被形成於豎向向下延伸穿過第二主動層106之凹陷中，以接觸第一主動層102。
當半導體裝置100被配置為用作功率開關時，閘極112以及歐姆接觸點114和116通常藉由端子被聯結，以形成與外部電路之電性連接。在運作中，2DEG層104中之電荷在歐姆接觸點114與116之間橫向流動，以成為外部電路中之電流。該電荷流動，從而該電流，可被來自電性連接於 閘極112與歐姆接觸點114間之外部電路之電壓控制。
本揭露內容中所述之電性連接係為歐姆連接。歐姆連接係為如下連接：其中電壓與電流間之關係係為基本線性的，且在該電流之兩個方向上係對稱的。例如，僅藉由金屬進行彼此接觸之兩個金屬圖案被電性連接。相比之下，歐姆接觸點114和116在半導體裝置100中未電性連接至彼此，乃因該二接觸點間之任何連接皆係透過該半導體材料中之通道進行的，該傳導路徑被閘極112控制。相似地，閘極112未電性連接至第二主動層106，乃因鈍化層108將閘極112與下面之主動層隔離。
如上面所討論，利用AlSiN作為鈍化層108有助於減輕在製造和/或操縱裝置100期間積累之表面電荷之不利效應。另外，利用AlSiN作為本文所述HFET結構中之鈍化層108可以使切換期間之電流崩塌最小化、減少閘極洩漏以及提供增強之閘極可靠性和穩定性。進一步，鈍化層108亦可以被用作一閘極電介質層。
第2圖例示一示例性半導體裝置(HFET裝置)200之剖視側視圖，半導體裝置200包含一第一主動層202、一第二主動層206以及形成於其間之一2DEG層204。亦示出了一鈍化/第一閘極電介質層208、一第二閘極電介質210、一閘極212以及一源極歐姆接觸點214和一汲極歐姆接觸點216。第2圖所示之半導體裝置200類似於第1圖之半導體裝置100，只是HFET裝置200包含位於鈍化層218頂上之一第二閘極電介質層210。第二閘極電介質層210被佈置於鈍化/第一閘極電介質層208上，且橫向包圍源極歐姆接觸點114和汲極歐姆接觸點116、以及閘極112。此外，鈍化/第一閘極電介質層208類似於鈍化層108，然而被稱為「鈍化/第一閘極電介質層」，以強調鈍化 層208亦可被用作多個閘極電介質層其中之一個層。
如圖所示，第二閘極電介質層210被佈置於鈍化/第一閘極電介質層208上。在一個實例中，第二閘極電介質層210包含氧化鋁(Al2O3)。在又一些實施例中，其他氧化物材料(諸如ZrO、HfO、SiO2和GdO)可被用於第二閘極電介質層210。在一個實施例中，第二閘極電介質層210具有近似10奈米至20奈米厚之範圍內之厚度。在一個實施例中，第二閘極電介質層210厚於鈍化/第一閘極電介質層208。例如，鈍化/第一閘極電介質層208之厚度可處於近似1奈米至10奈米之範圍內。在一個示例性製造過程中，可利用原子層沈積(atomic layer deposition；ALD)將第二閘極電介質層210與第一主動層202和第二主動層206非原位沈積。
如圖所示，鈍化/第一閘極電介質層208和第二閘極電介質層210將閘極212與第二主動層206豎向分隔開。在某些實施例中，閘極212可包含一閘極電極和一閘極場板構件。在第2圖之實例中，位於第二鈍化層218上方且朝著汲極歐姆接觸點216橫向延伸之閘極212之部分用作閘極場板構件，其用以減輕邊緣(最接近汲極歐姆接觸點216)處之電場強度。
如圖所示，源極歐姆接觸點214和汲極歐姆接觸點216分別被佈置於閘極212之對立之橫向側上。歐姆接觸點214和216豎向延伸第二閘極電介質層210和鈍化/第一閘極電介質層208，以接觸第二主動層206。在一個實施例中，歐姆接觸點214和216可藉由在第二閘極電介質層210和鈍化/第一閘極電介質層208中蝕刻開口、然後進行金屬沈積和退火步驟而形成。在另一示例性製造過程中，歐姆接觸點214和216可在沈積第二閘極電介質層210之前被形成。
進一步，鈍化/第一閘極電介質層208可連同第二閘極電介質層210一起被用作一個閘極電介質層。此項技術之從業者應意識到，以本文描述之方式利用多個閘極電介質層可有利地使所得到之HFET裝置在更高臨界電壓下運作。該臨界電壓VCRIT被定義為閘極-源極電壓VGS，在該電壓處，閘極洩漏電流中存在相對急劇之上升。另外，與僅僅利用單個閘極電介質層之裝置相比，多個閘極電介質層之使用可改進半導體裝置200之熱穩定性。熱穩定性與該裝置之閘極洩漏電流隨著溫度而增大多少有關。
第3圖例示一示例性半導體裝置(HFET裝置)300之剖視側視圖，該半導體裝置300包含一第一主動層302、一第二主動層306以及形成於其間之2DEG層304。亦顯示一鈍化/第一閘極電介質層308、一第二閘極電介質310、一上鈍化層318、一閘極312以及源極歐姆接觸點314和汲極歐姆接觸點316。第3圖所示之半導體裝置300類似於第1圖之半導體裝置100和第2圖之半導體裝置200，只是HFET裝置300包含上鈍化層318。上鈍化層318被佈置於第二閘極電介質310上，且橫向圍繞源極歐姆接觸點314和汲極歐姆接觸點316以及閘極312。進一步，鈍化/第一閘極電介質層308類似於鈍化層108，然而被稱為「鈍化/第一閘極電介質層」，以強調鈍化層/第一閘極電介質層308亦可被用作多個閘極電介質層其中之一個層。
在一個實施例中，上鈍化層318可包含一電介質材料，諸如氮化矽(SiN)。在另一些實施例中，上鈍化層318可包含多個材料層。應意識到，上鈍化層318藉由將HFET裝置300之表面與周圍環境中之電性和化學污染物隔離，而提供HFET裝置300之電特性之穩定性。上鈍化層218可藉由化學氣相沈積(諸如低壓化學氣相沈積(LPCVD)或電漿增強化學氣相沈 積(PECVD))沈積而成。
如圖所示，上鈍化層318、鈍化/第一閘極電介質層308和第二閘極電介質層310將閘極312與第二主動層306豎向分隔開。在某些實施例中，閘極312可包含一閘極電極和一閘極場板構件。如圖所示，閘極312豎向延伸穿過在上鈍化層318中形成之一開口，以接觸第二閘極電介質層210。在一示例性製造過程中，閘極312可係藉由在上鈍化層318中蝕刻開口、然後進行閘極金屬沈積而形成。在第3圖之實例中，位於上鈍化層318上方且朝著汲極歐姆接觸點316橫向延伸之閘極312之部分充當一閘極場板構件，其用以減輕邊緣(最靠近汲極歐姆接觸點316)處之電場強度。
如圖所示，源極歐姆接觸點314和汲極歐姆接觸點316分別被佈置於閘極312之對立之橫向側上。歐姆接觸點314和316豎向延伸穿過上鈍化層318、第二閘極電介質層310和鈍化/第一閘極電介質層308，以接觸第二主動層306。在一個實施例中，歐姆接觸點314和316可藉由在上鈍化層318、第二閘極電介質層310和鈍化/第一閘極電介質層308中蝕刻開口、然後進行金屬沈積和退火步驟而形成。在另一示例性製造過程中，歐姆接觸點314和316可在沈積第二閘極電介質層310和上鈍化層318之前形成。
第4圖例示用於建構半導體裝置(諸如第1圖、第2圖和第3圖中分別示出之HFET裝置100、200或300)之示例性處理流程400。在所示實例中，該處理在完成第一主動層和第二主動層在該基板上之磊晶生長或沈積之後開始。包含AlSiN之層(在上文亦被稱為鈍化/第一閘極電介質層)之形成係在GaN/AlGaN主動層之生長之後被原位執行(方框402)。在一個實施例中，該鈍化層係使用在800-900℃之間範圍之溫度以約100托之反應 器壓力執行之MOCVD技術來沈積。在一個實施例中，包含AlSiN之鈍化層係以MOCVD技術生長而成，使用矽烷(SiH4)、氨(NH3)和三甲基鋁(TMAl)作為用於AlSiN之前體。可使用氫氣(H2)和氮氣(N2)作為載氣(carrier gas)。總流量為約50升/分鐘，其中NH3流量處於1升/分鐘至10升/分鐘範圍內，SiH4為約1升/分鐘，且TMAl流量為約5sccm至20sccm範圍內。NH3流量被維持成使得綜合之N成分被維持在如由AlSiN膜之總體折射率和密度監測之Si3N4與AlN間之化學定量關係(stoichiometry)。
該鈍化層被形成至近似1奈米至10奈米之範圍內之厚度，且在該晶圓之表面之上係為連續的。在一個實施例中，該鈍化層之厚度係為約5奈米。在再一實施例中，該鈍化層係與該第一主動層和該第二主動層原位形成的。例如，被用於形成該第一主動層和該第二主動層之同一MOCVD機器亦可被用於形成該鈍化/第一閘極電介質層。在一個實例中，該鈍化層/第一閘極電介質層具有對於使用MOCVD原位生長之層而言所特有之純度、密度和強度。例如，原位生長之層通常具有較非原位生長之層更高之純度、更高之強度以及更高之密度。
在生長該鈍化層之後，該鈍化層之表面經歷台面隔離蝕刻(mesa isolation etching)，以界定歐姆接觸點之主動區(方框404)。該台面隔離可利用反應性離子蝕刻(reactive-ion etching；RIE)系統來執行。在另一些製造方法中，該台面隔離可使用電感耦合電漿(inductively coupled plasma；ICP)RIE來執行。在該處理流程中之此刻，可視需要穿過該鈍化層形成歐姆通孔開口，然後進行歐姆金屬化和退火(方框306)。一種示例性歐姆接觸金屬係為TiAlMoAu。該等金屬歐姆接觸點可利用一RTA工具在 近似600-900℃之溫度範圍被退火長達大約一分鐘。
接下來，第二閘極電介質層(可由Al2O3構成)可被視需要沈積於該鈍化層上(方框408)。該第二閘極電介質層亦可沈積於源極歐姆接觸點和汲極歐姆接觸點之上。在一個實施例中，該第二閘極電介質層係在300℃使用原子層沈積而被沈積於晶圓表面上。該第二閘極電介質層可被生長至近似10奈米至20奈米範圍內之厚度。
在一個實施例中，用於形成該第二閘極電介質層之沈積可係相對於該第一主動層和該第二主動層以及該鈍化/第一閘極電介質層非原位地執行。例如，該鈍化/第一閘極電介質層和該第二閘極電介質層二者可使用相同之原子層沈積腔或者其他機器或系統被沈積於晶圓表面上。
在已經沈積該第二閘極電介質層之後，可執行高溫退火(方框410)，以改善該第二閘極電介質層之膜和界面品質。例如，該退火步驟可在爐中在450-750℃之溫度範圍被執行近似5分鐘至10分鐘。亦可使用若干不同工具(諸如快速溫度退火(rapid temperature annealing；RTA)工具)來執行退火。應意識到，方框408和方框410被認為係可選的，乃因此等方框應用於第2圖和第3圖所示之HFET裝置(其例示一第二閘極電介質層)。
在退火之後，可視需要在該第二閘極電介質層之上沈積一上鈍化層(方框412)。在一個實施例中，該上鈍化層可使用PECVD來沈積。該上鈍化層亦可使用LPCVD來沈積。該上鈍化層通常被形成至在近似100奈米至150奈米範圍內之厚度。如上文所討論，該上鈍化層可包含氮化矽(SiN)或具有相似性質之其他材料。
在方框314中顯示閘極通孔之形成。此步驟係在一上鈍化層 已經形成於由多個閘極電介質層形成之堆疊之上時視需要執行。閘極通孔形成包含對該上鈍化層進行遮罩和蝕刻，以使得穿過該上鈍化層形成開口，由此暴露下面之第二閘極電介質層。在一個實施例中，可使用一氣體(諸如CF4或SF6)利用乾蝕刻來蝕刻穿透該上鈍化層。在該蝕刻處理暴露該第二閘極電介質層之後，執行一閘極金屬或金屬合金沈積(方框316)，以填充所蝕刻之開口。在一個實例中，NiAu被用作該閘極金屬。如第1圖、第2圖和第3圖所示，可藉由對該閘極金屬進行遮罩或蝕刻來形成該閘極之一場板部分，以使得一頂部部分在該上鈍化層之上朝著最遠之(汲極)歐姆接觸點橫向延伸。應意識到，方框412和414被認為係可選的，乃因此等方框應用於第3圖所示之HFET裝置300(其例示一上鈍化層)。
半導體技術領域中之通常知識者應理解，可執行其他標準之製造後(post-fabrication)或後端(back-end)處理步驟，包含：在該晶圓之表面上形成金屬(例如，圖案化線路或跡線)；晶圓背磨(backgrinding)，亦被稱為背研磨(backlapping)或晶圓打薄(wafer thinning)；晶粒分離(die separation)；以及封裝。
第5圖係為例示用於構建一HFET裝置(諸如第2圖和第3圖中所示之半導體裝置200或300)之另一示例性處理流程400之圖表。第5圖中所示之處理與參照第4圖所討論者相同，其中相同編號之步驟與上文所述者相同，只是處理流程500包含介於方框502與方框504間之附加方框503。在該AlSiN鈍化/第一閘極電介質層之原位生長之後，氮化鋁(AlN)被生長於該AlSiN層之頂上(方框503)。在一個實施例中，該AlN層係與該AlSiN鈍化/第一閘極電介質層以及該第一主動層和該第二主動層原位生長。該AlN層 之厚度可係為約1奈米厚。在方框504和506中之台面隔離蝕刻以及歐姆金屬化和退火之後，該AlN層被有效地用作籽晶層，以形成該Al2O3第二閘極電介質層(方框508)。
上面對所例示之示例性實施例之描述，包括摘要中之描述，不旨在作為窮舉性描述或限於所揭露之精確形式。儘管本文描述之主題之具體實施例和實例係為了例示目的，但在不脫離本發明之更廣精神和範圍之前提下，可具有多種等同潤飾。事實上，應意識到，具體之示例性之厚度、材料類型、溫度、電壓、時間等等係為瞭解釋目的而提供，且在根據本發明之教導之其他實施例和實例中亦可以採用其他值。
102‧‧‧第一主動層
104‧‧‧電荷層
106‧‧‧第二主動層
108‧‧‧鈍化層
112‧‧‧閘極
114‧‧‧源極歐姆接觸點
116‧‧‧汲極歐姆接觸點

Claims (28)

  1. 一種異質結構功率電晶體，包含：一第一主動層；一第二主動層，被佈置於該第一主動層上，一二維電子氣層(two-dimensional electron gas layer)形成於該第一主動層與該第二主動層之間；一包含氮化鋁矽(AlSiN)之鈍化層，被佈置於該第二主動層上；一閘極；一第一歐姆接觸點和一第二歐姆接觸點，電性連接至該第二主動層，該第一歐姆接觸點和該第二歐姆接觸點橫向間隔開，該閘極被佈置於該第一歐姆接觸點與該第二歐姆接觸點之間。
  2. 如請求項1所述之異質結構功率電晶體，更包含被佈置於該鈍化層上之一第二閘極電介質層，該閘極被佈置於該第二閘極電介質層上方。
  3. 如請求項2所述之異質結構功率電晶體，其中該第二閘極電介質層包含氧化鋁(Al2O3)。
  4. 如請求項2所述之異質結構功率電晶體，更包含被佈置於該第二閘極電介質層之上之一上鈍化層，該閘極豎向延伸穿過該上鈍化層，以接觸該第二閘極電介質層。
  5. 如請求項2所述之異質結構功率電晶體，其中該鈍化層具有一第一厚度，且該第二閘極電介質層具有一第二厚度，該第二厚度大於該第一厚度。
  6. 如請求項2所述之異質結構功率電晶體，其中該第一歐姆接觸點和該第二歐姆接觸點豎向延伸穿過該第二閘極電介質層和 該鈍化層。
  7. 如請求項4所述之異質結構功率電晶體，其中該第一歐姆接觸點和該第二歐姆接觸點豎向延伸穿過該上鈍化層、該第二閘極電介質層和該鈍化層。
  8. 如請求項1所述之異質結構功率電晶體，其中該鈍化層具有介於約1奈米至5奈米厚之範圍內之一第一厚度。
  9. 如請求項2所述之異質結構功率電晶體，其中該第二閘極電介質具有介於約10奈米至20奈米厚之範圍內之一第二厚度。
  10. 如請求項1所述之異質結構功率電晶體，其中該第一歐姆接觸點和該第二歐姆接觸點分別包含一源極歐姆接觸點和一汲極歐姆接觸點。
  11. 如請求項4所述之異質結構功率電晶體，其中該上鈍化層包含SiN。
  12. 如請求項1所述之異質結構功率電晶體，其中該第一主動層包含氮化鎵(GaN)。
  13. 如請求項1所述之異質結構功率電晶體，其中該第二主動層包含氮化鋁鎵(AlGaN)。
  14. 如請求項1所述之異質結構功率電晶體，其中該第一主動層和該第二主動層被限定為一隔離台面(isolated mesa)。
  15. 如請求項1所述之異質結構功率電晶體，其中該閘極包含鎳金(NiAu)合金。
  16. 如請求項10所述之異質結構功率電晶體，其中該閘極包含朝著該汲極歐姆接觸點延伸之一閘極場板(gate field plate)。
  17. 如請求項1所述之異質結構半導體裝置，其中該閘極包含鈦金 (TiAu)合金或鉬金(MoAu)合金。
  18. 一種用於製造一異質結構半導體裝置之方法，包含：在一基板上形成一第一主動層；在該第一主動層上形成一第二主動層，該第一主動層和該第二主動層具有不同之帶隙，以使得在該第一主動層與該第二主動層之間形成一二維電子氣層；在該第二主動層上形成包含氮化鋁矽(AlSiN)之一鈍化層，該鈍化層具有一第一厚度；形成一第一歐姆接觸點和一第二歐姆接觸點，其各自皆豎向延伸穿過該鈍化層，該第一歐姆接觸點和該第二歐姆接觸點橫向間隔開，且電性連接至該第二主動層；以及在該第一歐姆接觸點與該第二歐姆接觸點間之一橫向位置處形成一閘極。
  19. 如請求項19所述之方法，更包含：將一第二閘極電介質層沈積於該鈍化層之上，該第二閘極電介質層具有大於該第一厚度之一第二厚度。
  20. 如請求項19所述之方法，更包含：將一上鈍化層沈積於該第二閘極電介質層之上。
  21. 如請求項19所述之方法，更包含：將該第二閘極電介質層退火。
  22. 如請求項19所述之方法，其中該第二閘極電介質層包含氧化鋁。
  23. 如請求項18所述之方法，其中該第一主動層包含氮化鎵。
  24. 如請求項18所述之方法，其中該第二主動層包含氮化鋁鎵。
  25. 如請求項18所述之方法，其中該鈍化層係與該第一主動層和該第二主動層原位形成的。
  26. 如請求項18所述之方法，更包含：在該鈍化層之上與該鈍化層原位生長一AlN層。
  27. 如請求項18所述之方法，其中該第一厚度介於約1奈米至5奈米厚之範圍內。
  28. 如請求項19所述之方法，其中該第二厚度介於約10奈米至20奈米厚之範圍內。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI608568B (zh) * 2015-08-29 2017-12-11 台灣積體電路製造股份有限公司 半導體元件與其製作方法
TWI669820B (zh) * 2017-02-20 2019-08-21 日商闊斯泰股份有限公司 氮化物半導體基板以及氮化物半導體基板的製造方法
US10593790B2 (en) 2017-02-20 2020-03-17 Coorstek Kk Nitride semiconductor substrate and method for manufacturing the same
TWI762346B (zh) * 2021-06-04 2022-04-21 瑞礱科技股份有限公司 一種iii族氮化物半導體元件之歐姆接觸製造方法
TWI765974B (zh) * 2017-02-26 2022-06-01 日商住友化學股份有限公司 半導體基板、電子裝置、半導體基板之檢查方法及電子裝置之製造方法

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8633094B2 (en) 2011-12-01 2014-01-21 Power Integrations, Inc. GaN high voltage HFET with passivation plus gate dielectric multilayer structure
CN102723358B (zh) * 2012-05-30 2015-01-07 苏州能讯高能半导体有限公司 绝缘栅场效应晶体管及其制造方法
JP2014072377A (ja) * 2012-09-28 2014-04-21 Fujitsu Ltd 化合物半導体装置及びその製造方法
US8928037B2 (en) * 2013-02-28 2015-01-06 Power Integrations, Inc. Heterostructure power transistor with AlSiN passivation layer
US9443737B2 (en) * 2013-04-03 2016-09-13 Texas Instruments Incorporated Method of forming metal contacts in the barrier layer of a group III-N HEMT
JP6284140B2 (ja) * 2013-06-17 2018-02-28 株式会社タムラ製作所 Ｇａ２Ｏ３系半導体素子
US9455341B2 (en) * 2013-07-17 2016-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor having a back-barrier layer and method of making the same
US9806158B2 (en) 2013-08-01 2017-10-31 Taiwan Semiconductor Manufacturing Co., Ltd. HEMT-compatible lateral rectifier structure
US9978844B2 (en) 2013-08-01 2018-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. HEMT-compatible lateral rectifier structure
US10325988B2 (en) 2013-12-13 2019-06-18 Power Integrations, Inc. Vertical transistor device structure with cylindrically-shaped field plates
US9306014B1 (en) 2013-12-27 2016-04-05 Power Integrations, Inc. High-electron-mobility transistors
US9640620B2 (en) 2014-11-03 2017-05-02 Texas Instruments Incorporated High power transistor with oxide gate barriers
KR102514466B1 (ko) * 2014-12-15 2023-03-24 어플라이드 머티어리얼스, 인코포레이티드 진보된 배선 애플리케이션들을 위한 초박 유전체 확산 배리어 및 에칭 정지 층
FR3030886B1 (fr) * 2014-12-22 2017-03-10 Centre Nat Rech Scient Dispositif de modulation comportant une nano-diode
JP6879662B2 (ja) * 2014-12-23 2021-06-02 パワー・インテグレーションズ・インコーポレーテッド 高電子移動度トランジスタ
JP6401053B2 (ja) * 2014-12-26 2018-10-03 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
TWI626742B (zh) * 2015-06-18 2018-06-11 台達電子工業股份有限公司 半導體裝置
CN106935640A (zh) * 2015-12-31 2017-07-07 北京大学 高电子迁移率晶体管和存储器芯片
US10932684B2 (en) * 2016-03-10 2021-03-02 Epitronic Holdings Pte Ltd. Microelectronic sensor for air quality monitoring
US9812562B1 (en) * 2016-06-03 2017-11-07 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure, HEMT structure and method of forming the same
US10741682B2 (en) 2016-11-17 2020-08-11 Semiconductor Components Industries, Llc High-electron-mobility transistor (HEMT) semiconductor devices with reduced dynamic resistance
US20190263125A1 (en) * 2017-01-31 2019-08-29 Hewlett-Packard Development Company, L.P. Atomic layer deposition oxide layers in fluid ejection devices
CN109659361B (zh) 2017-10-12 2022-03-04 电力集成公司 用于异质结器件的栅极堆叠体
TWI748233B (zh) * 2018-08-29 2021-12-01 美商高效電源轉換公司 具有降低導通電阻之橫向功率元件
TWI725433B (zh) * 2019-05-24 2021-04-21 大陸商聚力成半導體(重慶)有限公司 半導體裝置的製作方法
TWI753759B (zh) * 2020-02-03 2022-01-21 美商應用材料股份有限公司 具有整合化氮化鋁種晶或波導層的超導奈米線單光子偵測器
US20220336600A1 (en) * 2021-04-20 2022-10-20 Taiwan Semiconductor Manufacturing Co., Ltd. Ohmic electrode for two-dimensional carrier gas (2dcg) semiconductor device

Family Cites Families (167)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL167277C (nl) 1970-08-29 1981-11-16 Philips Nv Halfgeleiderinrichting met een plaatvorming half- geleiderlichaam met over althans een deel van de dikte van het halfgeleiderlichaam afgeschuinde randen, dat is voorzien van een metalen elektrode die een gelijkrichtende overgang vormt met het halfgeleider- lichaam en werkwijze ter vervaardiging van de halfgeleiderinrichting.
US4142195A (en) 1976-03-22 1979-02-27 Rca Corporation Schottky barrier semiconductor device and method of making same
US4408216A (en) 1978-06-02 1983-10-04 International Rectifier Corporation Schottky device and method of manufacture using palladium and platinum intermetallic alloys and titanium barrier for low reverse leakage over wide temperature range
NL184551C (nl) 1978-07-24 1989-08-16 Philips Nv Veldeffekttransistor met geisoleerde stuurelektrode.
FR2517883A1 (fr) 1981-12-09 1983-06-10 Thomson Csf Dispositif semi-conducteur a faible capacite parasite muni de connexions externes prises au moyen de poutres
US4543595A (en) 1982-05-20 1985-09-24 Fairchild Camera And Instrument Corporation Bipolar memory cell
GB2137412B (en) 1983-03-15 1987-03-04 Standard Telephones Cables Ltd Semiconductor device
US4967243A (en) 1988-07-19 1990-10-30 General Electric Company Power transistor structure with high speed integral antiparallel Schottky diode
US4946547A (en) 1989-10-13 1990-08-07 Cree Research, Inc. Method of preparing silicon carbide surfaces for crystal growth
US5200022A (en) 1990-10-03 1993-04-06 Cree Research, Inc. Method of improving mechanically prepared substrate surfaces of alpha silicon carbide for deposition of beta silicon carbide thereon and resulting product
EP0576566B1 (en) 1991-03-18 1999-05-26 Trustees Of Boston University A method for the preparation and doping of highly insulating monocrystalline gallium nitride thin films
US5221413A (en) 1991-04-24 1993-06-22 At&T Bell Laboratories Method for making low defect density semiconductor heterostructure and devices made thereby
CA2120610C (en) 1992-08-07 1999-03-02 Hideaki Imai Nitride based semiconductor device and manufacture thereof
DE69433926T2 (de) 1993-04-28 2005-07-21 Nichia Corp., Anan Halbleitervorrichtung aus einer galliumnitridartigen III-V-Halbleiterverbindung
DE69531849T2 (de) 1994-05-30 2004-08-05 Canon K.K. Wiederaufladbare Lithiumbatterie
JP3495814B2 (ja) 1994-05-30 2004-02-09 キヤノン株式会社 電池用電極及び該電極を有するリチウム二次電池
US6078090A (en) 1997-04-02 2000-06-20 Siliconix Incorporated Trench-gated Schottky diode with integral clamping diode
WO1996041906A1 (en) 1995-06-13 1996-12-27 Advanced Technology Materials, Inc. Bulk single crystal gallium nitride and method of making same
US5689128A (en) 1995-08-21 1997-11-18 Siliconix Incorporated High density trenched DMOS transistor
US5874747A (en) 1996-02-05 1999-02-23 Advanced Technology Materials, Inc. High brightness electroluminescent device emitting in the green to ultraviolet spectrum and method of making the same
JP3742144B2 (ja) 1996-05-08 2006-02-01 ソニー株式会社 非水電解液二次電池及び非水電解液二次電池用の平面状集電体
US5612567A (en) 1996-05-13 1997-03-18 North Carolina State University Schottky barrier rectifiers and methods of forming same
JP3326371B2 (ja) * 1996-10-21 2002-09-24 東芝電子エンジニアリング株式会社 化合物半導体装置の製造方法
US5741724A (en) 1996-12-27 1998-04-21 Motorola Method of growing gallium nitride on a spinel substrate
JP3491492B2 (ja) 1997-04-09 2004-01-26 松下電器産業株式会社 窒化ガリウム結晶の製造方法
US5785606A (en) 1997-05-02 1998-07-28 Marquez; Ruben L. Method of playing multiple hand card game
US6239033B1 (en) 1998-05-28 2001-05-29 Sony Corporation Manufacturing method of semiconductor device
DE19723176C1 (de) 1997-06-03 1998-08-27 Daimler Benz Ag Leistungshalbleiter-Bauelement und Verfahren zu dessen Herstellung
JP2002511831A (ja) 1997-07-03 2002-04-16 シービーエル テクノロジーズ エピタキシャル蒸着により自立形基板を形成する熱的不整合の補償
JP3505357B2 (ja) 1997-07-16 2004-03-08 株式会社東芝 窒化ガリウム系半導体素子およびその製造方法
JP4453111B2 (ja) 1997-10-27 2010-04-21 三菱化学株式会社 負極材料とその製造方法、負極活物質、および非水系二次電池
JP3500281B2 (ja) 1997-11-05 2004-02-23 株式会社東芝 窒化ガリウム系半導体素子およびその製造方法
JP3036495B2 (ja) 1997-11-07 2000-04-24 豊田合成株式会社 窒化ガリウム系化合物半導体の製造方法
US6608327B1 (en) 1998-02-27 2003-08-19 North Carolina State University Gallium nitride semiconductor structure including laterally offset patterned layers
JP2948205B1 (ja) 1998-05-25 1999-09-13 花王株式会社 二次電池用負極の製造方法
JP4352473B2 (ja) 1998-06-26 2009-10-28 ソニー株式会社 半導体装置の製造方法
JP2000150535A (ja) 1998-11-09 2000-05-30 Fujitsu Quantum Device Kk 電界効果トランジスタとその製造方法
US6331450B1 (en) 1998-12-22 2001-12-18 Toyoda Gosei Co., Ltd. Method of manufacturing semiconductor device using group III nitride compound
US6252288B1 (en) 1999-01-19 2001-06-26 Rockwell Science Center, Llc High power trench-based rectifier with improved reverse breakdown characteristic
US20010001494A1 (en) 1999-04-01 2001-05-24 Christopher B. Kocon Power trench mos-gated device and process for forming same
US6389051B1 (en) 1999-04-09 2002-05-14 Xerox Corporation Structure and method for asymmetric waveguide nitride laser diode
US7084456B2 (en) 1999-05-25 2006-08-01 Advanced Analogic Technologies, Inc. Trench MOSFET with recessed clamping diode using graded doping
US6291298B1 (en) 1999-05-25 2001-09-18 Advanced Analogic Technologies, Inc. Process of manufacturing Trench gate semiconductor device having gate oxide layer with multiple thicknesses
US6252258B1 (en) 1999-08-10 2001-06-26 Rockwell Science Center Llc High power rectifier
US6211018B1 (en) 1999-08-14 2001-04-03 Electronics And Telecommunications Research Institute Method for fabricating high density trench gate type power device
JP4412827B2 (ja) 1999-08-20 2010-02-10 シャープ株式会社 窒化物半導体厚膜基板
EP1231653B1 (en) 1999-10-22 2010-12-08 Sanyo Electric Co., Ltd. Electrode for lithium cell and lithium secondary cell
US6685804B1 (en) 1999-10-22 2004-02-03 Sanyo Electric Co., Ltd. Method for fabricating electrode for rechargeable lithium battery
JP2002083594A (ja) 1999-10-22 2002-03-22 Sanyo Electric Co Ltd リチウム電池用電極並びにこれを用いたリチウム電池及びリチウム二次電池
US6184570B1 (en) 1999-10-28 2001-02-06 Ericsson Inc. Integrated circuit dies including thermal stress reducing grooves and microelectronic packages utilizing the same
WO2001043174A2 (en) 1999-12-13 2001-06-14 North Carolina State University Fabrication of gallium nitride layers on textured silicon substrates
US6380108B1 (en) 1999-12-21 2002-04-30 North Carolina State University Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on weak posts, and gallium nitride semiconductor structures fabricated thereby
US6573537B1 (en) 1999-12-22 2003-06-03 Lumileds Lighting, U.S., Llc Highly reflective ohmic contacts to III-nitride flip-chip LEDs
US6586781B2 (en) 2000-02-04 2003-07-01 Cree Lighting Company Group III nitride based FETs and HEMTs with reduced trapping and method for producing the same
KR100348269B1 (ko) 2000-03-22 2002-08-09 엘지전자 주식회사 루데니움 산화물을 이용한 쇼트키 콘택 방법
JP2001357855A (ja) 2000-06-14 2001-12-26 Shin Kobe Electric Mach Co Ltd 非水電解液二次電池
US6344665B1 (en) 2000-06-23 2002-02-05 Arima Optoelectronics Corp. Electrode structure of compound semiconductor device
US20020015833A1 (en) 2000-06-29 2002-02-07 Naotomi Takahashi Manufacturing method of electrodeposited copper foil and electrodeposited copper foil
JP4022708B2 (ja) 2000-06-29 2007-12-19 日本電気株式会社 半導体装置
JP2003101036A (ja) 2001-09-25 2003-04-04 Sanyo Electric Co Ltd ショットキーバリアダイオードおよびその製造方法
JP2002064201A (ja) 2000-08-18 2002-02-28 Toshiba Corp 半導体電界効果トランジスタ及び電力増幅器
US6518079B2 (en) 2000-12-20 2003-02-11 Lumileds Lighting, U.S., Llc Separation method for gallium nitride devices on lattice-mismatched substrates
JP2002305309A (ja) 2001-02-01 2002-10-18 Hitachi Ltd 半導体装置およびその製造方法
JP4073176B2 (ja) 2001-04-02 2008-04-09 新電元工業株式会社 半導体装置およびその製造方法
US6437374B1 (en) 2001-05-07 2002-08-20 Xerox Corporation Semiconductor device and method of forming a semiconductor device
TW492202B (en) 2001-06-05 2002-06-21 South Epitaxy Corp Structure of III-V light emitting diode (LED) arranged in flip chip configuration having structure for preventing electrostatic discharge
US20020197835A1 (en) 2001-06-06 2002-12-26 Sey-Ping Sun Anti-reflective coating and methods of making the same
US20030015708A1 (en) 2001-07-23 2003-01-23 Primit Parikh Gallium nitride based diodes with low forward voltage and low reverse current operation
CA2454269C (en) 2001-07-24 2015-07-07 Primit Parikh Insulating gate algan/gan hemt
US6524900B2 (en) 2001-07-25 2003-02-25 Abb Research, Ltd Method concerning a junction barrier Schottky diode, such a diode and use thereof
US20050179106A1 (en) 2001-07-27 2005-08-18 Sanyo Electric Company, Ltd. Schottky barrier diode
JP4064085B2 (ja) 2001-10-18 2008-03-19 三菱電機株式会社 半導体装置及びその製造方法
US6768146B2 (en) 2001-11-27 2004-07-27 The Furukawa Electric Co., Ltd. III-V nitride semiconductor device, and protection element and power conversion apparatus using the same
JP3871607B2 (ja) 2001-12-14 2007-01-24 松下電器産業株式会社 半導体素子およびその製造方法
US6515308B1 (en) 2001-12-21 2003-02-04 Xerox Corporation Nitride-based VCSEL or light emitting diode with p-n tunnel junction current injection
US6855970B2 (en) 2002-03-25 2005-02-15 Kabushiki Kaisha Toshiba High-breakdown-voltage semiconductor device
US6624444B1 (en) 2002-03-28 2003-09-23 Intel Corporation Electrical-optical package with capacitor DC shunts and associated methods
DE10217235A1 (de) 2002-04-18 2003-10-30 Philips Intellectual Property Schaltungsanordnung zur Erzeugung von Gleichspannungen
JP4221697B2 (ja) 2002-06-17 2009-02-12 日本電気株式会社 半導体装置
US7323402B2 (en) 2002-07-11 2008-01-29 International Rectifier Corporation Trench Schottky barrier diode with differential oxide thickness
JP3790500B2 (ja) 2002-07-16 2006-06-28 ユーディナデバイス株式会社 電界効果トランジスタ及びその製造方法
US20040021152A1 (en) 2002-08-05 2004-02-05 Chanh Nguyen Ga/A1GaN Heterostructure Field Effect Transistor with dielectric recessed gate
JP2004087587A (ja) 2002-08-23 2004-03-18 Mitsubishi Electric Corp 窒化物半導体装置およびその製造方法
FR2844099B1 (fr) 2002-09-03 2005-09-02 Commissariat Energie Atomique Dispositif semiconducteur de puissance quasi-vertical sur substrat composite
US7115896B2 (en) 2002-12-04 2006-10-03 Emcore Corporation Semiconductor structures for gallium nitride-based devices
JP4748498B2 (ja) 2002-12-05 2011-08-17 古河電気工業株式会社 電流遮断器付きＧａＮ系半導体装置
TWI240434B (en) 2003-06-24 2005-09-21 Osram Opto Semiconductors Gmbh Method to produce semiconductor-chips
FR2857982B1 (fr) 2003-07-24 2007-05-18 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
KR100690413B1 (ko) 2003-08-12 2007-03-12 니폰덴신뎅와 가부시키가이샤 질화물 반도체 성장용 기판
US7109551B2 (en) 2003-08-29 2006-09-19 Fuji Electric Holdings Co., Ltd. Semiconductor device
US7026665B1 (en) 2003-09-19 2006-04-11 Rf Micro Devices, Inc. High voltage GaN-based transistor structure
US7041579B2 (en) 2003-10-22 2006-05-09 Northrop Grumman Corporation Hard substrate wafer sawing process
JP2005129696A (ja) 2003-10-23 2005-05-19 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP4288592B2 (ja) 2004-01-20 2009-07-01 ソニー株式会社 電池
JP4449467B2 (ja) 2004-01-28 2010-04-14 サンケン電気株式会社 半導体装置
US7253015B2 (en) 2004-02-17 2007-08-07 Velox Semiconductor Corporation Low doped layer for nitride-based semiconductor device
US7084475B2 (en) 2004-02-17 2006-08-01 Velox Semiconductor Corporation Lateral conduction Schottky diode with plural mesas
JP4610207B2 (ja) 2004-02-24 2011-01-12 三洋電機株式会社 半導体装置およびその製造方法
US7229866B2 (en) 2004-03-15 2007-06-12 Velox Semiconductor Corporation Non-activated guard ring for semiconductor devices
CN101901858B (zh) 2004-04-28 2014-01-29 沃提科尔公司 垂直结构半导体器件
JP4398780B2 (ja) 2004-04-30 2010-01-13 古河電気工業株式会社 ＧａＮ系半導体装置
US20050277292A1 (en) 2004-05-28 2005-12-15 Chao-Hsien Peng Method for fabricating low resistivity barrier for copper interconnect
US7417266B1 (en) 2004-06-10 2008-08-26 Qspeed Semiconductor Inc. MOSFET having a JFET embedded as a body diode
US7238976B1 (en) 2004-06-15 2007-07-03 Qspeed Semiconductor Inc. Schottky barrier rectifier and method of manufacturing the same
US7118970B2 (en) 2004-06-22 2006-10-10 Cree, Inc. Methods of fabricating silicon carbide devices with hybrid well regions
EP2273553B1 (en) 2004-06-30 2020-02-12 IMEC vzw A method for fabricating AlGaN/GaN HEMT devices
US7547928B2 (en) 2004-06-30 2009-06-16 Interuniversitair Microelektronica Centrum (Imec) AlGaN/GaN high electron mobility transistor devices
JP2006100645A (ja) 2004-09-30 2006-04-13 Furukawa Electric Co Ltd:The ＧａＮ系半導体集積回路
KR100889362B1 (ko) * 2004-10-19 2009-03-18 삼성전자주식회사 다층 유전체막으로 이루어진 트랜지스터 및 그 제조 방법
US7456443B2 (en) 2004-11-23 2008-11-25 Cree, Inc. Transistors having buried n-type and p-type regions beneath the source region
JP4609048B2 (ja) 2004-11-25 2011-01-12 ソニー株式会社 二次電池用負極および二次電池
US7116567B2 (en) 2005-01-05 2006-10-03 Velox Semiconductor Corporation GaN semiconductor based voltage conversion device
US7436039B2 (en) 2005-01-06 2008-10-14 Velox Semiconductor Corporation Gallium nitride semiconductor device
US20060151868A1 (en) 2005-01-10 2006-07-13 Zhu Tinggang Package for gallium nitride semiconductor devices
US7429534B2 (en) 2005-02-22 2008-09-30 Sensor Electronic Technology, Inc. Etching a nitride-based heterostructure
JP2006245317A (ja) 2005-03-03 2006-09-14 Fujitsu Ltd 半導体装置およびその製造方法
DE102005012217B4 (de) 2005-03-15 2007-02-22 Infineon Technologies Austria Ag Lateraler MISFET und Verfahren zur Herstellung desselben
JP4912604B2 (ja) 2005-03-30 2012-04-11 住友電工デバイス・イノベーション株式会社 窒化物半導体ｈｅｍｔおよびその製造方法。
US7615774B2 (en) 2005-04-29 2009-11-10 Cree.Inc. Aluminum free group III-nitride based high electron mobility transistors
US8482035B2 (en) 2005-07-29 2013-07-09 International Rectifier Corporation Enhancement mode III-nitride transistors with single gate Dielectric structure
EP2312634B1 (en) 2005-09-07 2019-12-25 Cree, Inc. Transistors with fluorine treatment
US8026568B2 (en) 2005-11-15 2011-09-27 Velox Semiconductor Corporation Second Schottky contact metal layer to improve GaN Schottky diode performance
US7696598B2 (en) 2005-12-27 2010-04-13 Qspeed Semiconductor Inc. Ultrafast recovery diode
CN101361194B (zh) 2005-12-27 2010-12-22 美商科斯德半导体股份有限公司 用于快速恢复整流器结构的装置及方法
US7592211B2 (en) 2006-01-17 2009-09-22 Cree, Inc. Methods of fabricating transistors including supported gate electrodes
JP4705482B2 (ja) * 2006-01-27 2011-06-22 パナソニック株式会社 トランジスタ
US7964514B2 (en) 2006-03-02 2011-06-21 Applied Materials, Inc. Multiple nitrogen plasma treatments for thin SiON dielectrics
JP5231719B2 (ja) 2006-03-30 2013-07-10 富士通株式会社 電界効果トランジスタの製造方法
JP5032145B2 (ja) 2006-04-14 2012-09-26 株式会社東芝 半導体装置
US8399911B2 (en) 2006-06-07 2013-03-19 Imec Enhancement mode field effect device and the method of production thereof
WO2008012877A1 (fr) 2006-07-26 2008-01-31 Fujitsu Limited DISPOSITIF À SEMI-CONDUCTEURS COMPOSÉ EMPLOYANT UN SUBSTRAT DE SiC ET PROCÉDÉ POUR PRODUIRE CELUI-CI
US7939853B2 (en) 2007-03-20 2011-05-10 Power Integrations, Inc. Termination and contact structures for a high voltage GaN-based heterojunction transistor
JP5242068B2 (ja) * 2007-03-23 2013-07-24 古河電気工業株式会社 ＧａＮ系半導体デバイスおよびその製造方法
EP2176880A1 (en) 2007-07-20 2010-04-21 Imec Damascene contacts on iii-v cmos devices
JP2009032796A (ja) 2007-07-25 2009-02-12 Rohm Co Ltd 窒化物半導体素子および窒化物半導体素子の製造方法
US20090278233A1 (en) 2007-07-26 2009-11-12 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
JP4584293B2 (ja) 2007-08-31 2010-11-17 富士通株式会社 窒化物半導体装置、ドハティ増幅器、ドレイン電圧制御増幅器
CN100594591C (zh) 2007-10-17 2010-03-17 中国科学院微电子研究所 一种提高氮化镓基场效应晶体管性能的方法
CN101459080B (zh) 2007-12-12 2010-04-14 中国科学院微电子研究所 一种制作氮化镓基场效应晶体管的方法
FR2926672B1 (fr) 2008-01-21 2010-03-26 Soitec Silicon On Insulator Procede de fabrication de couches de materiau epitaxie
US8309987B2 (en) 2008-07-15 2012-11-13 Imec Enhancement mode semiconductor device
US7985986B2 (en) 2008-07-31 2011-07-26 Cree, Inc. Normally-off semiconductor devices
US8765508B2 (en) 2008-08-27 2014-07-01 Soitec Methods of fabricating semiconductor structures or devices using layers of semiconductor material having selected or controlled lattice parameters
US8168486B2 (en) 2009-06-24 2012-05-01 Intersil Americas Inc. Methods for manufacturing enhancement-mode HEMTs with self-aligned field plate
WO2010151721A1 (en) 2009-06-25 2010-12-29 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Transistor with enhanced channel charge inducing material layer and threshold voltage control
US9991360B2 (en) * 2009-06-26 2018-06-05 Cornell University Method for forming III-V semiconductor structures including aluminum-silicon nitride passivation
CN102484070B (zh) * 2009-06-26 2014-12-10 康奈尔大学 用于铝-硅氮化物的化学气相沉积处理
EP2317542B1 (en) 2009-10-30 2018-05-23 IMEC vzw Semiconductor device and method of manufacturing thereof
US9105703B2 (en) * 2010-03-22 2015-08-11 International Rectifier Corporation Programmable III-nitride transistor with aluminum-doped gate
JP5635803B2 (ja) 2010-05-07 2014-12-03 トランスフォーム・ジャパン株式会社 化合物半導体装置の製造方法及び化合物半導体装置
CN102576727B (zh) * 2010-06-23 2016-01-27 康奈尔大学 门控iii-v半导体结构和方法
EP2610898B1 (en) * 2010-08-25 2020-11-25 NGK Insulators, Ltd. Method for fabricating epitaxial substrate for semiconductor device, and method for fabricating semiconductor device
JP5758132B2 (ja) * 2011-01-26 2015-08-05 株式会社東芝 半導体素子
JP5648523B2 (ja) 2011-02-16 2015-01-07 富士通株式会社 半導体装置、電源装置、増幅器及び半導体装置の製造方法
US9076853B2 (en) * 2011-03-18 2015-07-07 International Rectifie Corporation High voltage rectifier and switching circuits
US8604486B2 (en) * 2011-06-10 2013-12-10 International Rectifier Corporation Enhancement mode group III-V high electron mobility transistor (HEMT) and method for fabrication
US9070758B2 (en) * 2011-06-20 2015-06-30 Imec CMOS compatible method for manufacturing a HEMT device and the HEMT device thereof
US8633094B2 (en) 2011-12-01 2014-01-21 Power Integrations, Inc. GaN high voltage HFET with passivation plus gate dielectric multilayer structure
US8940620B2 (en) 2011-12-15 2015-01-27 Power Integrations, Inc. Composite wafer for fabrication of semiconductor devices
GB201203161D0 (en) * 2012-02-23 2012-04-11 Epigan Nv A device comprising a III-N layer stack with improved passivation layer and associated manufacturing method
CN102723358B (zh) * 2012-05-30 2015-01-07 苏州能讯高能半导体有限公司 绝缘栅场效应晶体管及其制造方法
US8803246B2 (en) * 2012-07-16 2014-08-12 Transphorm Inc. Semiconductor electronic components with integrated current limiters
US20140077266A1 (en) 2012-09-14 2014-03-20 Power Integrations, Inc. Heterostructure Transistor with Multiple Gate Dielectric Layers
CN102856370B (zh) * 2012-09-18 2016-04-13 苏州晶湛半导体有限公司 一种增强型开关器件
US8913972B2 (en) 2012-10-11 2014-12-16 Nokia Siemens Networks Oy Antenna clustering for multi-antenna aperture selection
US8928037B2 (en) 2013-02-28 2015-01-06 Power Integrations, Inc. Heterostructure power transistor with AlSiN passivation layer
US20150235209A1 (en) 2014-02-19 2015-08-20 Bank Of America Corporation Location based transaction liability allocation

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI608568B (zh) * 2015-08-29 2017-12-11 台灣積體電路製造股份有限公司 半導體元件與其製作方法
TWI669820B (zh) * 2017-02-20 2019-08-21 日商闊斯泰股份有限公司 氮化物半導體基板以及氮化物半導體基板的製造方法
US10593790B2 (en) 2017-02-20 2020-03-17 Coorstek Kk Nitride semiconductor substrate and method for manufacturing the same
TWI765974B (zh) * 2017-02-26 2022-06-01 日商住友化學股份有限公司 半導體基板、電子裝置、半導體基板之檢查方法及電子裝置之製造方法
TWI762346B (zh) * 2021-06-04 2022-04-21 瑞礱科技股份有限公司 一種iii族氮化物半導體元件之歐姆接觸製造方法

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