TW201427014A - Semiconductor device - Google Patents

Abstract

A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween. The multilayer film has a shape having a first angle between a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film and a second angle between a bottom surface of the oxide film and a side surface of the oxide film. The first angle is acute and smaller than the second angle. Further, a semiconductor device including such a transistor is manufactured.

Description

Semiconductor device

The present invention relates to a semiconductor device and a method of fabricating the same.

Further, in the present specification, the semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and the electro-optical device, the semiconductor circuit, and the electronic device are all semiconductor devices.

A technique of forming a crystal using a semiconductor film formed on a substrate having an insulating surface has been attracting attention. This transistor is widely used in semiconductor devices such as integrated circuits or display devices. As a semiconductor film which can be applied to a transistor, a ruthenium film is known.

Regarding the ruthenium film used for the semiconductor film of the transistor, an amorphous ruthenium film or a polycrystalline ruthenium film is used depending on the application. For example, when applied to a transistor constituting a large-sized display device, it is preferable to use an amorphous germanium film in which a technique of forming a film on a large-area substrate has been established. On the other hand, when applied to a transistor constituting a highly functional display device in which a driving circuit is integrally formed, it is preferable to use a transistor capable of manufacturing a high field-effect mobility. Polycrystalline tantalum film. Regarding the polycrystalline ruthenium film, a method of forming an amorphous ruthenium film by heat treatment at a high temperature or laser treatment is known.

Further, oxide semiconductor films have been attracting attention in recent years. For example, a transistor using an oxide semiconductor film containing indium, gallium, and zinc having a carrier density of less than 10 ¹⁸ /cm ³ is disclosed (refer to Patent Document 1).

Since the oxide semiconductor film can be formed by a sputtering method, it can be applied to a transistor constituting a large display device. In addition, the transistor using the oxide semiconductor film has a high field-effect mobility, and thus it is possible to realize a highly functional display device in which a driving circuit is formed together. In addition, since it can be utilized by improving a part of the production apparatus of the transistor using the amorphous germanium film, it is advantageous in that it can suppress equipment investment.

Further, it is known that a transistor using an oxide semiconductor film has an extremely small leakage current (also referred to as an off-state current) in an off state. For example, a low-power CPU or the like to which a low leakage characteristic of a transistor using an oxide semiconductor film is applied is disclosed (see Patent Document 2).

[Patent Document 1] Japanese Patent Application Publication No. 2006-165528

[Patent Document 2] US Patent Application Publication No. 2012/0032730

A transistor using an oxide semiconductor film is defective in the oxide semiconductor film, and the oxide semiconductor film is in contact with Defects generated at the interface between the insulating films, the electrical characteristics of the transistors become poor. In addition, as the application range of the transistor using the oxide semiconductor film is expanded, the requirements for reliability are also diversified.

Thus, one of the problems to be solved by one embodiment of the present invention is to impart stable electrical characteristics to a transistor using an oxide semiconductor film. Further, one of the problems to be solved by one embodiment of the present invention is to impart excellent electrical characteristics to a transistor using an oxide semiconductor film. Further, one of the problems to be solved by one aspect of the present invention is to provide a highly reliable semiconductor device having the transistor.

One aspect of the invention is a semiconductor device comprising: a multilayer film in which an oxide semiconductor film and an oxide film are laminated; a gate electrode; and a gate insulating film, the multilayer film is bonded via a gate insulating film The gate electrode is provided in an overlapping manner, and the multilayer film has a shape having a first angle of a lower surface of the oxide semiconductor film and a side surface of the oxide semiconductor film, and a lower surface of the oxide film and a side surface of the oxide film. The second angle is presented, and the first angle is less than the second angle and the first angle is an acute angle.

In the above semiconductor device, the upper end of the oxide semiconductor film substantially coincides with the lower end of the oxide film in the multilayer film. Further, in the multilayer film, an oxide film may be laminated on the oxide semiconductor film, or an oxide film may be laminated on both the upper and lower sides of the oxide semiconductor film.

In the above semiconductor device, the first angle and the second angle It is preferably 10° or more and less than 90°.

In the above semiconductor device, it is preferable that the oxide film contains an element common to the oxide semiconductor film, and the energy of the conduction band bottom of the oxide film is closer to the vacuum level than the oxide semiconductor film. For example, it is preferable that the oxide semiconductor film and the oxide film are In-M-Zn oxide (M is Al, Ga, Ge, Y, Zr, Sn, La, Ce or Nd), and the oxide film The atomic ratio of In to M is smaller than that of the oxide semiconductor film.

In the above semiconductor device, it is preferable that the oxide film is amorphous, the oxide semiconductor film is crystalline, and the c-axis of the crystal portion included in the oxide semiconductor film is parallel to the oxide semiconductor film. The normal vector of the surface.

In the above semiconductor device, the source electrode and the drain electrode are provided in contact with the multilayer film, and a low resistance region is provided in a region in the vicinity of the interface in which the multilayer film is in contact with the source electrode and the drain electrode.

Further, in the above semiconductor device, an oxide film having the same or different composition as that of the oxide film may be provided in contact with the source electrode and the drain electrode and the upper surface of the multilayer film.

According to one aspect of the present invention, it is possible to impart stable electrical characteristics to a transistor by using a multilayer film including an oxide film and an oxide semiconductor film.

Further, by setting the shape of the multilayer film to a tapered shape having at least a first angle and a second angle larger than the first angle, the oxide semiconductor film as the channel region and the source electrode and the drain electrode can be enlarged. Contact area between and can make the on-state current of the transistor (on-state Current) increases.

Further, according to an aspect of the present invention, it is possible to provide a semiconductor device having high reliability of the above-described transistor.

100‧‧‧Substrate

104‧‧‧gate electrode

106‧‧‧Multilayer film

106a‧‧‧Oxide semiconductor film

106b‧‧‧Oxide film

106c‧‧‧low resistance zone

106d‧‧‧Low resistance zone

107‧‧‧Oxide film

112‧‧‧gate insulating film

113‧‧‧ steps

116a‧‧‧Source electrode

116b‧‧‧汲electrode

117‧‧‧Oxide film

118‧‧‧Protective insulation film

118a‧‧‧Oxide film

118b‧‧‧Oxide film

118c‧‧‧ nitride film

126a‧‧‧Oxide semiconductor film

126b‧‧‧Oxide film

200‧‧‧Substrate

202‧‧‧Base insulating film

204‧‧‧gate electrode

206‧‧‧Multilayer film

206a‧‧‧Oxide semiconductor film

206b‧‧‧Oxide film

206c‧‧‧Oxide film

206d‧‧‧low resistance zone

206e‧‧‧Low resistance zone

207‧‧‧Oxide film

212‧‧‧Gate insulation film

212a‧‧‧ source electrode

212b‧‧‧汲electrode

213‧‧ steps

214‧‧‧ steps

216a‧‧‧ source electrode

216b‧‧‧汲electrode

216c‧‧‧electrode

218‧‧‧Protective insulation film

226a‧‧‧Oxide semiconductor film

226b‧‧‧Oxide film

226c‧‧‧Oxide film

260‧‧‧Semiconductor film

401‧‧‧Semiconductor substrate

403‧‧‧Component separation zone

407‧‧‧gate insulating film

409‧‧‧gate electrode

411a‧‧‧ impurity area

411b‧‧‧ impurity area

415‧‧‧Insulation film

417‧‧‧Insulation film

419‧‧‧Optoelectronics

419a‧‧‧Contact plug

419b‧‧‧Contact plug

420‧‧‧Insulation film

421‧‧‧Insulation film

422‧‧‧Insulation film

423a‧‧‧Wiring

423b‧‧‧Wiring

424‧‧‧electrode

425‧‧‧Insulation film

445‧‧‧Insulation film

449‧‧‧Wiring

456‧‧‧Wiring

500‧‧‧Microcomputer

501‧‧‧DC power supply

502‧‧ ‧ busbar

503‧‧‧Power Gate Controller

504‧‧‧Power Gate

505‧‧‧CPU

506‧‧‧Volatile Memory Department

507‧‧‧ Non-volatile memory

508‧‧" interface

509‧‧‧Detection Department

511‧‧‧Light sensor

512‧‧Amplifier

513‧‧‧AD converter

514‧‧‧ photoelectric conversion components

517‧‧‧Optoelectronics

519‧‧‧Optoelectronics

530‧‧‧Lighting elements

700‧‧‧Substrate

719‧‧‧Lighting elements

720‧‧‧Insulation film

721‧‧‧Insulation film

731‧‧‧ terminals

732‧‧‧FPC

733a‧‧‧Wiring

733b‧‧‧Wiring

733c‧‧‧Wiring

734‧‧‧ Sealing material

735‧‧‧Drive circuit

736‧‧‧Drive circuit

737‧‧ ‧ pixels

741‧‧‧Optoelectronics

742‧‧‧ capacitor

743‧‧‧Switching elements

744‧‧‧ signal line

750 ‧ ‧ pixels

751‧‧‧Optoelectronics

752‧‧‧ capacitor

753‧‧‧Liquid Crystal Components

754‧‧‧ scan line

755‧‧‧ signal line

781‧‧‧electrode

782‧‧‧Lighting layer

783‧‧‧electrode

784‧‧‧ partition wall

785a‧‧‧ middle layer

785b‧‧‧ middle layer

785c‧‧‧ middle layer

785d‧‧‧ middle layer

786a‧‧‧Lighting layer

786b‧‧‧Lighting layer

786c‧‧‧Lighting layer

791‧‧‧electrode

792‧‧‧Insulation film

793‧‧‧Liquid layer

794‧‧‧Insulation film

795‧‧‧Separators

796‧‧‧electrode

797‧‧‧Substrate

801‧‧‧ glass substrate

803‧‧‧In-Ga-Zn oxide film

805‧‧‧In-Ga-Zn oxide film

807‧‧‧ photoresist

811‧‧‧ glass substrate

813‧‧‧In-Ga-Zn oxide film

815‧‧‧In-Ga-Zn oxide film

817‧‧‧ photoresist

821‧‧‧ nitride film

823‧‧‧Oxynitride film

825‧‧‧Oxide semiconductor film

826‧‧‧ film

827‧‧‧Oxynitride film

829‧‧‧Low-density area

831‧‧‧ glass substrate

833‧‧‧Oxynitride film

835‧‧‧Oxide semiconductor film

837‧‧‧Oxynitride film

1141‧‧‧Switching components

1142‧‧‧ memory unit

1143‧‧‧Memory unit group

1189‧‧‧ROM interface

1190‧‧‧Substrate

1191‧‧‧ALU

1192‧‧‧ALU controller

1193‧‧‧ instruction decoder

1194‧‧‧Interrupt controller

1195‧‧‧ Timing controller

1196‧‧‧ register

1197‧‧‧ register controller

1198‧‧‧ bus interface

1199‧‧‧ROM

8100‧‧‧ alarm device

8101‧‧‧Microcomputer

8200‧‧‧ indoor unit

8201‧‧‧Shell

8202‧‧‧Air outlet

8203‧‧‧CPU

8204‧‧‧Outdoor machine

8300‧‧‧Electric refrigerator

8301‧‧‧Shell

8302‧‧‧ refrigerator door

8303‧‧‧Freezer door

8304‧‧‧CPU

9700‧‧‧Electric car

9701‧‧‧Secondary battery

9702‧‧‧Control circuit

9703‧‧‧ drive

9704‧‧‧Processing device

1A to 1D are a plan view and a cross-sectional view illustrating a transistor; Fig. 2 is a cross-sectional view illustrating the transistor; Fig. 3 is a view illustrating an energy band structure of the multilayer film; and Fig. 4 is a view illustrating a multilayer film 5A to 5C are cross-sectional views illustrating a method of fabricating a transistor; FIGS. 6A and 6B are cross-sectional views illustrating a method of fabricating a transistor; and FIGS. 7A to 7D are plan views illustrating a transistor; FIG. 8A to FIG. 8C are plan views and cross-sectional views illustrating the transistor; FIG. 9 is a cross-sectional view illustrating the transistor; FIGS. 10A to 10C are diagrams illustrating the energy band structure of the multilayer film; FIGS. 11A to 11C are views A cross-sectional view illustrating a method of fabricating a transistor; FIGS. 12A and 12B are cross-sectional views illustrating a method of fabricating a transistor; FIGS. 13A to 13C are a plan view and a cross-sectional view illustrating a transistor; and FIGS. 14A to 14C are diagrams illustrating a transistor Top view and cross-sectional view; Fig. 15 is a circuit diagram showing an example of an EL display device; and Figs. 16A to 16C are views showing an example of the EL display device. 17A and 17B are cross-sectional views showing an example of an EL display device; Fig. 18 is a circuit diagram showing an example of a liquid crystal display device; and Figs. 19A to 19C are diagrams showing a liquid crystal display device. FIG. 20 is a block diagram showing an example of a semiconductor device; FIG. 21 is a cross-sectional view showing an example of a semiconductor device; and FIGS. 22A to 22C are block diagrams showing an example of a CPU; 23A to 23C are diagrams showing an example of an electronic device; FIG. 24 is a view for explaining a relationship between an etchant and an etching rate; FIGS. 25A and 25B are diagrams for explaining a STEM image; and FIG. 26 is a view for explaining a STEM image; 27A and 27B are diagrams for explaining STEM images; Figs. 28A and 28B are diagrams for explaining STEM images; Figs. 29A and 29B are diagrams for explaining STEM images; and Figs. 30A and 30B are diagrams for explaining STEM images; Fig. 31A And FIG. 31B is a view for explaining the structure of the multilayer film; and FIGS. 32A and 32B are views for explaining the structure of the multilayer film.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and as long as it is a person skilled in the art, the embodiment and details can be easily understood. Make various transformations. Further, the present invention should not be construed as being limited to the contents described in the embodiments described below. Further, when the structure of the invention is illustrated by the drawings, the component symbols representing the same object are used in common in different drawings. In addition, when representing the same target, the same hatching pattern is sometimes used, and no special mark is attached.

The ordinal numbers attached as the first, second, etc. are used for convenience, and do not indicate a process sequence or a stacking order. Further, in the present specification, the inherent name as a matter for a specific invention is not indicated.

In addition, the voltage mostly refers to a potential difference between a certain potential and a standard potential (for example, a ground potential (GND) or a source potential). Thus, the voltage can be changed to a potential.

Further, even when it is described as "electrical connection", there is a case where there is no physically connected portion in the actual circuit, and only the wiring is extended.

Further, when the current direction changes during the operation of the circuit or the like, the functions of the source and the drain may be interchanged. Therefore, in the present specification, terms such as a source and a drain may be interchanged and used.

In the present specification, "parallel" means a state in which two straight lines are arranged such that the angle formed is −10° or more and 10° or less. Therefore, the angle is also −5° or more and 5° or less. In addition, "vertical" means a state in which the two straight lines are arranged such that the angle is 80° or more and 100° or less, and therefore the angle is 85° or more and 95° or less.

In addition, in this specification, the crystal is trigonal or diamond. In the case of a square crystal, it is represented by a hexagonal system.

Further, in the present specification and the like, the configurations and contents described in the respective embodiments and the respective embodiments can be combined as appropriate.

Embodiment 1

In the present embodiment, a transistor of one embodiment of the present invention will be described.

1-1. Crystal structure (1)

1A to 1D are a plan view and a cross-sectional view showing a transistor of a BGTC structure. FIG. 1A shows a top view of a transistor. Fig. 1B shows a cross-sectional view corresponding to the chain line A1-A2 shown in Fig. 1A. Fig. 1C shows a cross-sectional view corresponding to the chain line A3-A4 shown in Fig. 1A. In addition, in FIG. 1A, in order to make the drawing clear, a part of the constituent elements of the transistor (a gate insulating film, a protective insulating film, etc.) is omitted.

The bottom gate type transistor is described in this section. Here, a transistor as a bottom gate top contact structure (BGTC structure) of a bottom gate type transistor will be described using FIGS. 1A to 1D. The transistor shown in FIG. 1B includes: a gate electrode 104 disposed on the substrate 100; a gate insulating film 112 disposed on the gate electrode 104; an oxide semiconductor film 106a including the oxide semiconductor film 106a disposed on the gate insulating film 112, and a multilayer film 106 of an oxide film 106b disposed on the oxide semiconductor film 106a; a source electrode 116a and a drain electrode 116b disposed on the gate insulating film 112 and the multilayer film 106; and a multilayer film 106 and a source electrode 116a and a protective insulating film 118 on the drain electrode 116b.

Further, depending on the type of the conductive film used for the source electrode 116a and the gate electrode 116b, the low resistance region 106c and the low portion are formed in the multilayer film 106 by taking oxygen from a portion of the multilayer film 106 or forming a mixed layer. Resistor region 106d. In FIG. 1B, the low-resistance region 106c and the low-resistance region 106d are regions in the vicinity of the interface of the multilayer film 106 in contact with the source electrode 116a and the drain electrode 116b (dashed line of the multilayer film 106 and the source electrode 116a and the drain electrode) The area between the electrodes 116b). One or all of the low resistance region 106c and the low resistance region 106d function as a source region and a drain region.

In the region overlapping the gate electrode 104 in FIG. 1A, the interval between the source electrode 116a and the drain electrode 116b is referred to as a channel length. However, in the case where the transistor includes the source region and the drain region, the interval between the low resistance region 106c and the low resistance region 106d may also be referred to as a channel length in a region overlapping the gate electrode 104.

Further, the channel formation region refers to a region overlapping the gate electrode 104 in the multilayer film 106 and sandwiched between the source electrode 116a and the drain electrode 116b (refer to FIG. 1B). In addition, the channel region refers to a region where the current mainly flows in the channel formation region. Here, the channel region is a part of the oxide semiconductor film 106a in the channel formation region.

Further, as shown in FIG. 1A, the gate electrode 104 is provided in such a manner that the multilayer film 106 is included inside the gate electrode 104 in the upper surface shape. With this arrangement, when light is incident from the side of the substrate 100, generation of carriers due to light in the multilayer film 106 can be suppressed. That is, the gate electrode 104 has a function as a light shielding film. However, it is also possible to form a multilayer film 106 until the outside of the gate electrode 104.

The lower surface of the oxide semiconductor film 106a corresponds to the surface of the oxide semiconductor film 106a on the substrate 100 side or the surface of the oxide semiconductor film 106a that is in contact with the gate insulating film 112. The lower surface of the oxide film 106b is a surface corresponding to the surface of the oxide film 106b on the substrate 100 side or a boundary surface between the oxide film 106b and the oxide semiconductor film 106a. Further, the laminated structure of the multilayer film 106 was observed by STEM (Scanning Transmission Electron Microscopy), and the boundary was confirmed. However, depending on the materials used for the oxide semiconductor film 106a and the oxide film 106b, the boundary may not be clearly confirmed.

1-1-1. Multilayer film

Hereinafter, the multilayer film 106 and the oxide semiconductor film 106a and the oxide film 106b constituting the multilayer film 106 will be described with reference to FIGS. 1A to 2 .

Fig. 2 is an enlarged view of a region surrounded by a broken line of Fig. 1B.

In the multilayer film 106, at least the oxide semiconductor film 106a has a tapered shape. Preferably, the oxide film 106b also has a tapered shape. Further, the tapered shape of the oxide semiconductor film 106a is different from the tapered shape of the oxide film 106b.

Specifically, in the oxide semiconductor film 106a, the angle between the lower surface of the oxide semiconductor film 106a and the side surface of the oxide semiconductor film 106a is referred to as a first angle θ1, and in the oxide film 106b, oxidation is performed. The lower surface of the film 106b and the side surface of the oxide film 106b The angle presented is referred to as the second angle θ2. In this case, the first angle θ1 may be an acute angle, and the second angle θ2 may be an acute angle or a vertical direction.

Preferably, the first angle θ1 and the second angle θ2 are both acute angles, and the first angle θ1 is smaller than the second angle θ2.

Further, the first angle θ1 is 10° or more and less than 90°, preferably 30° or more and 70° or less. The second angle θ2 is 10° or more and less than 90°, preferably 30° or more and 70° or less.

As described above, by setting the shape of the multilayer film 106 to a tapered shape having different taper angles, the following effects can be obtained. Regarding the multilayer film 106, by making it a tapered shape having a different taper angle, the contact area with the source electrode 116a and the drain electrode 116b can be enlarged as compared with the tapered shape having a constant taper angle. . Thereby, the contact resistance between the multilayer film 106 and the source electrode 116a and the drain electrode 116b can be lowered and the on-state current of the transistor can be increased.

In addition, by making the second angle θ2 larger than the first angle θ1, the contact area between the oxide film 106b and the source electrode 116a and the drain electrode 116b can be reduced, so that the formation in the oxide film 106b can be reduced. Low resistance zone. Thereby, it is possible to suppress the reduction in resistance of the oxide film 106b and suppress the leakage path generated between the source electrode 116a and the gate electrode 116b, and at the same time, effectively in the oxide semiconductor film 106a functioning as the channel region. A low resistance region is formed so that an increase in the on-state current of the transistor and a decrease in the off-state current of the transistor can be simultaneously achieved.

Further, the upper end of the oxide semiconductor film 106a substantially coincides with the lower end of the oxide film 106b (see FIG. 2). That is, the multilayer film The 106 has no large step 113 formed by the oxide semiconductor film 106a and the oxide film 106b (refer to FIGS. 31A and 31B). Therefore, it is possible to suppress the disconnection of the film (for example, the conductive film processed into the source electrode 116a and the drain electrode 116b) provided on the multilayer film 106, and it is possible to manufacture a transistor having excellent electrical characteristics. In addition, "the upper end of the oxide semiconductor film 106a substantially coincides with the lower end of the oxide film 106b" means that the distance L1 between the lower end of the oxide film 106b and the upper end of the oxide semiconductor film 106a is 30 nm or less, preferably 10 nm or less. (Refer to FIG. 31A and FIG. 31B).

When the multilayer film 106 is formed by etching, the above-described tapered shape can be formed by the difference in etching speed between the oxide semiconductor film 106a and the oxide film 106b. In particular, the above-described tapered shape can be formed by making the etching rate of the oxide semiconductor film 106a lower than the etching rate of the oxide film 106b.

For example, the above-described tapered shape can be formed by wet etching using a solution containing phosphoric acid as an etchant.

The advantage of forming the multilayer film 106 by wet etching is as follows. For example, when the oxide semiconductor film and the oxide film processed into the multilayer film 106 have defects such as pinholes, the oxide semiconductor film and the oxide film may be processed by dry etching. The insulating film (gate insulating film or the like) provided under the oxide semiconductor film and the oxide film is also etched by the pinhole. Thus, in the insulating film, an opening of an electrode (gate electrode or the like) provided under the insulating film may be formed. If a transistor is fabricated under such conditions, it will sometimes be manufactured. This electrode generates a transistor having a characteristic defect such as a short circuit between the electrode formed on the multilayer film 106 (source electrode, drain electrode, etc.). That is, if the multilayer film 106 is formed by dry etching, it sometimes affects the decrease in the yield of the transistor. Therefore, by forming the multilayer film 106 by wet etching, it is possible to manufacture a transistor having excellent electrical characteristics with high productivity.

In addition, since the etching rate of the wet etching varies depending on the concentration of the etchant and the temperature of the etchant, etc., it is preferable to appropriately adjust the etching rate of the oxide semiconductor film 106a to be lower than the etching rate of the oxide film 106b. . In addition, by making the second angle θ2 larger than the first angle θ1, the area exposed to the etchant in the wet etching can be reduced as much as possible. In addition, by making the second angle θ2 larger than the first angle θ1, the low-resistance region formed in the oxide film 106b due to the occurrence of contamination or defects caused by the etchant can be reduced.

For example, the etchant may be a phosphoric acid aqueous solution adjusted to about 85% or a mixed solution of phosphoric acid (72%), nitric acid (2%), and acetic acid (9.8%) (also referred to as a mixed aluminum acid solution). . Further, the temperature of the etchant is preferably room temperature or normal temperature of about 20 to 35 minutes. Further, an etchant other than the above may also be used.

The oxide semiconductor film 106a is an oxide semiconductor film containing at least indium. For example, zinc may be contained in addition to indium. Further, the oxide semiconductor film 106a preferably further contains an element M (M is Al, Ga, Ge, Y, Zr, Sn, La, Ce or Nd) in addition to ruthenium.

The oxide film 106b is an oxide film composed of one or more of the elements constituting the oxide semiconductor film 106a, and The energy of the conduction band bottom is closer to the vacuum energy level than the oxide semiconductor film 106a by 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, 0.15 eV or more, 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. At this time, when an electric field is applied to the gate electrode 104, the channel is formed in the oxide semiconductor film 106a having a lower energy at the bottom of the conduction band in the multilayer film 106. In other words, by having the oxide film 106b between the oxide semiconductor film 106a and the protective insulating film 118, the channel of the transistor can be formed in the oxide semiconductor film 106a which is not in contact with the protective insulating film 118. In addition, since the oxide film 106b is formed of one or more of the elements constituting the oxide semiconductor film 106a, interface scattering is less likely to occur between the oxide semiconductor film 106a and the oxide film 106b. Therefore, the movement of the carrier is not hindered between the oxide semiconductor film 106a and the oxide film 106b, thereby increasing the field effect mobility of the transistor. Further, the interface level is not easily formed between the oxide semiconductor film 106a and the oxide film 106b. When an interface level exists between the oxide semiconductor film 106a and the oxide film 106b, a second transistor having a different threshold voltage with the interface as a channel is sometimes formed, so that the threshold voltage in the appearance of the transistor fluctuates. Therefore, by providing the oxide film 106b, it is possible to reduce unevenness in electrical characteristics such as a critical voltage of the transistor.

For example, the oxide film 106b may contain Al, Ga, Ge, Y, Zr, Sn, La, Ce, Nd or Hf (especially Al or Ga) at a higher atomic ratio than the oxide semiconductor film 106a. Specifically, as the oxide film 106b, a ratio of atoms which is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more higher than that of the oxide semiconductor film 106a is used. An oxide film containing the above elements. Since the above elements are strongly bonded to oxygen, they have a function of suppressing generation of oxygen vacancies in the oxide film. That is, the oxide film 106b is less likely to generate oxygen vacancies than the oxide semiconductor film 106a.

For example, when the oxide semiconductor film 106a is an In-M-Zn oxide and the oxide film 106b is also set to an In-M-Zn oxide, when the oxide film 106b is set to In:M:Zn=x ₂ : y ₂ : z ₂ [atomic ratio] and the oxide semiconductor film 106a is set to In: M: Zn = x ₁ : y ₁ : z ₁ [atomic ratio], and y ₁ / x ₁ ratio is selected The oxide film 106b and the oxide semiconductor film 106a having a large y ₂ /x ₂ . Further, the element M is a metal element having a bonding strength with oxygen larger than that of In and oxygen, and examples thereof include Al, Ga, Ge, Y, Zr, Sn, La, Ce or Nd (especially Al or Ga). Wait. Preferably, the oxide film 106b and the oxide semiconductor film 106a which are y ₁ /x ₁ larger than y ₂ /x _{2 by} 1.5 times or more are selected. More preferably, the choice _{y 1 / x 1 y 2 /} x ₂ 2 times larger than the oxide film 106b and the oxide semiconductor film 106a ratio. Further preferred, the choice y ₁ / x _{1 2} 3 times greater than the oxide film 106b and the oxide semiconductor film 106a than y ₂ / x. At this time, in the oxide film 106b, if y ₂ is x ₂ or more, it is preferable to impart stable electrical characteristics to the transistor. However, if y ₂ is three times or more of x ₂ , the field effect mobility of the transistor becomes low, so that y ₂ is preferably less than three times x ₂ .

Further, when the oxide film 106b is dense, it is less likely to be damaged by plasma or the like used in the process of the transistor, and thus it is preferable to impart stable electrical characteristics to the transistor.

The thickness of the oxide film 106b is set to 3 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less. In addition, the thickness of the oxide semiconductor film 106a is set to 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably 3 nm or more and 50 nm or less.

The germanium concentration of the oxide semiconductor film 106a and the oxide film 106b will be described below. Further, in order to stabilize the electrical characteristics of the transistor, it is effective to achieve an essential or substantially essential reduction in the concentration of impurities in the oxide semiconductor film 106a. Specifically, the carrier density of the oxide semiconductor film may be set to be less than 1 × 10 ¹⁷ /cm ³ , less than 1 × 10 ¹⁵ /cm ³ or less than 1 × 10 ¹³ /cm ³ . Further, in the oxide semiconductor film, light elements, semimetal elements, metal elements and the like other than the main component (less than 1 atom%) are impurities. For example, in the oxide semiconductor film, hydrogen, nitrogen, carbon, ruthenium, osmium, titanium, and ruthenium become impurities. In order to reduce the impurity concentration in the oxide semiconductor film, it is preferable to lower the impurity concentration in the gate insulating film 112 and the oxide film 106b which are close to each other.

For example, in the case where the oxide semiconductor film 106a contains germanium, an impurity level is formed. In particular, when germanium is present between the oxide semiconductor film 106a and the oxide film 106b, the impurity level becomes a trap. Therefore, the germanium concentration between the oxide semiconductor film 106a and the oxide film 106b is set to be lower than 1 × 10 ¹⁹ atoms / cm ³ , preferably lower than 5 × 10 ¹⁸ atoms / cm ³ , more preferably lower than 2 × 10 ¹⁸ atoms/cm ³ .

Further, in the oxide semiconductor film 106a, hydrogen and nitrogen form a donor energy level, so that the carrier density is increased. The hydrogen concentration of the oxide semiconductor film 106a is 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 5 × 10 ¹⁹ atoms / cm ³ or less, in the secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry). It is 1 × 10 ¹⁹ atoms / cm ³ or less, and more preferably 5 × 10 ¹⁸ atoms / cm ³ or less. Further, the nitrogen concentration is less than 5 × 10 ¹⁹ atoms/cm ³ in the SIMS, preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, still more preferably 5 ×. 10 ¹⁷ atoms/cm ³ or less.

Moreover, in order to reduce the hydrogen concentration and the nitrogen concentration of the oxide semiconductor film 106a, it is preferable to reduce the hydrogen concentration and the nitrogen concentration of the oxide film 106b. The hydrogen concentration of the oxide film 106b is 2 × 10 ²⁰ atoms/cm ³ or less in the SIMS, preferably 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less, further preferably It is 5 × 10 ¹⁸ atoms / cm ³ or less. Further, the nitrogen concentration is less than 5 × 10 ¹⁹ atoms/cm ³ in the SIMS, preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, still more preferably 5 ×. 10 ¹⁷ atoms/cm ³ or less.

The oxide semiconductor film 106a and the oxide film 106b are amorphous or crystalline. Examples of the crystal form include a polycrystalline structure, a single crystal structure, and a crystallite structure. Further, the oxide semiconductor film 106a and the oxide film 106b may be a mixed structure in which crystal grains are dispersed in an amorphous region. Further, the crystal orientation of each crystal grain of the crystallite structure is random, and the crystal grain size of the crystallite or the mixed structure includes 0.1 nm or more and 10 nm or less, preferably 1 nm or more and 10 nm or less, more preferably 2 nm. Above and below 4 nm.

In the oxide semiconductor film 106a and the oxide film 106b, it is preferable that the oxide semiconductor film 106a is crystalline, and the oxide film 106b is amorphous or crystalline. Since the oxide semiconductor film 106a forming the channel is crystalline, it is possible to impart stable electrical characteristics to the transistor. Further, the crystalline oxide semiconductor film 106a is preferably CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor).

Further, the oxide semiconductor film 106a is preferably formed on the amorphous film. For example, it may be on the surface of the amorphous insulating film or on the surface of the amorphous semiconductor film. The oxide semiconductor film 106a of CAAC-OS can be formed on the amorphous film by using a film formation method described later.

The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal portions, and most of the crystal portions have a size that can be accommodated in a cube shorter than 100 nm on one side. Therefore, a case is also included in which the size of the crystal portion included in the CAAC-OS film is a size that can be accommodated in a cube shorter than 10 nm, shorter than 5 nm, or shorter than 3 nm. The CAAC-OS film has a low defect energy density. The CAAC-OS film will be described in detail below.

When the CAAC-OS film was observed by TEM, a clear boundary between the crystal portion and the crystal portion, that is, a grain boundary (also referred to as a grain boundary) could not be confirmed. Therefore, it can be said that the CAAC-OS film is less likely to cause a decrease in the electron mobility due to the grain boundary.

When the CAAC-OS film (cross-sectional TEM image) is observed by TEM from a direction substantially parallel to the sample surface, it can be confirmed in the crystal portion. The metal atoms are arranged in a layered shape. Each layer of the metal atom is a convex-concave shape reflecting the surface (also referred to as a formed surface) of the CAAC-OS film or the upper surface of the CAAC-OS film, and is formed on the surface or upper side parallel to the CAAC-OS film. The way the surface is arranged.

On the other hand, when the CAAC-OS film (planar TEM image) was observed by TEM from a direction substantially perpendicular to the sample surface, it was confirmed that the metal atoms were arranged in a triangular shape or a hexagonal shape in the crystal portion. However, no regularity was found in the arrangement of metal atoms between different crystal parts.

It can be seen from the cross-sectional TEM image and the planar TEM image that the crystal portion of the CAAC-OS film has an alignment property.

When the CAAC-OS film is subjected to structural analysis using an X-ray diffraction (XRD) device, for example, in the analysis of the out-of-plane method of the CAAC-OS film having crystals of InGaZnO ₄ , sometimes A peak appears near the diffraction angle (2θ) of 31°. Since the peak is attributed to the (009) plane of the InGaZnO ₄ crystal, it can be confirmed that the crystal in the CAAC-OS film has c-axis orientation, and the c-axis is oriented substantially perpendicular to the formed or upper surface of the CAAC-OS film. The direction.

On the other hand, in the analysis of the CAAC-OS film by the in-plane method in which the X-ray is incident on the sample from the direction substantially perpendicular to the c-axis, a peak appears in the vicinity of 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. As long as it is a single crystal oxide semiconductor film of InGaZnO ₄ , when 2θ is fixed at around 56° and is on the normal vector of the sample surface ( Axis) rotate the sample and analyze it ( Scanning, six peaks attributed to the crystal faces equivalent to the (110) plane are observed. On the other hand, in the case of the CAAC-OS film, even when 2θ is fixed at around 56° In the case of scanning, there is no obvious peak.

As described above, in the CAAC-OS film, although the alignment of the a-axis and the b-axis is irregular between the crystal portions, the c-axis is aligned, and the c-axis is oriented parallel to the surface to be formed or the upper surface. The direction of the vector. Therefore, each layer of the metal atoms arranged in a layer shape confirmed by the cross-sectional TEM observation is a surface parallel to the ab plane of the crystal.

Further, the crystal portion is formed when a CAAC-OS film is formed or a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is aligned in a direction parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. Thus, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film.

In addition, the degree of crystallinity in the CAAC-OS film may also be uneven. For example, when the crystal portion of the CAAC-OS film is formed by crystal growth from the vicinity of the upper surface of the CAAC-OS film, the region near the upper surface may be changed in crystallinity compared to the region near the surface to be formed. high. Further, when an impurity is added to the CAAC-OS film, the degree of crystallization of the region to which the impurity is added changes, and a region having a different degree of crystallization may be partially formed.

Further, in the analysis of the out-of-pLane method of the CAAC-OS film having InGaZnO ₄ crystal, in addition to the peak near 2θ of 31°, a peak appeared in the vicinity of 2θ of 36°. A peak in the vicinity of 2θ of 36° indicates that a part of the CAAC-OS film contains crystals having no c-axis alignment property. Preferably, the peak is shown in the CAAC-OS film at around 2θ of 31° and the peak is not shown when 2θ is around 36°.

In a transistor using CAAC-OS, variations in electrical characteristics due to irradiation of visible light or ultraviolet light are small. Therefore, the transistor has stable electrical characteristics.

In addition, since the oxide semiconductor film 106a contains a high concentration of germanium and carbon, the crystallinity of the oxide semiconductor film 106a may be lowered. In order not to lower the crystallinity of the oxide semiconductor film 106a, the germanium concentration of the oxide semiconductor film 106a is set to be less than 1 × 10 ¹⁹ atoms / cm ³ , preferably less than 5 × 10 ¹⁸ atoms / cm ³ , more preferably It is less than 2 × 10 ¹⁸ atoms/cm ³ . In addition, in order not to lower the crystallinity of the oxide semiconductor film 106a, the carbon concentration of the oxide semiconductor film 106a is set to be less than 1 × 10 ¹⁹ atoms / cm ³ , preferably less than 5 × 10 ¹⁸ atoms / cm ³ , More preferably, it is less than 2 × 10 ¹⁸ atoms / cm ³ .

In this way, in the case where the oxide semiconductor film 106a having the channel formed has high crystallinity and the energy density due to impurities or defects is small, the transistor using the multilayer film 106 has stable electrical characteristics.

The local energy level in the multilayer film 106 will be described below. By reducing the local energy density in the multilayer film 106, it is possible to impart stable electrical characteristics to the transistor using the multilayer film 106. The multilayer photo film 106 can be utilized by a constant photocurrent method (CPM: Constant Photocurrent Method). The local energy level is evaluated.

In order to impart stable electrical characteristics to the transistor, the absorption coefficient of the local energy level in the multilayer film 106 obtained by the CPM measurement is set to be less than 1 × 10 ^-3 cm ^-1 , preferably less than 3 × 10 ^-4 cm ^{-1 .} can. Further, by setting the absorption coefficient of the local energy level in the multilayer film 106 obtained by the CPM measurement to be less than 1 × 10 ^-3 cm ^-1 , preferably less than 3 × 10 ^-4 cm ^-1 , the crystal can be improved. Field efficiency movement rate. Further, in order to set the absorption coefficient of the local energy level in the multilayer film 106 obtained by the CPM measurement to be less than 1 × 10 ^-3 cm ^-1 , preferably less than 3 × 10 ^-4 cm ^-1 , it will be used as an oxide semiconductor The concentration of lanthanum, cerium, carbon, lanthanum or titanium or the like which forms a local energy element in the film 106a is set to be less than 2 × 10 ¹⁸ atoms / cm ³ , preferably less than 2 × 10 ¹⁷ atoms / cm ³ .

Further, in the CPM measurement, at each wavelength: the amount of light irradiated to the surface of the sample between the terminals is adjusted so that light is applied in a state where a voltage is applied between the electrode and the electrode provided in contact with the multilayer film 106 as a sample The current value is constant, and the absorption coefficient is derived based on the amount of illumination light. In the CPM measurement, when the sample is defective, the absorption coefficient corresponding to the energy of the energy level in which the defect exists (in terms of wavelength) increases. The defect density of the sample can be derived by multiplying the constant by the equivalent of the increase in the absorption coefficient.

It can be considered that the local energy level measured by CPM is an energy level resulting from impurities or defects. That is, it is understood that the transistor of the multilayer film 106 having a small absorption coefficient of the local energy level obtained by the CPM has stable electrical characteristics.

Hereinafter, the energy band structure of the multilayer film 106 will be described with reference to Fig. 3 .

As an example, an In-Ga-Zn oxide having an energy gap of 3.15 eV is used as the oxide semiconductor film 106a, and an In-Ga-Zn oxide having an energy gap of 3.5 eV is used as the oxide film 106b. The energy gap was measured using a spectral ellipsometer (UT-IB JOBIN YVON UT-300).

The energy difference (also referred to as free potential) between the vacuum energy level of the oxide semiconductor film 106a and the oxide film 106b and the upper end of the valence band is 8 eV and 8.2 eV, respectively. Further, the energy difference between the vacuum level and the valence band tip was measured by an ultraviolet photoelectron spectroscopy (UPS: Versa Probe).

Therefore, the energy difference (also referred to as electron affinity) between the vacuum energy level of the oxide semiconductor film 106a and the oxide film 106b and the energy of the conduction band bottom is 4.85 eV and 4.7 eV, respectively.

FIG. 3 schematically illustrates a portion of the energy band structure of the multilayer film 106. Fig. 3 is an energy band structure corresponding to the chain line A5-A6 of Fig. 2. Specifically, a case where the tantalum oxide film (the gate insulating film 112 and the protective insulating film 118) is provided in contact with each of the oxide semiconductor film 106a and the oxide film 106b has been described. Here, EcI1 represents the energy of the conduction band bottom of the ruthenium oxide film, EcS1 represents the energy of the conduction band bottom of the oxide semiconductor film 106a, EcS2 represents the energy of the conduction band bottom of the oxide film 106b, and EcI2 represents the conduction band of the ruthenium oxide film. The energy of the bottom.

As shown in FIG. 3, in the oxide semiconductor film 106a and oxidation In the film 106b, the energy of the bottom of the conduction band changes gently without a barrier. In other words, it can be said that it changes continuously. This can be said that the oxide film 106b contains an element common to the oxide semiconductor film 106a, and a mixed layer is formed by the mutual movement of oxygen between the oxide semiconductor film 106a and the oxide film 106b.

As is clear from FIG. 3, the oxide semiconductor film 106a of the multilayer film 106 is a well, and a channel region is formed in the oxide semiconductor film 106a in the transistor using the multilayer film 106. Further, since the energy of the conduction band bottom of the multilayer film 106 is continuously changed, it can be said that the oxide semiconductor film 106a and the oxide film 106b are continuously joined.

Further, as shown in FIG. 4, although a trap level due to impurities or defects may be formed in the vicinity of the interface between the oxide film 106b and the protective insulating film 118, oxidation may be performed by providing the oxide film 106b. The semiconductor film 106a is away from the trap level. However, when the energy difference between EcS1 and EcS2 is small, the electrons of the oxide semiconductor film 106a sometimes cross the energy difference to reach the trap level. The electrons are trapped by the trap level, causing a negative fixed charge at the interface of the insulating film, which causes the critical voltage of the transistor to move in a positive direction.

Therefore, when the energy difference between EcS1 and EcS2 is 0.1 eV or more, preferably 0.15 eV or more, it is preferable to reduce the variation of the threshold voltage of the transistor and obtain stable electrical characteristics.

1-1-2. Source electrode and drain electrode

As the source electrode 116a and the drain electrode 116b, it may be a single layer or As the method of lamination, a conductive film containing one or more of aluminum, titanium, chromium, cobalt, nickel, copper, cerium, zirconium, molybdenum, niobium, silver, lanthanum, and tungsten is used. Preferably, the source electrode 116a and the drain electrode 116b are multilayer films having a layer containing copper. By using a multilayer film having a layer containing copper as the source electrode 116a and the drain electrode 116b, when wiring is formed in the same layer as the source electrode 116a and the drain electrode 116b, wiring resistance can be reduced. In addition, the source electrode 116a and the drain electrode 116b may have the same composition or different compositions.

Further, in the case where a multilayer film having a layer containing copper is used as the source electrode 116a and the drain electrode 116b, an interface between the oxide film 106b and the protective insulating film 118 is sometimes formed due to the influence of copper, for example. The trap level as shown in Figure 4. In this case, since the oxide film 106b is provided, it is possible to suppress electrons from being trapped by the trap level. Therefore, it is possible to impart stable electrical characteristics to the transistor and reduce wiring resistance.

1-1-3. Protective insulating film

As the protective insulating film 118, a single layer or a stacked layer is used, including alumina, magnesia, cerium oxide, cerium oxynitride, cerium oxynitride, cerium nitride, gallium oxide, cerium oxide, cerium oxide, zirconium oxide, and oxidation. One or more insulating films of cerium, cerium oxide, cerium oxide, and cerium oxide may be used.

For example, the protective insulating film 118 may be a multilayer film in which a hafnium oxide film is used as the first layer and a tantalum nitride film is used as the second layer. In this case, the hafnium oxide film may also be a hafnium oxynitride film. Further, the tantalum nitride film may also be a hafnium oxynitride film. The hafnium oxide film is preferably a hafnium oxide film having a small defect density. Specifically, the following ruthenium oxide film is used: in the measurement of Electron Spin Resonance (ESR), the density of the spin derived from the signal having a g value of 2.001 is 3 × 10 ¹⁷ spins/cm ³ or less. Preferably, it is 5 x 10 ¹⁶ spins/cm ³ or less. As the tantalum nitride film, a tantalum nitride film having a small amount of hydrogen gas and ammonia gas released is used. The amount of hydrogen and ammonia released can be measured by thermal desorption spectroscopy (TDS). Further, as the tantalum nitride film, a tantalum nitride film which does not transmit or hardly permeate hydrogen, water, and oxygen is used.

Further, for example, the protective insulating film 118 is a multilayer film in which the first hafnium oxide film 118a is the first layer, the second hafnium oxide film 118b is the second layer, and the tantalum nitride film 118c is the third layer. (Refer to Figure 1D). In this case, one or both of the first hafnium oxide film 118a and the second hafnium oxide film 118b may also be a hafnium oxynitride film. Further, the tantalum nitride film may also be a hafnium oxynitride film. The first hafnium oxide film 118a is preferably a hafnium oxide film having a small defect density. Specifically, the following cerium oxide film is used: in the ESR measurement, the density of the spin derived from the signal having a g value of 2.001 is 3 × 10 ¹⁷ spins / cm ³ or less, preferably 5 × 10 ¹⁶ spins / cm ³ the following. The second hafnium oxide film 118b uses a hafnium oxide film containing excess oxygen. The tantalum nitride film 118c is a tantalum nitride film having a small amount of hydrogen gas and ammonia gas released. Further, as the tantalum nitride film, a tantalum nitride film which does not transmit or hardly permeate hydrogen, water, and oxygen is used.

The ruthenium oxide film containing excess oxygen means a ruthenium oxide film which can release oxygen by heat treatment or the like. Further, the insulating film containing excess oxygen is an insulating film having a function of releasing oxygen by heat treatment.

The insulating film containing excess oxygen can reduce oxygen vacancies in the oxide semiconductor film 106a. The oxygen vacancies in the oxide semiconductor film 106a form a defect level, and a part thereof becomes a donor energy level. Therefore, by reducing the oxygen vacancies in the oxide semiconductor film 106a (especially the oxygen vacancies in the channel region), the carrier density of the oxide semiconductor film 106a (especially the channel region) can be lowered, thereby making it possible to impart stable electrical properties to the transistor. characteristic.

Here, the film which releases oxygen by heat treatment may also release the amount analyzed by TDS to be 1 × 10 ¹⁸ atoms / cm ³ or more, 1 × 10 ¹⁹ atoms / cm ³ or more, or 1 × 10 ²⁰ atoms / cm. ³ or more oxygen (converted to oxygen atoms).

Further, the film which releases oxygen by heat treatment sometimes contains peroxidic radicals. Specifically, the above case means that the spin density due to the peroxy radical is 5 × 10 ¹⁷ spins/cm ³ or more. Further, in the ESR, a film containing a peroxy radical may have a signal having an asymmetry in the vicinity of a g value of 2.01.

Further, the insulating film containing excess oxygen may also be an excess of cerium oxide (SiO _X (X>2)). In an oxygen-excess cerium oxide (SiO _X (X>2)), the number of oxygen atoms per unit volume is more than twice that of erbium atoms. The number of germanium atoms per unit volume and the number of oxygen atoms are values measured by RBS (Rutherford Backscattering Spectrometry).

1-1-4. Gate insulating film

The gate insulating film 112 is used in a single layer or in a stacked manner to contain oxidation More than one of aluminum, magnesium oxide, cerium oxide, cerium oxynitride, cerium oxynitride, cerium nitride, gallium oxide, cerium oxide, cerium oxide, zirconium oxide, cerium oxide, cerium oxide, cerium oxide, and cerium oxide. The film can be.

For example, the gate insulating film may be a multilayer film in which a tantalum nitride film is used as the first layer and a hafnium oxide film is used as the second layer. In this case, the hafnium oxide film may also be a hafnium oxynitride film. Further, the tantalum nitride film may also be a hafnium oxynitride film. The hafnium oxide film is preferably a hafnium oxide film having a small defect density. Specifically, the following cerium oxide film is used: in the ESR, the density of the spin derived from the signal having a g value of 2.001 is 3 × 10 ¹⁷ spins/cm ³ or less, preferably 5 × 10 ¹⁶ spins/cm ³ or less. . The hafnium oxide film is preferably a hafnium oxide film containing an excess of oxygen. As the tantalum nitride film, a tantalum nitride film having a small amount of hydrogen gas and ammonia gas released is used. The amount of hydrogen and ammonia released can be measured by TDS analysis.

When at least one of the gate insulating film 112 and the protective insulating film 118 includes an insulating film containing excess oxygen, the oxygen vacancies of the oxide semiconductor film 106a can be reduced to impart stable electrical characteristics to the transistor.

1-1-5. Gate electrode

The gate electrode 104 may be a single layer or a laminated film containing one or more of aluminum, titanium, chromium, cobalt, nickel, copper, lanthanum, zirconium, molybdenum, niobium, silver, lanthanum, and tungsten.

1-1-6. Substrate

There is no major limitation on the substrate 100. For example, as the substrate 100, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. In addition, as the substrate 100, a single crystal semiconductor substrate such as tantalum or niobium carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as tantalum, an SOI (Silicon On Insulator) substrate, or the like may be used. A substrate on which semiconductor elements are provided on these substrates is used.

In addition, the fifth generation (1000 mm × 1200 mm or 1300 mm × 1500 mm), the sixth generation (1500 mm × 1800 mm), the seventh generation (1870 mm × 2200 mm), the eighth generation (2200 mm × 2500 mm), and the ninth generation are used as the substrate 100. In the case of a large-sized glass substrate (2400 mm × 2800 mm) or the tenth generation (2880 mm × 3130 mm), it is difficult to perform fine processing due to shrinkage of the substrate 100 due to heat treatment or the like in the process of the semiconductor device. Therefore, when the above-described large-sized glass substrate is used as the substrate 100, it is preferable to use a substrate having less shrinkage due to heat treatment. For example, the shrinkage amount after the heat treatment for 1 hour at 400 ° C, preferably 450 ° C, and more preferably 500 is used as the substrate 100 is 10 ppm or less, preferably 5 ppm or less, more preferably 3 ppm or less. Large glass substrate.

Further, a flexible substrate can also be used for the substrate 100. Further, as a method of providing a transistor on a flexible substrate, there is also a method of peeling off the transistor and transposing the transistor onto the substrate 100 as a flexible substrate after the transistor is formed on the non-flexible substrate. . In this case, it is preferred to provide a peeling layer between the non-flexible substrate and the transistor.

The transistor constructed as described above is formed in the oxide semiconductor film 106a by the channel, thereby having stable electrical characteristics and having high field-effect mobility. Further, even if a multilayer film having a layer containing copper is used for the source electrode 116a and the drain electrode 116b, stable electrical characteristics can be obtained.

1-2. Method of manufacturing transistor structure (1)

Here, a method of manufacturing a transistor will be described with reference to FIGS. 5A to 6B.

First, the substrate 100 is prepared.

Next, a conductive film as the gate electrode 104 is formed. Regarding the conductive film as the gate electrode 104, by sputtering, chemical vapor deposition (CVD: Chemical Vapor Deposition), molecular beam epitaxy (MBE: Molecular Beam Epitaxy), atomic layer deposition (ALD: Atomic) A conductive film shown as the gate electrode 104 may be formed by a layer deposition method or a pulsed laser deposition (PLD) method.

Next, a part of the conductive film as the gate electrode 104 is etched to form the gate electrode 104 (see FIG. 5A).

Next, a gate insulating film 112 is formed (see FIG. 5B). The gate insulating film 112 may be formed of the insulating film as the gate insulating film 112 by a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method.

Next, an oxide semiconductor film 126a processed into an oxide semiconductor film 106a is formed (see FIG. 5C). About oxide semiconductor The film 126a may be formed of the oxide semiconductor film described above as the oxide semiconductor film 106a by a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method.

Next, an oxide film 126b processed into the oxide film 106b is formed. The oxide film 126b may be formed by the above-described oxide film 106b by a sputtering method, a CVD method, an MBE method, an ALD method or a PLD method.

In the case where the oxide semiconductor film 126a and the oxide film 126b are formed by a sputtering method, an RF power source device, an AC power source device, a DC power source device, or the like can be suitably used as the power source device for generating plasma.

As the sputtering gas, a mixed gas of a rare gas (typically argon) atmosphere, an oxygen atmosphere, a rare gas, and oxygen can be suitably used. Further, in the case of using a mixed gas of a rare gas and oxygen, it is preferred to increase the ratio of oxygen to a relatively rare gas.

Further, the target material may be appropriately selected in combination with the composition of the oxide semiconductor film 126a and the oxide film 126b.

In the case of using the sputtering method, at least the oxide semiconductor film 126a is formed by the following process, whereby CAAC-OS can be formed. Specifically, the substrate temperature is set to 150° C. or higher and 500° C. or lower, preferably 150° C. or higher and 450° C. or lower, and more preferably 200° C. or higher and 350° C. or lower, and heating is performed to form an oxide semiconductor. Film 126a. Further, the oxide film 126b may be formed by heating as described above.

In addition, in order to make the oxide semiconductor film 106a and oxide The film 106b is continuously joined, and it is preferable that the oxide semiconductor film 126a and the oxide film 126b are continuously formed so as not to be exposed to the atmosphere. Further, the oxide semiconductor film 126a and the oxide film 126b can suppress impurities from entering between the layers.

Specifically, in order to form the continuous joining, it is preferable to use a multi-chamber film forming apparatus (sputtering apparatus) equipped with a loading lock chamber so as to continuously laminate the respective films so as not to be in contact with the atmosphere. In each of the chambers of the sputtering apparatus, it is preferable to use an adsorption type vacuum exhaust pump such as a cryopump that can remove water or the like which is an impurity to the oxide semiconductor film as much as possible to perform high vacuum discharge. Gas (exhaust to 1 × 10 ^-4 Pa to 5 × 10 ^-7 Pa or so). Alternatively, it is preferred to combine the turbomolecular pump and the cold trap to prevent gas from flowing back from the exhaust system to the chamber.

In order to obtain an oxide semiconductor film in which the impurity and the carrier density are lowered, it is necessary to perform high-vacuum evacuation in the chamber, and it is also necessary to perform high-purification of the sputtering gas. As the oxygen or argon gas used as the sputtering gas, it is possible to prevent moisture, etc. as much as possible by using a gas which is highly purified to a dew point of -40 ° C or lower, preferably -80 ° C or lower, more preferably -100 ° C or lower. Enters the oxide semiconductor film.

Further, when the oxide film 126b is formed by a sputtering method, it is preferable to use a target containing indium from the viewpoint of reducing the number of particles generated at the time of film formation. Further, it is preferable to use an oxide target having a relatively small atomic ratio of gallium. This is because by using a target containing indium, the conductivity of the target can be improved and DC discharge and AC discharge can be easily performed, which is easy to correspond to a large-area substrate. Thereby, the semiconductor device can be improved Productivity.

Further, after the oxide semiconductor film 126a and the oxide film 126b are formed, the plasma treatment may be performed in an oxygen atmosphere or a nitrogen atmosphere and an oxygen atmosphere. Thereby, at least the oxygen vacancies in the oxide semiconductor film 126a can be reduced.

Then, a photoresist mask is formed on the oxide semiconductor film 126a and the oxide film 126b, and a part of the oxide semiconductor film 126a and the oxide film 126b is etched by the photoresist mask to form the oxide semiconductor film 106a and The multilayer film 106 of the oxide film 106b (see FIG. 6A). This etching employs wet etching as described above. By performing this wet etching, the multilayer film 106 can be formed into a tapered shape having two different taper angles.

Next, it is preferred to perform the first heat treatment. The first heat treatment may be carried out at 250 ° C or higher and 650 ° C or lower, preferably at 300 ° C or higher and 500 ° C or lower. The first heat treatment is carried out in an atmosphere of an oxidizing gas containing 10 ppm or more, 1% or more, or 10% or more under an inert gas atmosphere or under reduced pressure. Alternatively, the first heat treatment may be carried out in an oxidizing gas atmosphere containing 10 ppm or more, 1% or more, or 10% or more in order to fill the desorbed oxygen after heat treatment in an inert gas atmosphere. By performing the first heat treatment, the crystallinity of the oxide semiconductor film 106a can be improved, and impurities such as water, hydrogen, nitrogen, and carbon can be removed from the gate insulating film 112 and the multilayer film 106.

Further, the first heat treatment may be performed before or after the etching process of forming the multilayer film 106.

Next, a conductive film serving as the source electrode 116a and the drain electrode 116b is formed. The conductive film as the source electrode 116a and the drain electrode 116b is formed by using a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method to form a conductive film as the source electrode 116a and the drain electrode 116b. Just fine.

For example, as the conductive film to be the source electrode 116a and the drain electrode 116b, a multilayer film including a tungsten layer and a copper layer provided on the tungsten layer may be formed.

Next, a part of the conductive film as the source electrode 116a and the drain electrode 116b is etched to form the source electrode 116a and the drain electrode 116b (see FIG. 6B). In the case of using a multilayer film including a tungsten layer and a copper layer provided on the tungsten layer as the conductive film to be the source electrode 116a and the drain electrode 116b, the multilayer film can be etched using the same mask. Even if the tungsten layer and the copper layer are etched once, the copper concentration between the oxide semiconductor film 106a and the oxide film 106b can be set lower than 1 by providing the oxide film 106b on the oxide semiconductor film 106a. ×10 ¹⁹ atoms/cm ³ , less than 2 × 10 ¹⁸ atoms/cm ³ or less than 2 × 10 ¹⁷ atoms/cm ³ , and thus deterioration of electrical characteristics of the transistor due to copper does not occur. Therefore, the degree of freedom of the process can be improved and the productivity of the transistor can be improved.

Next, it is preferred to perform the second heat treatment. The second heat treatment may be performed with reference to the description of the first heat treatment. By the second heat treatment, impurities such as hydrogen and water can be removed from the multilayer film 106. Since hydrogen is particularly easy to move in the multilayer film 106, it is reduced by performing the second heat treatment. Less hydrogen can impart stable electrical characteristics to the transistor. Further, since water is also a compound containing hydrogen, it may become an impurity in the oxide semiconductor film 106a.

Further, the low resistance region 106c and the low resistance region 106d may be formed in the multilayer film 106 contacting the source electrode 116a and the drain electrode 116b by the second heat treatment.

As described above, by forming the multilayer film 106, the crystallinity of the oxide semiconductor film 106a can be improved, and the impurity concentration of the oxide semiconductor film 106a, the impurity concentration of the oxide film 106b, and the oxide semiconductor film 106a and oxide can be reduced. The impurity concentration of the interface between the films 106b.

Next, a protective insulating film 118 is formed (see FIG. 1B). The protective insulating film 118 may be formed of the above-described insulating film as the protective insulating film 118 by a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method.

Here, a case where the protective insulating film 118 is a three-layer structure as shown in FIG. 1D will be described. First, the first hafnium oxide film 118a is formed. Next, a second hafnium oxide film 118b is formed. Then, a treatment of adding oxygen ions to the second hafnium oxide film 118b may be performed. The treatment of adding oxygen ions may be performed by an ion doping apparatus or a plasma processing apparatus. As the ion doping apparatus, an ion doping apparatus having a mass separation function can also be utilized. As a raw material of oxygen ions, oxygen such as ¹⁶ O ₂ or ¹⁸ O ₂ , nitrous oxide gas or ozone gas may be used. Next, the protective insulating film 118 may be formed by forming the tantalum nitride film 118c.

The first hafnium oxide film 118a is preferably formed by a plasma CVD method which is one of CVD methods. Specifically, it can be formed under the following conditions: the substrate temperature is set to 180° C. or higher and 400° C. or lower, preferably 200° C. or higher and 370° C. or lower, and a deposition gas containing cerium and an oxidizing gas are used and the pressure is set. It is 20 Pa or more and 250 Pa or less, and it is preferable to set it as 40 Pa or more and 200 Pa or less, and the high frequency power is supplied to an electrode. Further, typical examples of the deposition gas containing ruthenium include decane, acetane, propane, fluorinated decane, and the like. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, and nitrogen dioxide.

Further, by setting the flow rate of the oxidizing gas to 100 times or more of the deposition gas containing cerium, the hydrogen content in the first cerium oxide film 118a can be reduced, and the dangling bonds can be reduced.

By the above manner, the first hafnium oxide film 118a having a small defect density is formed. That is, the first hafnium oxide film 118a may have a density of spin derived from a signal having a g value of 2.001 in the ESR of 3 × 10 ¹⁷ spins/cm ³ or less or 5 × 10 ¹⁶ spins/cm ³ or less.

The second hafnium oxide film 118b is preferably formed by a plasma CVD method. Specifically, it can be formed under the following conditions: the substrate temperature is set to 160° C. or higher and 350° C. or lower, preferably 180° C. or higher and 260° C. or lower, and a deposition gas containing cerium and an oxidizing gas are used and the pressure is set. It is preferably 100 Pa or more and 200 Pa or less, and is preferably 100 Pa or more and 200 Pa or less, and supplies 0.17 W/cm ² or more and 0.5 W/cm ² or less, preferably 0.25 W/cm ² or more and 0.35 W/cm to the electrode. ² or less high frequency power.

Since the decomposition efficiency of the gas in the plasma is improved by the above method, the oxygen radicals are increased, and the oxidation of the gas is enhanced, so that the second hafnium oxide film 118b containing excess oxygen can be formed.

The tantalum nitride film 118c is preferably formed by a plasma CVD method. Specifically, it can be formed under the following conditions: the substrate temperature is set to 180° C. or higher and 400° C. or lower, preferably 200° C. or higher and 370° C. or lower, and a deposition gas containing cerium, nitrogen gas, and ammonia gas is used and the pressure is applied. The temperature is set to 20 Pa or more and 250 Pa or less, preferably 40 Pa or more and 200 Pa or less, and high frequency power is supplied.

Further, the flow rate of nitrogen gas is 5 times or more and 50 times or less, preferably 10 times or more and 50 times or less, of the flow rate of the ammonia gas. Further, decomposition of a deposition gas containing cerium and nitrogen can be promoted by using ammonia gas. This is because the ammonia gas is dissociated by the plasma energy and the heat energy, and the energy generated by the dissociation contributes to the bonding of the deposition gas containing cerium and the decomposition of the nitrogen gas.

Therefore, the tantalum nitride film 118c having a small amount of hydrogen gas and ammonia gas released can be formed by the above method. Further, since the hydrogen content is small, a dense tantalum nitride film 118c which makes hydrogen, water, and oxygen impervious or hardly permeated can be formed.

Next, it is preferred to perform the third heat treatment. The third heat treatment may be performed with reference to the description of the first heat treatment. By the third heat treatment, excess oxygen can be released from the gate insulating film 112 or/and the protective insulating film 118, and the oxygen vacancies of the multilayer film 106 can be lowered. In addition, in the multilayer film 106, appearance is performed due to oxygen vacancies capturing adjacent oxygen atoms mobile.

By the above steps, the transistor of the BGTC structure shown in FIGS. 1A to 1D can be manufactured.

1-3. Crystal structure (2)

Here, a modification of the transistor shown in FIGS. 1A to 1D will be described using FIGS. 7A to 7D.

7A to 7D are a plan view and a cross-sectional view showing a transistor as the modification. Fig. 7A shows a plan view of a transistor. Fig. 7B shows a cross-sectional view corresponding to the chain line A1-A2 shown in Fig. 7A. In addition, FIG. 7C shows a cross-sectional view corresponding to the chain line A3-A4 shown in FIG. 7A. In addition, in FIG. 7A, in order to make a figure clear, a part of the components of the transistor (gate insulating film, protective insulating film, etc.) is abbreviate|omitted.

The transistor shown in FIGS. 7A to 7D is different from the transistor shown in FIGS. 1A to 1D in that it contacts the upper surface of the source electrode 116a and the gate electrode 116b, and the upper surface of the multilayer film 106. The oxide film 107 is provided in a manner.

The oxide film 117 can be formed using an oxide film which can be applied to the oxide film 106b of the multilayer film 106, and can be formed by a method applicable to the oxide film 106b. Further, other constituent elements of the transistor shown in FIGS. 7A to 7D are the same as those of the transistor shown in FIGS. 1A to 1D, and the above description can be appropriately referred to.

Since the transistor shown in FIGS. 7A to 7D is provided with an oxide film between the oxide semiconductor film 106a and the protective insulating film 118 Since the structure of the oxide film 107 is 106b, the trap level due to impurities or defects formed in the vicinity of the interface between the protective insulating film 118 and the oxide semiconductor film 106a can be further separated. That is, even in the case where the energy difference between EcS1 and EcS2 is small, it is possible to suppress the electrons of the oxide semiconductor film 106a from reaching the trap level beyond the energy difference. Therefore, the transistor shown in FIGS. 7A to 7D is a transistor having stable electrical characteristics in which the variation of the threshold voltage is further lowered.

In addition, the method of manufacturing the transistor shown in FIGS. 7A to 7D can be referred to the description about the transistor shown in FIGS. 1A to 1D as appropriate.

As described above, since the impurity and the carrier density are lowered in the oxide semiconductor film 106a (especially, the channel region) of the multilayer film 106, the transistors shown in FIGS. 1A to 1D and 7A to 7D have stability. Electrical characteristics.

Embodiment 2

In the present embodiment, a transistor having a configuration different from that of the first embodiment of the embodiment of the present invention will be described.

2-1. Crystal structure (3)

The top gate type transistor is described in this section. Here, a transistor of a top gate top contact structure (TGTC structure) of a top gate type transistor will be described using FIGS. 8A to 8C.

8A to 8C show the tilt of a transistor of a TGTC structure View and section view. Fig. 8A shows a plan view of a transistor. Fig. 8B shows a cross-sectional view corresponding to the chain line B1-B2 shown in Fig. 8A. Fig. 8C shows a cross-sectional view corresponding to the chain line B3-B4 shown in Fig. 8A.

The transistor shown in FIG. 8B includes a base insulating film 202 disposed on a substrate 200, and a multilayer film 206 including an oxide film 206c disposed on the base insulating film 202 and disposed on the oxide film 206c. An oxide semiconductor film 206a and an oxide film 206b disposed on the oxide semiconductor film 206a; a source electrode 216a and a drain electrode 216b disposed on the base insulating film 202 and the multilayer film 206; and a multilayer film 206 and a source a gate insulating film 212 on the electrode 216a and the drain electrode 216b; a gate electrode 204 provided on the gate insulating film 212; and a protective insulating film 218 provided on the gate insulating film 212 and the gate electrode 204. Further, the transistor may not include one or both of the base insulating film 202 and the protective insulating film 218.

Further, depending on the kind of the conductive film for the source electrode 216a and the drain electrode 216b, it is possible to take oxygen from a part of the multilayer film 206 or form a mixed layer, and form the low-resistance region 206d and the low-resistance region in the multilayer film 206. 206e. In FIG. 8B, the low-resistance region 206d and the low-resistance region 206e become a region in the vicinity of the interface in contact with the source electrode 216a and the drain electrode 216b in the multilayer film 206 (dashed line of the multilayer film 206 and the source electrode 216a and the drain electrode) The area between the electrodes 216b). One or all of the low resistance region 206d and the low resistance region 206e function as a source region and a drain region.

The area overlapped with the gate electrode 204 shown in FIG. 8A In the middle, the interval between the source electrode 216a and the drain electrode 216b is referred to as a channel length. Further, in the case where the transistor includes the source region and the drain region, in the region overlapping the gate electrode 204, the interval between the source region and the drain region may also be referred to as the channel length.

Further, the channel formation region refers to a region of the multilayer film 206 that overlaps the gate electrode 204 and is sandwiched between the source electrode 216a and the drain electrode 216b. In addition, the channel region refers to a region where the current in the channel formation region mainly flows. Here, the channel region is a part of the oxide semiconductor film 206a in the channel formation region.

2-1-1. About multilayer film

The multilayer film 206 has a structure in which an oxide film 206b and an oxide film 206c are laminated on the upper and lower sides of the oxide semiconductor film 206a. The lower surface of the oxide semiconductor film 206a corresponds to the surface of the oxide semiconductor film 206a on the substrate 200 side or the boundary surface with the oxide film 206c. The lower surface of the oxide film 206b corresponds to the surface of the oxide film 206b on the substrate 200 side or the boundary surface with the oxide semiconductor film 206a. The lower surface of the oxide film 206c corresponds to the surface of the oxide film 206c on the substrate 200 side or the surface of the oxide film 206c that is in contact with the gate insulating film 112. Further, the laminated structure of the multilayer film 206 can be confirmed by STEM (Scanning Transmission Electron Microscopy). However, depending on the materials used for the oxide semiconductor film 206a, the oxide film 206b, and the oxide film 206c, the boundary may not be clearly confirmed.

As the oxide semiconductor film 206a, an oxide semiconductor film which can be applied to the oxide semiconductor film 106a of the first embodiment can be used. As the oxide film 206b, an oxide film which can be applied to the oxide film 106b of the first embodiment can be used. As the oxide film 206c, an oxide film which can be applied to the oxide film 106b of the first embodiment can be used.

In the multilayer film 206, at least the oxide semiconductor film 206a has a tapered shape. Preferably, the oxide film 206b and the oxide film 206c also have a tapered shape. Further, it is preferable that at least the tapered shape of the oxide semiconductor film 206a is different from the tapered shape of the oxide film 206b and the tapered shape of the oxide film 206c. The tapered shape of the oxide film 206b and the oxide film 206c may be the same or different.

Specifically, in the oxide semiconductor film 206a, the angle between the lower surface of the oxide semiconductor film 206a and the side surface of the oxide semiconductor film 206a is referred to as a first angle θ1, and in the oxide film 206b, an oxide is formed. The angle between the lower surface of the film 206b and the side surface of the oxide film 206b is referred to as a second angle θ2, and in the oxide film 206c, the angle between the lower surface of the oxide film 206c and the side surface of the oxide film 206c It is called the third angle θ3. In this case, the first angle θ1 may be set to an acute angle, and the second angle θ2 and the third angle θ3 may be set to an acute angle or a vertical direction.

Preferably, the first angle θ1, the second angle θ2, and the third angle θ3 are all acute angles, and at least the first angle θ1 is smaller than the second angle θ2 and the third angle θ3 (refer to FIG. 9).

Further, the second angle θ2 and the third angle θ3 may be the same angle or different angles. For example, by using an oxide film The 206b and the oxide film 206c are made of the same type of oxide film, and the second angle θ2 and the third angle θ3 can be set to the same angle.

Further, the first angle θ1 is 10° or more and less than 90°, preferably 30° or more and 70° or less. The second angle θ2 and the third angle θ3 are 10° or more and less than 90°, preferably 30° or more and 70° or less.

As described above, by setting the shape of the multilayer film 206 to a tapered shape having different taper angles, the following effects can be obtained. For the multilayer film 206, by setting it to a tapered shape having different taper angles, the multilayer film 206 can be enlarged between the source electrode 216a and the drain electrode 216b as compared with the tapered shape having the same taper angle. Contact area. Thereby, the contact resistance between the multilayer film 206 and the source electrode 216a and the drain electrode 216b can be lowered to increase the on-state current of the transistor.

Further, by making the second angle θ2 and the third angle θ3 larger than the first angle θ1, the contact area between the oxide film 206b and the oxide film 206c and the source electrode 216a and the drain electrode 216b can be reduced, thereby making it possible to The low resistance region formed in the oxide film 206b and the oxide film 206c is reduced. Therefore, it is possible to suppress the low resistance of one or both of the oxide film 206b and the oxide film 206c, suppress the leakage path generated between the source electrode 216a and the drain electrode 216b, and at the same time function as a channel region. The low-resistance region is efficiently formed in the oxide semiconductor film 206a, so that an increase in the on-state current of the transistor and a decrease in the off-state current of the transistor can be simultaneously achieved.

Further, the upper end of the oxide semiconductor film 206a substantially coincides with the lower end of the oxide film 206b, and the upper end of the oxide film 206c and the oxide The lower ends of the semiconductor films 206a are substantially identical (see FIG. 9). That is, the multilayer film 206 does not have a large step 213 and a large step 214 formed of two or more of the oxide semiconductor film 206a, the oxide film 206b, and the oxide film 206c (refer to FIGS. 32A and 32B). ). Therefore, the disconnection of the film (for example, the conductive film processed into the source electrode 216a and the drain electrode 216b) provided on the multilayer film 206 can be suppressed, so that a transistor having good electrical characteristics can be manufactured. Further, "the upper end of the oxide semiconductor film 206a substantially coincides with the lower end of the oxide film 206b, and the upper end of the oxide film 206c substantially coincides with the lower end of the oxide semiconductor film 206a" means the lower end of the oxide film 206b and the oxide semiconductor film. The distance L1 between the upper ends of 206a and the distance L2 between the upper end of the oxide film 206c and the lower end of the oxide semiconductor film 206a are 30 nm or less, preferably 10 nm or less (see FIGS. 32A and 32B).

The above-described tapered shape can be formed by utilizing the difference in etching speed of each film when the multilayer film 206 is formed by etching. In particular, the tapered shape can be formed by making the etching rate of the oxide semiconductor film 206a lower than the etching rate of the oxide film 206b and the etching rate of the oxide film 206c.

When the second angle θ2 is smaller than the third angle θ3, the etching rate of the oxide film 206b may be lower than the etching rate of the oxide film 206c. Further, when the second angle θ2 is made larger than the third angle θ3, the etching rate of the oxide film 206b may be higher than the etching rate of the oxide film 206c.

As in Embodiment 1, the above-described tapered shape can be made by It is formed by wet etching using a solution containing phosphoric acid for the etchant. Further, the details of the wet etching can be referred to the first embodiment. Further, by making the second angle θ2 and the third angle θ3 larger than the first angle θ1, the area exposed to the etchant in the wet etching can be minimized. Further, by making the second angle θ2 and the third angle θ3 larger than the first angle θ1, it is possible to reduce the formation of the oxide film 206b and the oxide film 206c due to contamination or defect generation by the etchant. Resistance zone.

By forming the multilayer film 206 by wet etching, as shown in Embodiment 1, it is possible to suppress a decrease in the yield of the transistor and to manufacture a transistor having good electrical characteristics with high productivity.

Hereinafter, the energy band structure of the multilayer film 206 will be described with reference to FIGS. 10A to 10C.

For example, an In-Ga-Zn oxide having an energy gap of 3.15 eV is used as the oxide semiconductor film 206a, and an In-Ga-Zn oxide having an energy gap of 3.5 eV is used as the oxide film 206b and the oxide film 206c. The energy gap was measured using a spectral ellipsometer (UT-IB JOBIN YVON UT-300).

The energy difference (also referred to as free potential) between the vacuum energy level of the oxide semiconductor film 206a and the upper end of the valence band is 8 eV. Further, the free potential of the oxide film 206b and the oxide film 206c was 8.2 eV. Further, the energy difference between the vacuum level and the valence band tip was measured by an ultraviolet photoelectron spectroscopy (UPS: Versa Probe).

Therefore, the vacuum level and the conductance of the oxide semiconductor film 206a The energy difference (also known as electron affinity) between the bottomed energy is 4.85 eV. The electron affinity of the oxide film 206b and the oxide film 206c was 4.7 eV.

FIG. 10A schematically illustrates a portion of the energy band structure of the multilayer film 206. In FIG. 10A, a case where a tantalum oxide film (base insulating film 202 and gate insulating film 212) is provided in contact with each of the oxide film 206b and the oxide film 206c is described. Here, EcI1 represents the energy of the conduction band bottom of the ruthenium oxide film, EcS1 represents the energy of the conduction band bottom of the oxide semiconductor film 206a, EcS2 represents the energy of the conduction band bottom of the oxide film 206b, and EcS3 represents the conduction of the oxide film 206c. With bottom energy, EcI2 represents the energy of the conduction band bottom of the ruthenium oxide film.

As shown in FIG. 10A, in the oxide semiconductor film 206a, the oxide film 206b, and the oxide film 206c, the energy of the conduction band bottom changes gently without a barrier. In other words, it can be said that it changes continuously. This can be said that the oxide film 206b and the oxide film 206c contain the same elements as the oxide semiconductor film 206a, and are oxidized between the oxide semiconductor film 206a and the oxide film 206b and in the oxide semiconductor film 206a. The oxygen between the film 206c moves to each other to form a mixed layer.

As is apparent from FIG. 10A, the oxide semiconductor film 206a of the multilayer film 206 becomes a well, and in the transistor using the multilayer film 206, a channel region is formed in the oxide semiconductor film 206a. In addition, since the energy of the conduction band bottom of the multilayer film 206 is continuously changed, it can be said that the oxide semiconductor film 206a and the oxide film 206b are continuously joined, and the oxide semiconductor The film 206a is continuously joined to the oxide film 206c.

Further, by forming the oxide film 206b and the oxide film 206c as oxide films having different energy at the bottom of the conduction band, the energy band structure of the multilayer film 206 can be changed in accordance with the magnitude relationship of the energy of the conduction band bottom.

The multilayer film 206 having the energy band structure shown in Fig. 10B can be formed by using an oxide having a larger conduction band bottom than the oxide film 206b as the oxide film 206c.

By using the oxide of the conduction band bottom as the oxide film 206c as an oxide smaller than the oxide film 206b, the multilayer film 206 having the energy band structure shown in Fig. 10C can be formed.

Further, in the multilayer film 206 having the energy band structure shown in FIGS. 10B and 10C, the channel region is also formed in the oxide semiconductor film 206a.

In addition, although it is possible to form a trap level due to an impurity or a defect in the vicinity of the interface between the oxide film 206b and the gate insulating film 212, the oxide semiconductor film 206a can be made by providing the oxide film 206b. The trap can be farther away. However, in the case where the energy difference between EcS1 and EcS2 is small, the electrons of the oxide semiconductor film 206a sometimes pass the energy difference to reach the trap level. Since the electrons are trapped by the trap level, a negative fixed charge is generated at the interface of the insulating film, which causes the threshold voltage of the transistor to move in the positive direction.

In addition, although it is possible to form a trap level due to an impurity or a defect in the vicinity of the interface between the oxide film 206c and the base insulating film 202, the oxide semiconductor film 206a can be made far from the trap level from. Further, when the energy difference between EcS1 and EcS3 is small, the electrons of the oxide semiconductor film 206a sometimes pass the energy difference to reach the trap level. The electrons are trapped by the trap level, causing a negative fixed charge at the interface of the insulating film, which causes the critical voltage of the transistor to move in a positive direction.

Therefore, when the energy difference between EcS1 and EcS2 and the energy difference between EcS1 and EcS3 are set to 0.1 eV or more, preferably 0.15 eV or more, the variation of the threshold voltage of the transistor is reduced to obtain stable electrical characteristics. So it is better.

2-1-2. About other structures

The substrate 200 can be referred to the description about the substrate 100. Further, the source electrode 216a and the drain electrode 216b can be referred to the description of the source electrode 116a and the drain electrode 116b. In addition, the gate insulating film 212 can be referred to the description about the gate insulating film 112. In addition, the description of the gate electrode 104 can be referred to as the gate electrode 204. Further, the protective insulating film 218 can be referred to the description about the protective insulating film 118.

Further, in FIG. 8A, although the multilayer film 206 is formed to the outer side of the gate electrode 204 in the upper surface shape, it may be formed such that the width of the gate electrode 204 is larger than the width of the multilayer film 206 to suppress light from above. A carrier is generated in the multilayer film 206.

The base insulating film 202 may be used in a single layer or in a laminated manner including alumina, magnesia, cerium oxide, cerium oxynitride, cerium oxynitride, cerium nitride, gallium oxide, cerium oxide, cerium oxide, zirconium oxide, cerium oxide. One or more insulating films of cerium oxide, cerium oxide, and cerium oxide.

For example, the base insulating film 202 may have a laminated structure in which the first layer is a tantalum nitride film and the second layer is a hafnium oxide film. At this time, the hafnium oxide film may also be a hafnium oxynitride film. Further, the tantalum nitride film may also be a hafnium oxynitride film. The hafnium oxide film is preferably a hafnium oxide film having a small defect density. Specifically, the following cerium oxide film is used: in the ESR, the density of the spin derived from the signal having a g value of 2.001 is 3 × 10 ¹⁷ spins/cm ³ or less, preferably 5 × 10 ¹⁶ spins/cm ³ or less. . As the tantalum nitride film, a tantalum nitride film having a small amount of hydrogen and ammonia released is used. The amount of hydrogen and ammonia released can be measured by TDS analysis. Further, as the tantalum nitride film, a tantalum nitride film which does not transmit or hardly permeate hydrogen, water, and oxygen is used.

Further, for example, the base insulating film 202 may be a laminate in which the first layer is a first tantalum nitride film, the second layer is a first hafnium oxide film, and the third layer is a second hafnium oxide film. structure. In this case, the first hafnium oxide film or/and the second hafnium oxide film may also be a hafnium oxynitride film. Further, the tantalum nitride film may also be a hafnium oxynitride film. The first hafnium oxide film is preferably a hafnium oxide film having a small defect density. Specifically, the following cerium oxide film is used: in the ESR, the density of the spin derived from the signal having a g value of 2.001 is 3 × 10 ¹⁷ spins/cm ³ or less, preferably 5 × 10 ¹⁶ spins/cm ³ or less. . The second hafnium oxide film uses a hafnium oxide film containing excess oxygen. As the tantalum nitride film, a tantalum nitride film having a small amount of hydrogen and ammonia released is used. Further, as the tantalum nitride film, a tantalum nitride film which does not transmit or hardly permeate hydrogen, water, and oxygen is used.

In the case where one or both of the gate insulating film 212 and the base insulating film 202 have an insulating film containing excess oxygen, oxygen vacancies in the oxide semiconductor film 206a can be lowered.

As described above, the transistor shown in the present embodiment has stable electrical characteristics and high field-effect mobility because the impurity and the carrier density of the oxide semiconductor film 206a (especially the channel region) of the multilayer film 206 are lowered.

2-2. Method of manufacturing transistor structure (3)

Here, a method of manufacturing a transistor will be described using FIGS. 11A to 12B.

First, the substrate 200 is prepared.

A base insulating film 202 is formed on the substrate 200. The insulating film may be formed by using a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method for the base insulating film 202.

Next, an oxide film 226c processed into the oxide film 206c is formed. The method of forming the oxide film 206c can be referred to the description of the oxide film 106b of the first embodiment. Further, the oxide film 206c is formed as CAAC-OS or amorphous. When the oxide film 206c is CAAC-OS or amorphous, the oxide semiconductor film 226a which is the oxide semiconductor film 206a is likely to be CAAC-OS.

Next, an oxide semiconductor film 226a processed into the oxide semiconductor film 206a is formed. The method of forming the oxide semiconductor film 226a can be referred to the description of the oxide semiconductor film 106a of the first embodiment.

Next, an oxide film 226b processed into the oxide film 206b is formed. The film formation method of the oxide film 226b can be referred to the implementation side. Description of the oxide film 106b of Formula 1 (refer FIG. 11A).

As shown in the first embodiment, in order to continuously bond the oxide film 206c and the oxide semiconductor film 206a and the oxide film 206b, it is preferable to continuously laminate the oxide film 226c and the oxide so that the respective films are not exposed to the atmosphere. Semiconductor film 226a and oxide film 226b.

Then, a part of the oxide film 226c, the oxide semiconductor film 226a, and the oxide film 226b is etched to form a multilayer film 206 including the oxide film 206c, the oxide semiconductor film 206a, and the oxide film 206b (see FIG. 11B). Further, the etching can be referred to the above etching.

Next, it is preferred to perform the first heat treatment. The first heat treatment may be carried out at 250 ° C or higher and 650 ° C or lower, preferably 300 ° C or higher and 500 ° C or lower. The first heat treatment is performed in an inert gas atmosphere containing an oxidizing gas atmosphere of 10 ppm or more, 1% or more, or 10% or more, or under reduced pressure. Alternatively, the first heat treatment may be carried out in an oxidizing gas atmosphere containing 10 ppm or more, 1% or more, or 10% or more in order to fill the desorbed oxygen after heat treatment in an inert gas atmosphere. By performing the first heat treatment, the crystallinity of the oxide semiconductor film 226a can be improved, and impurities such as water, hydrogen, nitrogen, and carbon can be removed from the base insulating film 202 and the multilayer film 206.

Further, the first heat treatment may be performed before or after the etching process of forming the multilayer film 206.

Next, a conductive film serving as the source electrode 216a and the drain electrode 216b is formed. Used as source electrode 216a and drain electrode 216b For the film formation method of the conductive film, the description of the source electrode 116a and the drain electrode 116b of the first embodiment can be referred to.

Next, a part of the conductive film as the source electrode 216a and the drain electrode 216b is etched to form a source electrode 216a and a drain electrode 216b (see FIG. 11C).

Next, it is preferred to perform the second heat treatment. The second heat treatment may be performed with reference to the description of the first heat treatment. By performing the second heat treatment, impurities such as water, hydrogen, nitrogen, and carbon can be removed from the multilayer film 206.

Further, the low resistance region 206d and the low resistance region 206e may be formed in the multilayer film 206 contacting the source electrode 216a and the drain electrode 216b by the second heat treatment.

Next, a gate insulating film 212 is formed (see FIG. 12A). The method of forming the gate insulating film 212 can be referred to the description of the gate insulating film 112 of the first embodiment.

Next, a conductive film as the gate electrode 204 is formed. Next, a part of the conductive film as the gate electrode 204 is etched to form a gate electrode 204 (see FIG. 12B). The film formation method and etching process of the gate electrode 204 can be referred to the description of the gate electrode 104 of the first embodiment.

Next, a protective insulating film 218 is formed (see FIG. 8B). The method of forming the protective insulating film 218 can be referred to the description of the protective insulating film 118.

Through the above steps, it can be manufactured as shown in FIGS. 8A to 8C. The transistor.

2-3. Crystal structure (4)

Here, a modification of the transistor shown in FIGS. 8A to 8C will be described using FIGS. 13A to 13C.

13A to 13C are a plan view and a cross-sectional view showing a transistor as the modification. Fig. 13A shows a plan view of a transistor. Fig. 13B shows a cross-sectional view corresponding to the chain line B1-B2 shown in Fig. 13A. In addition, FIG. 13C shows a cross-sectional view corresponding to the chain line B3-B4 shown in FIG. 13A. In addition, in FIG. 13A, in order to make a figure clear, a part of the components of the transistor (gate insulating film, protective insulating film, etc.) is abbreviate|omitted.

The transistor shown in FIGS. 13A to 13C is different from the transistor shown in FIGS. 8A to 8C in that the oxide film 206c is not included in the multilayer film 206. That is, the multilayer film 206 in the transistor shown in FIGS. 13A to 13C is the oxide semiconductor film 206a and the oxide film 206b. Further, other constituent elements of the transistor shown in FIGS. 13A to 13C are the same as those of the transistor shown in FIGS. 8A to 8C, and the above description can be appropriately referred to.

In the transistor shown in FIGS. 13A to 13C, although it is possible to form a trap level due to an impurity or a defect in the vicinity of the interface between the oxide film 206b and the gate insulating film 212, by providing an oxide film 206b, the oxide semiconductor film 206a can be moved away from the trap level. Therefore, the transistor shown in FIGS. 13A to 13C is a transistor having stable electrical characteristics in which variation in threshold voltage is lowered.

Further, the method of manufacturing the transistor shown in FIGS. 13A to 13C can be referred to the description of the transistor shown in the first embodiment and FIGS. 8A to 8C as appropriate.

2-4. Crystal structure (5)

Here, a transistor which is a modification of the transistor shown in FIGS. 8A to 8C will be described using FIGS. 14A to 14C.

14A to 14C are a plan view and a cross-sectional view showing a transistor as the modification. Fig. 14A shows a plan view of a transistor. Fig. 14B shows a cross-sectional view corresponding to the chain line B1-B2 shown in Fig. 14A. In addition, FIG. 14C shows a cross-sectional view corresponding to the chain line B3-B4 shown in FIG. 14A. In addition, in FIG. 14A, in order to clarify the drawing, a part of the constituent elements of the transistor (a gate insulating film, a protective insulating film, etc.) is omitted.

The transistor shown in FIGS. 14A to 14C is different from the transistor shown in FIGS. 8A to 8C in that the oxide film 206b is not included in the multilayer film 206. That is, the multilayer film 206 in the transistor shown in FIGS. 14A to 14C is the oxide film 206c and the oxide semiconductor film 206a. In addition, the oxide film 207 is also provided in contact with the upper surface of the source electrode 216a, the upper surface of the drain electrode 216b, and the upper surface of the multilayer film 206.

As the oxide film 207, an oxide film which can be applied to the oxide film 106b of the multilayer film 106 of the first embodiment can be used, and can be formed by a method which can be applied to the oxide film 106b. In addition, other constituent elements of the transistor shown in FIGS. 14A to 14C and FIGS. 8A to 8C The illustrated transistors are the same, and the above description can be appropriately referred to.

Since the transistor shown in FIGS. 14A to 14C has a structure in which the oxide film 207 is provided between the oxide semiconductor film 206a and the gate insulating film 212, it can be further caused by the formation of the oxide film 207 and the gate. The trap level of impurities or defects in the vicinity of the interface between the insulating films 212 is away from the oxide semiconductor film 106a. Therefore, the transistor shown in FIGS. 14A to 14C is a transistor having stable electrical characteristics in which variation in the threshold voltage of the transistor is lowered.

Further, the method of manufacturing the transistor shown in FIGS. 14A to 14C can be referred to the description of the transistor shown in the first embodiment and FIGS. 8A to 8C as appropriate.

2-5. Other transistor structures

For example, in the transistor shown in FIGS. 8A to 8C, a transistor having the following structure is also included in one embodiment of the present invention: on the upper surface of the source electrode 212a and the gate electrode 212b, and on the multilayer film 206. An oxide film 207 of the transistor shown in FIGS. 14A to 14C is provided between the surface and the gate insulating film 212.

By using the transistor having the above structure, the oxide film 206b and the oxide film 207 are provided between the oxide semiconductor film 206a and the gate insulating film 212, so that it can be further formed in the oxide. The trap level of impurities or defects in the vicinity of the interface between the film 207 and the gate insulating film 212 is away from the oxide semiconductor film 206a. That is, even when the energy difference between EcS1 and EcS2 is small Next, it is also possible to suppress the electrons of the oxide semiconductor film 206a from reaching the trap level beyond the energy difference. Therefore, a transistor having stable electrical characteristics in which the variation of the threshold voltage is further reduced can be obtained.

Further, the following transistor is also included in one embodiment of the present invention: a multilayer film 206 having an oxide semiconductor film 206a, an oxide film 206b, and an oxide film 206c is used instead of the bottom gate structure explained in Embodiment 1. Multilayer film 106 of the transistor.

As described above, since the impurity and the carrier density are lowered in the oxide semiconductor films 106a, 206a (especially the channel region) of the multilayer films 106, 206, FIGS. 8A to 8C, 13A to 13C, and 14A to The transistor shown in Fig. 14C has stable electrical characteristics.

Embodiment 3

In the present embodiment, a semiconductor device using the transistor described in the above embodiment will be described.

3-1. Display device

Here, a display device using one of the semiconductor devices of the transistor described in the above embodiment will be described.

As the display element provided in the display device, a liquid crystal element (also referred to as a liquid crystal display element), a light-emitting element (also referred to as a light-emitting display element), or the like can be used. The light-emitting element includes, within its scope, an element whose luminance is controlled by current or voltage, and specifically includes an inorganic EL (Electro Luminescence) element, an organic EL element, and the like. this Further, a display medium whose contrast is changed by an electric action such as electronic ink may be used as the display element. Next, a display device using an EL element and a display device using the liquid crystal element will be described as an example of a display device.

Further, the display device shown below includes a panel in a state in which a display element is sealed, and a module in a state in which an IC including a controller is mounted in the panel.

In addition, the display device shown below refers to an image display device or a light source (including a lighting device). In addition, the display device further includes: a module in which a connector (such as FPC or TCP) is mounted; a module in which a printed circuit board is disposed at an end of the TCP; or an IC (integrated circuit) is directly mounted to the COG method A module that displays components.

Further, an input unit (not shown) by sensing according to contact or non-contact may be provided in the display device shown below. For example, as an input unit by sensing according to contact, various methods such as a resistive type, a capacitive type, an infrared type, an electromagnetic induction type, a surface acoustic wave type, and the like can be employed. Further, the input unit by the non-contact sensing can be implemented by an infrared camera or the like.

The input unit can be provided by a so-called "On-cell" method separately provided on the display device shown below, or by a so-called "unit" integrally provided with the display device shown below. In-cell mode is set.

3-1-1.EL display device

Here, a display device (also referred to as an EL display device) using an EL element will be described.

Fig. 15 is an example of a circuit diagram of a pixel of an EL display device.

The EL display device shown in FIG. 15 has a switching element 743, a transistor 741, a capacitor 742, and a light-emitting element 719.

The gate of the transistor 741 is electrically connected to one end of the switching element 743 and one end of the capacitor 742. The source of the transistor 741 is electrically connected to one end of the light-emitting element 719. The drain of the transistor 741 is electrically connected to the other end of the capacitor 742 and is supplied with a power supply potential VDD. The other end of the switching element 743 is electrically connected to the signal line 744. The other end of the light-emitting element 719 is supplied with a constant potential. In addition, the constant potential is a potential equal to or lower than the ground potential GND.

Further, the transistor 741 is the transistor described in the above embodiment. The transistor has stable electrical characteristics. Therefore, it can be an EL display device with high display quality.

As the switching element 743, a transistor is preferably used. By using a transistor, the area of the pixel can be reduced, whereby an EL display device having high resolution can be obtained. Further, the switching element 743 may be the transistor described in the above embodiment. By using the transistor as the switching element 743, the switching element 743 can be fabricated by the same process as the transistor 741, whereby the productivity of the EL display device can be improved.

Fig. 16A is a plan view of the EL display device. EL display The substrate 100, the substrate 700, the sealing material 734, the driving circuit 735, the driving circuit 736, the pixels 737, and the FPC 732 are disposed. The sealing material 734 is disposed between the substrate 100 and the substrate 700 in such a manner as to surround the pixel 737, the driving circuit 735, and the driving circuit 736. In addition, one or both of the driving circuit 735 and the driving circuit 736 may also be disposed outside the sealing material 734.

Fig. 16B is a cross-sectional view of the EL display device corresponding to the chain line M-N of Fig. 16A. The FPC 732 is connected to the wiring 733a via the terminal 731. Further, the wiring 733a is on the same layer as the gate electrode 104.

In addition, FIG. 16B shows an example in which the transistor 741 and the capacitor 742 are disposed on the same plane. By adopting such a configuration, the capacitor 742 can be formed on the same plane as the gate electrode, the gate insulating film, and the source electrode (drain electrode) of the transistor 741. Thus, by arranging the transistor 741 and the capacitor 742 on the same plane, the process of the EL display device can be shortened, whereby productivity can be improved.

FIG. 16B shows an example in which the transistor shown in FIGS. 1A to 1D is applied as the transistor 741. Therefore, the configuration described below with reference to FIGS. 1A to 1D is referred to as a configuration that is not particularly described below in the respective configurations of the transistor 741.

An insulating film 720 is provided on the transistor 741 and the capacitor 742.

Here, an opening portion up to the source electrode 116a of the transistor 741 is provided in the insulating film 720 and the protective insulating film 118.

An electrode 781 is provided on the insulating film 720. Electrode 781 The opening provided in the insulating film 720 and the protective insulating film 118 is connected to the source electrode 116a of the transistor 741.

A partition wall 784 including an opening portion up to the electrode 781 is provided on the electrode 781.

A light-emitting layer 782 that is in contact with the electrode 781 by an opening provided in the partition 784 is provided on the partition 784.

An electrode 783 is provided on the light emitting layer 782.

A region where the electrode 781, the light-emitting layer 782, and the electrode 783 overlap each other is the light-emitting element 719.

In addition, regarding the insulating film 720, the description of the protective insulating film 118 is referred to. Alternatively, a resin film such as a polyimide resin, an acrylic resin, an epoxy resin, or an anthrone resin may be used.

The light-emitting layer 782 is not limited to a single layer, and the light-emitting layer 782 may be provided by laminating a plurality of light-emitting layers or the like. For example, the structure shown in Fig. 16C can be employed. 16C is a structure in which an intermediate layer 785a, a light-emitting layer 786a, an intermediate layer 785b, a light-emitting layer 786b, an intermediate layer 785c, a light-emitting layer 786c, and an intermediate layer 785d are laminated in this order. At this time, when the light-emitting layer 786a, the light-emitting layer 786b, and the light-emitting layer 786c are formed with a light-emitting layer of an appropriate light-emitting color, the light-emitting element 719 having high color reproducibility or high light-emitting efficiency can be formed.

It is also possible to obtain white light by laminating a plurality of light-emitting layers. Although not shown in FIG. 16B, a configuration in which white light is extracted via the coloring layer may be employed.

Although shown here, there are three illuminating layers and four The structure of the interlayer is not limited to this structure, and the number of layers of the light-emitting layer and the intermediate layer may be appropriately changed. For example, it may be composed only of the intermediate layer 785a, the light-emitting layer 786a, the intermediate layer 785b, the light-emitting layer 786b, and the intermediate layer 785c. Further, a configuration in which the intermediate layer 785a, the light-emitting layer 786a, the intermediate layer 785b, the light-emitting layer 786b, the light-emitting layer 786c, and the intermediate layer 785d are formed, and the intermediate layer 785c is omitted may be employed.

Further, the intermediate layer may have a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, or the like in a laminated structure. In addition, the intermediate layer does not necessarily include all of the above layers. These layers can be selected and set as appropriate. In addition, it is also possible to repeatedly set layers having the same function. Further, as the intermediate layer, in addition to the carrier generating layer, an electron relay layer or the like may be added as appropriate.

The electrode 781 may be a conductive film having visible light transmittance. Having visible light transmittance means that the average transmittance in the visible light region (for example, a wavelength range of from 400 nm to 800 nm) is 70% or more, particularly 80% or more.

As the electrode 781, for example, an oxide film such as an In—Zn—W oxide film, an In—Sn oxide film, an In—Zn oxide film, an indium oxide film, a zinc oxide film, or a tin oxide film can be used. Further, a trace amount of Al, Ga, Sb, F or the like may be added to the oxide film. Further, a metal thin film (preferably about 5 nm to 30 nm) having a degree of light transmission can be used. For example, a 5 nm thick Ag film, a Mg film, or an Ag-Mg alloy film can be used.

Alternatively, the electrode 781 is preferably reflective using high efficiency. See the film of light. For example, the electrode 781 may be a film containing lithium, aluminum, titanium, magnesium, ruthenium, silver, rhodium or nickel.

The electrode 783 can use a film selected from the group consisting of the electrode 781. Further, in the case where the electrode 781 has visible light transmittance, it is preferable that the electrode 783 efficiently reflects visible light. Further, in the case where the electrode 781 efficiently reflects visible light, it is preferable that the electrode 783 has visible light transmittance.

Further, although the electrode 781 and the electrode 783 are provided in the configuration shown in FIG. 16B, the electrode 781 and the electrode 783 may be exchanged with each other. The electrode functioning as the anode is preferably a conductive film having a large work function, and the electrode functioning as a cathode is preferably a conductive film having a small work function. However, in the case of contacting the anode and providing a carrier generating layer, various conductive films can be used for the anode regardless of the work function.

Regarding the partition 784, the description of the protective insulating film 118 is referred to. Alternatively, a resin film such as a polyimide resin, an acrylic resin, an epoxy resin, or an anthrone resin may be used.

Further, in the display device, an optical member (optical substrate) such as a black matrix (light shielding film), a polarizing member, a phase difference member, an antireflection member, or the like is appropriately provided. For example, circular polarization using a polarizing substrate and a phase difference substrate can also be used.

The transistor 741 connected to the light-emitting element 719 has stable electrical characteristics. Therefore, an EL display device with high display quality can be provided.

17A and 17B are different from the portion of FIG. 16B. An example of a cross-sectional view of an EL display device. Specifically, the difference is the wiring connected to the FPC 732. In FIG. 17A, the FPC 732 is connected to the wiring 733b via the terminal 731. The wiring 733b is the same layer as the source electrode 116a and the drain electrode 116b. In FIG. 17B, the FPC 732 is connected to the wiring 733c via the terminal 731. The wiring 733c is on the same layer as the electrode 781.

3-1-2. Liquid crystal display device

Next, a display device (also referred to as a liquid crystal display device) using a liquid crystal element will be described.

18 is a circuit diagram showing a configuration example of a pixel of a liquid crystal display device. The pixel 750 shown in FIG. 18 includes a transistor 751, a capacitor 752, and a pair of liquid crystal-filled elements (hereinafter referred to as liquid crystal elements) 753 between the electrodes.

In the transistor 751, one of the source and the drain is electrically connected to the signal line 755, and the gate is electrically connected to the scan line 754.

In the capacitor 752, one electrode is electrically connected to the other of the source and the drain of the transistor 751, and the other electrode is electrically connected to a wiring that supplies a common potential.

In the liquid crystal element 753, one electrode is electrically connected to the other of the source and the drain of the transistor 751, and the other electrode is electrically connected to a wiring that supplies a common potential. Further, the common potential supplied to the wiring electrically connected to the other electrode of the capacitor 752 described above may be different from the common potential supplied to the other electrode of the liquid crystal element 753.

In addition, a top view of the liquid crystal display device and the EL display device The top view is roughly the same. Fig. 19A shows a cross-sectional view of a liquid crystal display device corresponding to the chain line M-N of Fig. 16A. In FIG. 19A, the FPC 732 is connected to the wiring 733a via the terminal 731. Further, the wiring 733a is on the same layer as the gate electrode 104.

Fig. 19A shows an example in which the transistor 751 and the capacitor 752 are disposed on the same plane. By adopting such a configuration, the capacitor 752 can be formed on the same plane as the gate electrode, the gate insulating film, and the source electrode (drain electrode) of the transistor 751. Thus, by arranging the transistor 751 and the capacitor 752 on the same plane, the process of the liquid crystal display device can be shortened, thereby improving productivity.

As the transistor 751, the above transistor can be used. Fig. 19A shows an example in which the transistor shown in Figs. 1A to 1D is applied. Therefore, the configuration that will not be described below in the respective configurations of the transistor 751 will be described with reference to FIGS. 1A to 1D.

In addition, the transistor 751 can use a transistor having a very small off-state current. Therefore, the electric charge held in the capacitor 752 is not easily leaked, and the voltage applied to the liquid crystal element 753 can be maintained for a long period of time. Therefore, when the moving image or the still image having little movement is displayed, the transistor 751 is turned off, and the power for the operation of the transistor 751 is not required, whereby the liquid crystal display device having low power consumption can be obtained.

The size of the capacitor 752 provided in the liquid crystal display device is set so that the electric charge can be stored for a predetermined period in consideration of the leakage current or the like of the transistor 751 disposed in the pixel portion. By using the transistor 751, it is provided that it has 1/3 or less of the liquid crystal capacitance in each pixel, preferably 1/5. The following capacitor-sized capacitors are sufficient, so the aperture ratio of the pixels can be increased.

An insulating film 721 is provided on the transistor 751 and the capacitor 752.

Here, an opening portion up to the gate electrode 116b of the transistor 751 is provided in the insulating film 721 and the protective insulating film 118.

An electrode 791 is provided on the insulating film 721. The electrode 791 is connected to the gate electrode 116b of the transistor 751 through an opening provided in the insulating film 721 and the protective insulating film 118.

An insulating film 792 functioning as an alignment film is provided on the electrode 791.

A liquid crystal layer 793 is provided on the insulating film 792.

An insulating film 794 functioning as an alignment film is provided on the liquid crystal layer 793.

A spacer 795 is disposed on the insulating film 794.

An electrode 796 is provided on the spacer 795 and the insulating film 794.

A substrate 797 is disposed on the electrode 796.

Further, regarding the insulating film 721, the description of the protective insulating film 118 is referred to. Alternatively, a resin film such as a polyimide resin, an acrylic resin, an epoxy resin, or an anthrone resin may be used.

The liquid crystal layer 793 may be a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal or the like. These liquid crystals exhibit a cholesterol phase and a stratification according to conditions. Phase, cubic phase, chiral nematic phase, and isotropic.

Further, as the liquid crystal layer 793, a liquid crystal exhibiting a blue phase can also be used. In this case, a structure in which the insulating film 792 and the insulating film 794 functioning as an alignment film are not provided may be employed.

The electrode 791 may be a conductive film having visible light transmittance.

When the liquid crystal display device is of a transmissive type, as the electrode 791, for example, an In—Zn—W oxide film, an In—Sn oxide film, an In—Zn oxide film, an indium oxide film, a zinc oxide film, and tin oxide can be used. An oxide film such as a film. Further, a trace amount of Al, Ga, Sb, F or the like may be added to the oxide film. Further, a metal thin film (preferably about 5 nm to 30 nm) having a degree of light transmission can be used.

In the case where the liquid crystal display device is of a reflective type, the electrode 791 is preferably a film that reflects visible light with high efficiency. For example, the electrode 791 may be a film containing aluminum, titanium, chromium, copper, molybdenum, silver, ruthenium or tungsten.

When the liquid crystal display device is of a transmissive type, the electrode 796 can use a conductive film having visible light transmittance selected from the electrode 791. On the other hand, when the liquid crystal display device is of a reflective type, when the electrode 791 has visible light transmittance, it is preferable that the electrode 796 efficiently reflects visible light. Further, in the case where the electrode 791 reflects visible light efficiently, the electrode 796 preferably has visible light transmittance.

Further, although the electrode 791 and the electrode 796 are provided in the configuration shown in FIG. 19A, the electrode 791 and the electrode 796 may be exchanged with each other.

The insulating film 792 and the insulating film 794 may be formed using an organic compound or an inorganic compound.

The separator 795 may be selected from an organic compound or an inorganic compound. In addition, the spacer 795 may have various shapes such as a column shape or a spherical shape.

A region where the electrode 791, the insulating film 792, the liquid crystal layer 793, the insulating film 794, and the electrode 796 overlap each other is the liquid crystal element 753.

The substrate 797 may be made of glass, resin, metal or the like. The substrate 797 can have flexibility.

19B and 19C are views showing an example of a cross-sectional view of a liquid crystal display device different from a portion A of Fig. 19. Specifically, the difference is the wiring connected to the FPC 732. In FIG. 19B, the FPC 732 is connected to the wiring 733b via the terminal 731. The wiring 733b is the same layer as the source electrode 116a and the drain electrode 116b. In FIG. 19C, the FPC 732 is connected to the wiring 733c via the terminal 731. The wiring 733c is on the same layer as the electrode 791.

The transistor 751 connected to the liquid crystal element 753 has stable electrical characteristics. Therefore, it is possible to provide a liquid crystal display device having high display quality. In addition, since the off-state current of the transistor 751 can be made extremely small, a liquid crystal display device with low power consumption can be provided.

In the liquid crystal display device, the operation mode can be appropriately selected. For example, there is a vertical electric field method in which a voltage is applied perpendicularly to the substrate, and a horizontal electric field method in which a voltage is applied in parallel with the substrate. Specifically, TN mode, VA mode, MVA mode, PVA mode, ASM mode, TBA mode, OCB mode, FLC mode, AFLC mode, or FFS may be mentioned. Mode, etc.

In the liquid crystal display device, an optical member (optical substrate) such as a black matrix (light shielding layer), a polarizing member, a phase difference member, and an antireflection member is appropriately provided. For example, circular polarization using a polarizing substrate and a phase difference substrate can also be used. Further, as the light source, a backlight, a sidelight, or the like can also be used.

Further, a time division display method (field sequential driving method) may be performed using a plurality of light emitting diodes (LEDs) as a backlight. By applying the field sequential driving method, color display can be performed without using a colored layer.

As described above, as the display mode in the pixel portion, a forward mode, an interleaving method, or the like can be employed. Further, the color elements that are controlled in the pixels when performing color display are not limited to three colors of RGB (R represents red, G represents green, and B represents blue). For example, RGBW (W indicates white) or RGB may be added with one or more colors of yellow, cyan, magenta, and the like. In addition, the size of the display area in the dots of each color element may also be different. However, the present invention is not limited to a display device for color display, but can also be applied to a liquid crystal display device for monochrome display.

3-2. Microcomputer

The above transistor can be used for a microcomputer mounted in various electronic devices.

Next, as one of the electronic devices on which the microcomputer is mounted For example, the structure and operation of the fire alarm will be described with reference to FIGS. 20, 21, 22A to 22C, and 23A.

Further, in the present specification, the fire alarm indicates all devices that urgently notify the occurrence of a fire, and includes, for example, a home fire alarm, an automatic fire alarm device, a fire detector for the automatic fire alarm device, and the like.

The alarm device shown in Fig. 20 has at least a microcomputer 500. Here, the microcomputer 500 is disposed inside the alarm device. The microcomputer 500 includes a power gate controller 503 electrically connected to the high potential power line VDD, a power gate 504 electrically connected to the high potential power line VDD and the power gate controller 503, and a CPU electrically connected to the power gate 504 (Central Processing Unit) : a central processing unit) 505 and a detecting unit 509 electrically connected to the power gate 504 and the CPU 505. Further, the CPU 505 includes a volatile memory unit 506 and a non-volatile memory unit 507.

In addition, the CPU 505 is electrically connected to the bus bar 502 via the interface 508. Like interface 508, interface 508 is also electrically coupled to power gate 504. As the bus bar standard of the interface 508, for example, an I ² C bus bar or the like can be used. A light-emitting element 530 electrically connected to the power gate 504 via the interface 508 is provided in the alarm device.

As the light-emitting element 530, it is preferable to emit light having high directivity. For example, an organic EL element, an inorganic EL element, an LED, or the like can be used.

The power gate controller 503 has a timer in accordance with which the power gate 504 is controlled. The power gate 504 is in accordance with the power gate controller 503 Control, supply or cut off the power supplied from the high potential power line VDD to the CPU 505, the detecting unit 509, and the interface 508. Here, as the power gate 504, a switching element such as a transistor can be used.

By using the power gate controller 503 and the power gate 504, power supply to the detecting unit 509, the CPU 505, and the interface 508 can be performed during the measurement of the amount of light, and the detecting unit can be cut off during the idle period of the measurement period. 509, CPU 505 and interface 508 power supply. By operating the alarm device in this manner, it is possible to reduce the power consumption compared to the case where the power supply is constantly supplied to each of the above-described configurations.

Further, when a transistor is used as the power gate 504, it is preferable to use a transistor for the non-volatile memory portion 507 and having an extremely low off-state current, for example, the transistor described in the above embodiment. By using such a transistor, leakage current can be reduced when the power supply 504 is turned off, and power consumption is reduced.

It is also possible to provide a DC power source 501 in the alarm device and supply power to the high-potential power source line VDD from the DC power source 501. The electrode on the high potential side of the DC power source 501 is electrically connected to the high potential power source line VDD, and the electrode on the low potential side of the DC power source 501 is electrically connected to the low potential power source line VSS. The low potential power line VSS is electrically connected to the microcomputer 500. Here, the high potential power line VDD is supplied with a high potential H. In addition, a low potential L such as a ground potential (GND) is supplied to the low potential power line VSS.

In the case where a battery is used as the DC power source 501, for example, a configuration in which a battery case including the following components is provided in the casing, that is, an electrode electrically connected to the high-potential power source line VDD, and a low-potential electric current may be employed. An electrode electrically connected to the source line VSS and an outer casing of the battery can be held. Further, the alarm device may not necessarily be provided with the DC power source 501. For example, a configuration may be adopted in which the power source is supplied from the AC power source provided outside the alarm device via the wiring.

Further, as the above battery, a secondary battery such as a lithium ion secondary battery (also referred to as a lithium ion battery, a lithium ion battery or a lithium ion battery) may be used. Further, it is preferable to provide a solar cell to be able to charge the secondary battery.

The detecting unit 509 measures the physical quantity of the abnormality and transmits the measured value to the CPU 505. The physical quantity of the abnormality differs depending on the use of the alarm device, and the physical quantity related to the fire is measured in the alarm device that functions as a fire alarm. Therefore, the detecting unit 509 measures the amount of light as a physical quantity related to the fire and detects the presence of the smoke.

The detecting unit 509 has a photo sensor 511 electrically connected to the power gate 504, an amplifier 512 electrically connected to the power gate 504, and an AD converter 513 electrically connected to the power gate 504 and the CPU 505. The light-emitting element 530, the photo sensor 511, the amplifier 512, and the AD converter 513 operate when the power supply shutter 504 supplies power to the detecting unit 509.

Figure 21 shows a portion of a section of the alarm device. An element isolation region 403 is formed on the p-type semiconductor substrate 401, and an n-type transistor 519 is formed. The n-type transistor 519 includes a gate insulating film 407, a gate electrode 409, an n-type impurity region 411a, and an n-type impurity. Area 411b. The n-type transistor 519 is formed using a semiconductor such as a single crystal germanium, so that high-speed operation can be performed. Therefore, it is possible to form a CPU capable of high-speed access. Volatile memory. Further, an insulating film 415 and an insulating film 417 are provided on the n-type transistor 519.

Further, a contact plug 419a and a contact plug 419b are formed at an opening portion that selectively etches a part of the insulating film 415 and the insulating film 417, and a trench is provided on the insulating film 417, the contact plug 419a, and the contact plug 419b. The insulating film 421 of the portion. Moreover, the wiring 423a and the wiring 423b are formed in the groove portion of the insulating film 421. In addition, the insulating film 420 is formed on the insulating film 421, the wiring 423a, and the wiring 423b by a sputtering method, a CVD method, or the like, and an insulating film 422 having a groove portion is formed on the insulating film 420. An electrode 424 is formed in the groove portion of the insulating film 422. The electrode 424 is an electrode that functions as a back gate electrode of the second transistor 517. By providing such an electrode 424, the control of the threshold voltage of the second transistor 517 can be performed.

Further, an insulating film 425 is provided on the insulating film 422 and the electrode 424 by a sputtering method, a CVD method, or the like.

A second transistor 517 and a photoelectric conversion element 514 are provided on the insulating film 425. The second transistor 517 includes: a multilayer film 206 including an oxide semiconductor film 206a and an oxide film 206b; a source electrode 216a and a drain electrode 216b contacting the multilayer film 206; a gate insulating film 212; and a gate electrode 204. And a protective insulating film 218. Further, an insulating film 445 covering the photoelectric conversion element 514 and the second transistor 517 is provided, and a wiring 449 contacting the gate electrode 216b is provided on the insulating film 445. The wiring 449 functions as a node that electrically connects the gate electrode of the second transistor 517 and the gate electrode 409 of the n-type transistor 519.

The photo sensor 511 includes a photoelectric conversion element 514, a capacitance element, a first transistor, a second transistor 517, a third transistor, and an n-type transistor 519. Here, as the photoelectric conversion element 514, for example, a photodiode or the like can be used.

One of the terminals of the photoelectric conversion element 514 is electrically connected to the low potential power line VSS, and the other of the terminals is electrically connected to one of the source electrode and the drain electrode of the second transistor 517. Providing a charge accumulation control signal Tx to the gate electrode of the second transistor 517, one of the source electrode and the drain electrode and one of the pair of electrodes of the capacitance element, the source electrode of the first transistor, and the drain electrode One of the electrodes and the gate electrode of the n-type transistor 519 are electrically connected (hereinafter, this node is sometimes referred to as a node FD). The other of the pair of electrodes of the capacitive element is electrically connected to the low potential power line VSS. A reset signal Res is provided to the gate electrode of the first transistor, and the other of the source electrode and the drain electrode is electrically connected to the high potential power line VDD. One of the source electrode and the drain electrode of the n-type transistor 519 is electrically connected to one of the source electrode and the drain electrode of the third transistor, and the amplifier 512. Further, the other of the source electrode and the drain electrode of the n-type transistor 519 is electrically connected to the high-potential power supply line VDD. A bias signal Bias is provided to the gate electrode of the third transistor, and the other of the source electrode and the drain electrode is electrically connected to the low potential power line VSS.

Further, it is not always necessary to provide a capacitor element. For example, when the parasitic capacitance of the n-type transistor 519 or the like is sufficiently large, a configuration in which a capacitor element is not provided may be employed.

In addition, the first transistor and the second transistor 517 are preferably Use a transistor with a very low off-state current. Further, as the transistor having an extremely low off-state current, a transistor using the above-described multilayer film including an oxide semiconductor film is preferably used. By adopting such a configuration, the potential of the node FD can be maintained for a long time.

Further, in the structure shown in FIG. 21, the photoelectric conversion element 514 is provided on the insulating film 425 in electrical connection with the second transistor 517.

The photoelectric conversion element 514 has a semiconductor film 260 provided on the insulating film 425, and a source electrode 216a and an electrode 216c that are in contact with the second transistor 517 provided on the semiconductor film 260. The source electrode 216a is an electrode functioning as a source electrode or a drain electrode of the second transistor 517, and electrically connects the photoelectric conversion element 514 and the second transistor 517.

A gate insulating film 212, a protective insulating film 218, and an insulating film 445 are provided on the semiconductor film 260, the source electrode 216a of the second transistor 517, and the electrode 216c. Further, a wiring 456 is provided on the insulating film 445, and is in contact with the electrode 216c via an opening provided in the gate insulating film 212, the protective insulating film 218, and the insulating film 445.

The electrode 216c can be formed by the same process as the source electrode 216a and the drain electrode 216b of the second transistor 517, and the wiring 456 can be formed by the same process as the wiring 449.

As the semiconductor film 260, a semiconductor film capable of photoelectric conversion can be provided, and for example, tantalum and niobium can be used. When ruthenium is used for the semiconductor film 260, it functions as a photosensor that detects visible light. In addition, because the wavelengths of electromagnetic waves that helium and neon can absorb are different, If a structure in which germanium is used for the semiconductor film 260 is employed, it can be used as a sensor for detecting infrared rays.

As described above, since the detecting unit 509 including the photo sensor 511 can be provided in the microcomputer 500, the number of components can be reduced, and the casing of the alarm device can be reduced.

In the fire alarm including the IC chip described above, a CPU 505 that combines a plurality of circuits using the above transistors and mounts them on one IC wafer is employed.

3-3. CPU

22A to 22C are block diagrams showing a specific configuration of a CPU in which the above-described transistor is used at least for a part thereof.

The CPU shown in FIG. 22A includes: ALU 1191 (Arithmetic logic unit); ALU controller 1192; instruction decoder 1193; interrupt controller 1194; timing controller 1195; register 1196; Controller 1197; bus interface 1198 (Bus I/F); rewritable ROM 1199; and ROM interface 1189 (ROM I/F). As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. ROM 1199 and ROM interface 1189 can be placed on different wafers. Of course, the CPU shown in Fig. 22A is only an example shown by simplifying its structure, and the actual CPU has various structures depending on its use.

The command input to the CPU via the bus interface 1198 is input to the instruction decoder 1193 and decoded, and is input to the ALU. The controller 1192, the interrupt controller 1194, the scratchpad controller 1197, and the timing controller 1195.

The ALU controller 1192, the interrupt controller 1194, the scratchpad controller 1197, and the timing controller 1195 perform various controls in accordance with the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the action of the ALU 1191. Further, the interrupt controller 1194 determines an interrupt request from an external input/output device and peripheral circuits based on the priority or the mask state during execution of the program of the CPU, and processes the request. The scratchpad controller 1197 generates an address of the scratchpad 1196 and performs a read from the scratchpad 1196 or a write to the scratchpad 1196 depending on the state of the CPU.

Further, the timing controller 1195 generates signals for controlling the operation timings of the ALU 1191, the ALU controller 1192, the command decoder 1193, the interrupt controller 1194, and the scratchpad controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates the internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the internal clock signal CLK2 to the above various circuits.

In the CPU shown in FIG. 22A, a memory unit is provided in the register 1196. As the memory unit of the register 1196, the above transistor can be used.

In the CPU shown in FIG. 22A, the register controller 1197 performs selection of the holding operation in the register 1196 in accordance with an instruction from the ALU 1191. In other words, in the memory unit of the register 1196, whether to perform the holding of the data based on the flip-flop or the capacitor-based selection is performed. The maintenance of the information of the components. In the case where the holding of the data based on the flip-flop is selected, the supply of the power supply voltage to the memory cells in the register 1196 is performed. When the holding of the data based on the capacitive element is selected, the data rewriting of the capacitive element is performed, and the supply of the power supply voltage to the memory unit in the register 1196 can be stopped.

As shown in FIG. 22B or FIG. 22C, the supply of the power supply voltage can be stopped by providing a switching element between the memory cell group and the node to which the power supply potential VDD or the power supply potential VSS is supplied. The circuit of Fig. 22B and Fig. 22C will be described below.

22B and 22C are memory devices in which the above-described transistor is used to control a switching element for supplying a power supply potential to a memory cell.

The memory device shown in FIG. 22B has a switching element 1141 and a memory cell group 1143 having a plurality of memory cells 1142. Specifically, each of the memory cells 1142 can use the above-described transistor. Via the switching element 1141, the high level power supply potential VDD is supplied to the respective memory cells 1142 of the memory cell group 1143. Further, the potential of the signal IN and the potential of the low-level power supply potential VSS are supplied to the respective memory cells 1142 of the memory cell group 1143.

In Fig. 22B, the above-described transistor is used as the switching element 1141, and with respect to the transistor, its switching is controlled by a signal SigA supplied to its gate electrode layer.

Further, the structure in which the switching element 1141 has only one transistor is shown in FIG. 22B, but there is no particular limitation thereto, and a plurality of transistors may be provided. The switching element 1141 has a plurality of switching elements In the case of a functioning transistor, the plurality of transistors may be connected in parallel or in series, or may be connected in parallel and in series.

In addition, in FIG. 22B, the supply of the high-level power supply potential VDD to each memory cell 1142 of the memory cell group 1143 is controlled by the switching element 1141, but the supply of the low-level power supply potential VSS may be controlled by the switching element 1141. .

In addition, FIG. 22C shows an example of the memory device in which the low-level power supply potential VSS is supplied to the respective memory cells 1142 of the memory cell group 1143 via the switching element 1141. The supply of the low-level power supply potential VSS to each of the memory cells 1142 of the memory cell group 1143 can be controlled by the switching element 1141.

When the switching element is provided between the memory cell group and the node to which the power supply potential VDD or the power supply potential VSS is applied, and the operation of the CPU is temporarily stopped, and the supply of the power supply voltage is stopped, the data can be held, thereby reducing power consumption. the amount. Specifically, for example, while the user of the personal computer stops inputting information to an input device such as a keyboard, the operation of the CPU can be stopped, whereby power consumption can be reduced.

Here, the CPU has been described as an example, but it can also be applied to an LSI such as a DSP (Digital Signal Processor), a custom LSI, or an FPGA (Field Programmable Gate Array).

3-4. Setting example

In FIG. 23A, the alarm device 8100 is a residential fire alarm. There is a detection unit and a microcomputer 8101. The microcomputer 8101 includes a CPU using the above transistor.

In FIG. 23A, an air conditioner having an indoor unit 8200 and an outdoor unit 8204 includes a CPU using the above-described transistor. Specifically, the indoor unit 8200 has a housing 8201, a blower port 8202, a CPU 8203, and the like. In FIG. 23A, the case where the CPU 8203 is set in the indoor unit 8200 is exemplified, but the CPU 8203 may be provided in the outdoor unit 8204. Alternatively, the CPU 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. The air conditioner can be made to be power-saving by including a CPU using the above-described transistor.

In Fig. 23A, the electric refrigerator freezer 8300 includes a CPU using the above-described transistor. Specifically, the electric refrigerator-freezer 8300 includes a casing 8301, a refrigerator compartment door 8302, a freezer compartment door 8303, a CPU 8304, and the like. In FIG. 23A, the CPU 8304 is disposed inside the casing 8301. The electric refrigerator-freezer 8300 can be made to be power-saving by including a CPU using the above-described transistor.

23B and 23C show an example of an electric car. The electric vehicle 9700 is loaded with a secondary battery 9701. The electric power of the secondary battery 9701 is adjusted by the control circuit 9702 and supplied to the drive device 9703. The control circuit 9702 is controlled by a processing device 9704 having a ROM, a RAM, a CPU, and the like (not shown). The electric vehicle 9700 can be made to be power-saving by including a CPU using the above-described transistor.

The drive unit 9703 is constituted by a direct current motor or an alternating current motor alone or in combination with an electric motor and an internal combustion engine. Processing device 9704 according to the operation information (acceleration, deceleration, stop, etc.) of the driver of the electric vehicle 9700, the information at the time of driving (the information such as climbing, downhill, etc., load information received by the driving wheel, etc.), etc., to the control circuit 9702 Output control signals. The control circuit 9702 adjusts the electric energy supplied from the secondary battery 9701 in accordance with the control signal of the processing device 9704 and controls the output of the driving device 9703. When an AC motor is mounted, although not shown, an inverter that converts direct current into alternating current is built in.

Example 1

In the present embodiment, the etching rate at the time of wet etching the oxide semiconductor film and the shape of the side surface of the oxide semiconductor film will be described with reference to FIGS. 24 to 30B.

First, the type and etching rate of each of the oxide semiconductor film and the etchant will be described.

The manufacturing methods of the sample 1 and the sample 2 will be described below.

An oxide semiconductor film is formed on the glass substrate. Sample 1 had an In-Ga-Zn oxide film having a thickness of 100 nm formed on a glass substrate using a sputtering target of a metal oxide of In:Ga:Zn=1:1:1 (atomic ratio). Sample 2 had an In-Ga-Zn oxide film having a thickness of 100 nm formed on a glass substrate using a sputtering target of a metal oxide of In:Ga:Zn=1:3:2 (atomic ratio).

As a film formation condition of the In—Ga—Zn oxide film in the sample 1 , a sputtering target is used as a target of In:Ga:Zn=1:1:1 (atomic ratio). Supply to the reaction chamber of the sputtering device For argon having a flow rate of 50 sccm of sputtering gas and oxygen having a flow rate of 50 sccm, the pressure in the reaction chamber was controlled to 0.6 Pa, and a DC power of 5 kW was supplied. Further, the substrate temperature at the time of forming the In—Ga—Zn oxide film was 170° C.

As a film formation condition of the In-Ga-Zn oxide film of the sample 2, a sputtering target was used as a target of In:Ga:Zn=1:3:2 (atomic ratio), In the reaction chamber of the sputtering apparatus, Ar having a flow rate of 90 sccm and oxygen having a flow rate of 10 sccm were supplied as a sputtering gas, the pressure in the reaction chamber was controlled to 0.3 Pa, and a DC power of 5 kW was supplied. Further, the substrate temperature at the time of forming the In-Ga-Zn oxide film was 100 °C.

Next, the In-Ga-Zn oxide film formed in the sample 1 and the sample 2 was subjected to wet etching. In the wet etching process, any one of the first etchant to the third etchant is used. As the first etchant, 85 wt% of phosphoric acid at 25 ° C was used. As the second etchant, an aqueous oxalic acid solution at 60° C. (for example, ITO-07N (aqueous solution containing 5% by weight or less of oxalic acid) manufactured by Kanto Chemical Co., Ltd., Japan) is used. As the third etchant, a phosphoric acid-based aqueous solution (for example, a mixed aluminum silicate solution manufactured by Nippon Shokuhin Co., Ltd.) (aqueous solution containing 72% by weight of phosphoric acid, 2% by weight of nitric acid, and 9.8% by weight of acetic acid) is used. )).

Next, FIG. 24 shows the relationship between each etchant in the sample 1 and the sample 2 and the etching rate.

As can be seen from Fig. 24, there is an In-Ga-Zn oxide formed by using In:Ga:Zn = 1:1:1 (atomic ratio) as a sputtering target. The sample 1 of the film (indicated as In-Ga-Zn-O (111)) was etched in the etching using the aqueous oxalic acid solution as the second etchant.

On the other hand, it is understood that an In-Ga-Zn oxide film (indicated as In-Ga-Zn-) formed using In:Ga:Zn=1:3:2 (atomic ratio) as a sputtering target is provided. Sample 2 of O(132)) The etching rate was approximately the same in all etchants.

Next, the shape of the side surface of the oxide semiconductor film when the oxide semiconductor film of the stacked structure is etched using any one of the first etchant to the third etchant will be described.

The manufacturing methods of the sample 3 and the sample 4 will be described below. Further, Sample 3 and Sample 4 are a two-layer structure in which a first In-Ga-Zn oxide film and a second In-Ga-Zn oxide film are laminated.

The oxide semiconductor film of the laminated structure is formed on a glass substrate. First, a first In-Ga-Zn oxide film having a thickness of 35 nm is deposited on a glass substrate using a sputtering target of a metal oxide of In:Ga:Zn=1:1:1 (atomic ratio). Film formation. Next, a second In-Ga-Zn oxide film having a thickness of 20 nm was formed by using a sputtering target of a metal oxide of In:Ga:Zn=1:3:2 (atomic ratio).

Further, the first In—Ga—Zn oxide film is a film formed by the same film formation conditions as the In—Ga—Zn oxide film of Sample 1. In addition, the second In—Ga—Zn oxide film is a film formed by the same film formation conditions as the In—Ga—Zn oxide film of Sample 2.

Next, etching the oxide semiconductor film of the stacked structure engraved. In the sample 3, as the etchant, 85 wt% of phosphoric acid at 25 ° C as the first etchant was used. In the sample 4, as the etchant, a 30 ° C phosphoric acid aqueous solution as a third etchant was used.

Next, a method of manufacturing the sample 5 will be described. Further, the sample 5 is a three-layer structure in which a first In-Ga-Zn oxide film is laminated to a third In-Ga-Zn oxide film.

A tantalum nitride film and a hafnium oxynitride film are formed on the glass substrate by a CVD method. Next, an oxide semiconductor film having a laminated structure is formed on the hafnium oxynitride film. Next, a sputtering target of a metal oxide of In:Ga:Zn=1:3:2 (atomic ratio) is used on the hafnium oxynitride film to form a first In-Ga-Zn oxide having a thickness of 5 nm. Film. Next, a second In-Ga-Zn oxide film having a thickness of 20 nm was formed using a sputtering target of a metal oxide of In:Ga:Zn=3:1:2 (atomic ratio). Next, a third In-Ga-Zn oxide film having a thickness of 20 nm was formed using a sputtering target of a metal oxide of In:Ga:Zn=1:1:1 (atomic ratio). Next, a hafnium oxynitride film was formed on the third In-Ga-Zn oxide film by a CVD method.

Further, the first In-Ga-Zn oxide film in the sample 5 was formed using the sputtering target as a target of In:Ga:Zn=1:3:2 (atomic ratio), 90 sccm of argon and 10 sccm of oxygen as a sputtering gas were supplied to the reaction chamber of the sputtering apparatus, the pressure in the reaction chamber was controlled to 0.6 Pa, and a direct current of 5 kW was supplied. The second In-Ga-Zn oxide film is formed using a sputtering target as a target of In:Ga:Zn=3:1:2 (atomic ratio) to a sputtering apparatus. 50 sccm of argon and 50 sccm of oxygen as a sputtering gas were supplied in the reaction chamber, the pressure in the reaction chamber was controlled to 0.6 Pa, and a DC power of 5 kW was supplied. The third In-Ga-Zn oxide film was formed under the following conditions: a sputtering target was set to a target of In:Ga:Zn=1:1:1 (atomic ratio), and the reaction was performed on a sputtering apparatus. The chamber was supplied with 100 sccm of oxygen as a sputtering gas, the pressure in the reaction chamber was controlled to 0.6 Pa, and a DC power of 5 kW was supplied. Further, the substrate temperature at the time of forming the first In-Ga-Zn oxide film to the third In-Ga-Zn oxide film was 170 °C.

Next, the oxide semiconductor film of the stacked structure is etched. In the sample 5, an aqueous oxalic acid solution of 60 ° C as a second etchant was used as an etchant.

Next, a method of manufacturing the sample 6 will be described. Further, the sample 6 is a two-layer structure in which a first In-Ga-Zn oxide film and a second In-Ga-Zn oxide film are laminated.

A hafnium oxynitride film is formed on the glass substrate by a CVD method. Next, the same film formation conditions as those of the sample 3 and the sample 4 were used on the yttrium oxynitride film, and a sputtering target of a metal oxide of In:Ga:Zn=1:1:1 (atomic ratio) was used. After forming a first In-Ga-Zn oxide film having a thickness of 35 nm, a sputtering target of a metal oxide of In:Ga:Zn=1:3:2 (atomic ratio) was used to form a thickness of 20 nm. A second In-Ga-Zn oxide film. Next, a hafnium oxynitride film is formed on the second In-Ga-Zn oxide film.

Next, the oxide semiconductor film of the stacked structure is etched. In the sample 6, the oxide semiconductor film of the laminated structure was etched by dry etching. Further, BCl _{3 is} used as an etching gas.

Next, the cross-sectional shape of the sample 3 to the sample 6 was observed using STEM (Scanning Transmission Electron Microscopy).

Fig. 25A shows a phase contrast image (TE image) of 200,000 magnification of the sample 3, and Fig. 25B shows a schematic view of Fig. 25A. In addition, FIG. 26 shows a Z contrast image (ZC image) of 150,000 times magnification of the sample 3.

Fig. 27A shows a phase contrast image (TE image) of 200,000 magnification of the sample 4, and Fig. 27B shows a schematic view of Fig. 27A.

Fig. 28A shows a phase contrast image (TE image) of 150,000 times magnification of the sample 5, and Fig. 28B shows a schematic view of Fig. 28A. In order to explain the details of the vicinity of the side surface of the oxide semiconductor film of the laminated structure in the sample 5, FIG. 29A shows a Z-contrast image (ZC image) of 150,000 times magnification of the sample 5, and FIG. 29B shows a schematic view of FIG. 29A.

Fig. 30A shows a phase contrast image (TE image) of 150,000 times magnification of the sample 6, and Fig. 30B shows a schematic view of Fig. 30A.

As shown in FIG. 25B, in the sample 3, a first In-Ga-Zn oxide film 803 is formed on the glass substrate 801. A second In-Ga-Zn oxide film 805 is formed on the first In-Ga-Zn oxide film 803. A photoresist 807 is provided on the second In-Ga-Zn oxide film 805.

Further, as shown in FIG. 26, in the sample 3, the first In-Ga-Zn oxide film 803 and the second In-Ga-Zn oxide film 805 can confirm the boundary between the two in accordance with the difference in shading. That is, in the present invention In the transistor of one embodiment, even when the oxide semiconductor film and the oxide film contain the same element, the boundary between the two can be confirmed based on the difference in composition.

As shown in FIG. 27B, in the sample 4, a first In-Ga-Zn oxide film 813 is formed on the glass substrate 811. A second In-Ga-Zn oxide film 815 is formed on the first In-Ga-Zn oxide film 813. A photoresist 817 is provided on the second In-Ga-Zn oxide film 815.

In the sample 3 and the sample 4, the angles of the glass substrates 801 and 811 and the side faces of the first In-Ga-Zn oxide films 803 and 813 are set to an angle θ1. The angle between the interface of the first In-Ga-Zn oxide film 803, 813 and the second In-Ga-Zn oxide film 805, 815 and the side faces of the second In-Ga-Zn oxide film 805, 815 Set to angle θ2. As shown in FIGS. 25A and 25B and FIGS. 27A and 27B, it is understood that the angle θ2 is larger than the angle θ1 in the sample 3 and the sample 4.

As shown in FIG. 28B, in the sample 5, a hafnium oxynitride film 823 is formed on the tantalum nitride film 821. An oxide semiconductor film 825 having a laminated structure is formed on the hafnium oxynitride film 823. A hafnium oxynitride film 827 is formed on the hafnium oxynitride film 823 and the stacked oxide semiconductor film 825. Further, a low density region 829 is formed in the hafnium oxynitride film 827.

In the sample 5, the angle between the interface of the yttrium oxynitride film 823 and the oxide semiconductor film 825 of the laminated structure and the side surface of the oxide semiconductor film 825 of the laminated structure is referred to as an angle θ3. As shown in Fig. 29B, in the sample 5, the angle θ3 is an obtuse angle. In addition, the ZC image has a different contrast depending on the difference of the atomic number, and thus it is known that the oxide layer in the laminated structure is half. A film 826 having a composition different from that of the oxide semiconductor film is formed on the side surface of the conductor film 825. When the film 826 was analyzed by Energy Dispersive X-ray Spectrometry (EDX), the film 826 contained tungsten.

As shown in FIG. 30B, in the sample 6, a hafnium oxynitride film 833 is formed on the glass substrate 831. An oxide semiconductor film 835 having a laminated structure is formed on the hafnium oxynitride film 833. A hafnium oxynitride film 837 is formed on the hafnium oxynitride film 833 and the stacked oxide semiconductor film 835.

In the sample 6, the angle between the interface of the yttrium oxynitride film 833 and the oxide semiconductor film 835 of the laminated structure and the side surface of the oxide semiconductor film 835 of the laminated structure is referred to as an angle θ4. As shown in FIG. 30B, in the sample 6, the angle θ4 is substantially the same, and does not change depending on the position of the side surface of the oxide semiconductor film.

As described above, in the oxide semiconductor film of a laminated structure, by using a wet etching method using an aqueous solution of phosphoric acid or phosphoric acid as an etchant, it is possible to use In:Ga:Zn=1:1:1 (atoms). The angle θ1 between the side surface of the In—Ga—Zn oxide film formed by the sputtering target and the interface film of the base film of the In—Ga—Zn oxide film is smaller than that of using In:Ga:Zn=1: An angle θ2 between the side surface of the In—Ga—Zn oxide film formed by the sputtering target of 3:2 (atomic ratio) and the interface of the base film of the In—Ga—Zn oxide film.

100‧‧‧Substrate

104‧‧‧gate electrode

106‧‧‧Multilayer film

106a‧‧‧Oxide semiconductor film

106b‧‧‧Oxide film

106c‧‧‧low resistance zone

106d‧‧‧Low resistance zone

112‧‧‧gate insulating film

116a‧‧‧Source electrode

116b‧‧‧汲electrode

118‧‧‧Protective insulation film

Claims (16)

A semiconductor device comprising: a multilayer film in which an oxide semiconductor film and an oxide film are laminated; a gate electrode; and a gate insulating film, wherein the multilayer film overlaps the gate electrode via the gate insulating film, Wherein the multilayer film has a shape having a first angle of a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film, and a bottom surface of the oxide film and a side surface of the oxide film a second angle, and wherein the first angle is an acute angle and less than the second angle. The semiconductor device according to claim 1, wherein in the multilayer film, an upper end of the oxide semiconductor film substantially coincides with a lower end of the oxide film. The semiconductor device according to claim 1, wherein the first angle and the second angle are each 10° or more and less than 90°. The semiconductor device according to claim 1, wherein in the multilayer film, the oxide film is laminated on the oxide semiconductor film. The semiconductor device according to the first aspect of the invention, wherein the oxide semiconductor film is laminated on the oxide film, and wherein the second oxide film is laminated on the oxide semiconductor film. The semiconductor device according to claim 1, wherein the oxide film contains a chemical element, Wherein the oxide semiconductor film contains the chemical element, and wherein the energy of the conduction band bottom of the oxide film is closer to the vacuum energy level than the energy of the conduction band bottom of the oxide semiconductor film. The semiconductor device of claim 6, wherein the energy of the conduction band bottom of the oxide film is closer to the vacuum energy level of 0.05 eV or more than the energy of the conduction band bottom of the oxide semiconductor film. Below 2eV. The semiconductor device according to the first aspect of the invention, wherein the oxide semiconductor film and the oxide film each comprise an In-M-Zn oxide, wherein M is selected from the group consisting of Al, Ga, Ge, Y, Zr, La One of a group consisting of Ce and Nd, and wherein the oxide film has an atomic ratio of In to M smaller than that of the oxide semiconductor film. The semiconductor device according to the first aspect of the invention, wherein the oxide film is amorphous, wherein the oxide semiconductor film is crystalline, and wherein the c-axis of the crystal portion included in the oxide semiconductor film A normal vector parallel to the surface of the oxide semiconductor film. The semiconductor device according to claim 1, further comprising a source electrode and a drain electrode contacting the multilayer film. The semiconductor device of claim 10, wherein the low resistance region is disposed in an area in the multilayer film and in an interface between the multilayer film and one of the source electrode and the one of the drain electrodes nearby. A semiconductor device according to claim 10, further comprising a second oxide film having the same or different composition as the oxide film, wherein the second oxide film is disposed on an upper surface of the source electrode The upper surface of the electrode and the upper surface of the multilayer film are in contact with each other. A semiconductor device comprising: a gate electrode; an oxide semiconductor film on the gate electrode; and an oxide film on the oxide semiconductor film, wherein a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film The first angle is less than a second angle of the bottom surface of the oxide film and the side surface of the oxide film, and wherein the first angle is an acute angle. The semiconductor device according to claim 13, wherein the oxide semiconductor film contains In-Ga-Zn oxide. The semiconductor device according to claim 13, wherein the oxide film contains In-Ga-Zn oxide. The semiconductor device of claim 13, wherein the oxide semiconductor film comprises an In-Ga-Zn oxide, and wherein the oxide film comprises an In-Ga-Zn oxide.