JP5496745B2 - Thin film field effect transistor and method of manufacturing the same - Google Patents

Description

  The present invention relates to a thin film field effect transistor using an amorphous oxide semiconductor and a method for manufacturing the same, and more particularly, to a thin film field effect transistor having an etching stopper layer, good TTFT characteristics, and high reliability. It relates to a manufacturing method.

Currently, field effect transistors are widely used as semiconductor memory integrated circuits, high-frequency signal amplifiers, and the like.
In addition, as a switching element of a flat thin image display device (FPD) such as a liquid crystal display device (LCD), an electroluminescence display device (EL), a field emission display (FED), etc., a thin film among field effect transistors Field effect transistors (hereinafter also referred to as TFTs) are used. In a TFT used for FPD, an amorphous silicon thin film or a polycrystalline silicon thin film is formed as an active layer on a glass substrate.

A TFT using the above-described amorphous silicon thin film or polycrystalline silicon thin film as an active layer requires a relatively high temperature thermal process. For this reason, although a glass substrate can be used, it is difficult to use a resin substrate having low heat resistance.
Further, the FPD is required to be thinner, lighter, and more resistant to breakage, and the use of a lightweight and flexible resin substrate instead of the glass substrate is also being studied. For this reason, TFTs using an amorphous oxide that can be formed at a low temperature are being actively developed.

A TFT using an amorphous oxide has a substrate, a gate electrode, a gate insulating film, an active layer composed of an amorphous oxide semiconductor, a source electrode and a drain electrode, and the source electrode and the drain electrode are formed on the active layer. Is formed.
In a TFT using an amorphous oxide, a source electrode and a drain electrode are formed by etching a conductive film. For this reason, if an etching stopper layer for protecting the active layer is not formed on the active layer, the active layer may also be etched when the source electrode and the drain electrode are formed, resulting in poor TFT characteristics and uneven characteristics. is there. In an extreme case, the active layer is entirely etched and may not exhibit TFT characteristics. For this reason, a TFT provided with an etching stopper layer or the like for protecting the active layer has been proposed (see, for example, Patent Documents 1 to 3).

A bottom-gate thin film transistor disclosed in Patent Document 1 includes a gate electrode, a first insulating film as a gate insulating film, an oxide semiconductor layer (corresponding to an active layer) as a channel layer, and a protective layer over a substrate. A second insulating film, a source electrode, and a drain electrode are included. In this thin film transistor, the oxide semiconductor layer includes an oxide containing at least one of In, Zn, and Sn, and the second insulating film includes an amorphous oxide insulator formed in contact with the oxide semiconductor layer. And 3.8 × 10 ¹⁹ / cm ³ or more of desorbed gas observed as oxygen by temperature programmed desorption analysis.
The second insulating film functions as an etching stop layer, and is preferably provided so as to cover a part of the channel region, preferably the entire channel region.
Note that the second insulating film is made of amorphous SiOx, amorphous silicon oxynitride, or amorphous aluminum oxide.

Patent Document 2 discloses a channel protection type thin film transistor. In this thin film transistor, a gate electrode is formed on a substrate, a first gate insulating film is formed so as to cover the gate electrode, and a second gate insulating film is formed on the first gate insulating film. Has been. An oxide semiconductor film (corresponding to an active layer) is formed on the second gate insulating film so as to cover the gate electrode. A channel protective film is formed over the oxide semiconductor film in a region overlapping with the gate electrode. Further, a source electrode and a drain electrode are formed over the oxide semiconductor film.
The channel protective film prevents etching of the semiconductor layer in the channel portion when forming the source electrode and the drain electrode. This channel protective film is made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like.

Patent Document 3 describes a thin film field-effect transistor having a gate electrode, a gate insulating film, an active layer containing an amorphous oxide semiconductor, a source electrode, and a drain electrode on a substrate. In this thin film field effect transistor, the mean square roughness of the interface between the gate insulating film and the active layer is less than 2 nm, the carrier concentration of the active layer is 1 × 10 ¹⁵ / cm ³ or more, and the film thickness of the active layer Is 0.5 nm or more and less than 20 nm. In addition, a low carrier concentration layer made of an amorphous oxide semiconductor layer having a carrier concentration of 10 ¹⁶ / cm ³ or less is stacked in contact with the active layer. This low carrier concentration layer also functions as a protective film that protects the active layer from the environment (water, oxygen).

JP 2008-166716 A JP 2009-21612 A JP 2009-141342 A

  As described above, the bottom gate thin film transistor of Patent Document 1 is provided with the second insulating film functioning as an etching stop layer. The thin film transistor disclosed in Patent Document 2 is also provided with a channel protective film that prevents etching of the semiconductor layer in the channel portion. Thus, Patent Documents 1 and 2 are provided with an etching stopper layer.

As described above, the etching stopper layer is formed on the active layer, and the source electrode and the drain electrode are also formed on the active layer. For this reason, in order to form a source electrode and a drain electrode, it is necessary to process an etching stopper layer.
However, as in Patent Documents 1 and 2, when the etching stopper layer is formed of amorphous SiOx, SiO ₂ or the like, it is necessary to process by dry etching or in the case of wet etching, use buffered hydrofluoric acid. Therefore, it is difficult to process the etching stopper layer.

Further, when an SiO ₂ film or SiNx film is formed as an etching stopper layer on the active layer, the active layer is damaged. Due to this damage, the resistance of the active layer is lowered, and the threshold value of the TFT is shifted to minus, or the TFT is not turned off and the TFT operation may not be exhibited.
Note that when the SiO ₂ film, which is an etching stopper layer, is formed by sputtering in a high-concentration oxygen atmosphere, the above-described reduction in resistance of the active layer can be prevented depending on the film formation conditions. Thus, even if the resistance reduction can be avoided, the back channel of the underlying active layer is damaged by oxygen ions. When the active layer is damaged by oxygen ions, the threshold shift becomes large when the reliability of the TFT is evaluated.

  In Patent Document 3, a low carrier concentration layer having the same composition as the active layer is formed so as to function also as a protective film. However, this low carrier concentration layer may be etched to the active layer depending on the etching conditions at the time of forming the source electrode and the drain electrode. As a result, defective TFT characteristics and uneven characteristics may occur, and the reliability of the TFT may decrease.

  An object of the present invention is to provide a thin film field-effect transistor that eliminates the problems of the prior art, has good TFT characteristics, and has high reliability, and a method for manufacturing the same.

  In order to achieve the above object, according to a first aspect of the present invention, at least a gate electrode, an insulating film, an active layer, an etching stopper layer, a source electrode, and a drain electrode are formed on a substrate, and the active layer is formed on the active layer. A thin film field effect transistor in which the etching stopper layer is formed, and the source electrode and the drain electrode are formed on the etching stopper layer, wherein the etching stopper layer includes an In, Ga having a Zn concentration of less than 20%. The active layer is made of an amorphous oxide semiconductor containing In, Ga and Zn, and the Zn concentration is higher than the Zn concentration of the etching stopper layer. It is an object of the present invention to provide a thin film field effect transistor.

Here, in the present invention, the Zn concentration in the active layer indicates the concentration of Zn atoms contained in the amorphous oxide semiconductor film excluding oxygen atoms. As a method for calculating the Zn concentration, Zn concentration = [Amount of Zn atom contained in the amorphous oxide semiconductor film / (In atom amount contained in the amorphous oxide semiconductor film + Atom amount contained in the amorphous oxide semiconductor film + The amount of Zn atoms contained in the amorphous oxide semiconductor film) can be used. The In concentration and the Ga concentration in the active layer are also defined in the same manner as the Zn concentration, and the In concentration and the Ga concentration are obtained in the same manner as the Zn concentration.
In the present invention, the Zn concentration, In concentration, and Ga concentration in the etching stopper layer are the same as the definitions of Zn concentration, In concentration, and Ga concentration in the active layer described above, and the Zn concentration, In concentration in the active layer described above. In addition, in the definition and calculation method of Ga concentration, “amorphous oxide semiconductor” is replaced with “amorphous oxide film”.

In this case, the etching stopper layer preferably has an In concentration of 40% or more and a Ga concentration of 37% or more.
The source electrode and the drain electrode are preferably made of molybdenum or a molybdenum alloy, and molybdenum is particularly preferable.
The thin film field effect transistor may have either a top contact type bottom gate structure or a top contact type top gate structure.
The active layer and the etching stopper layer are preferably in the same shape.

  In the second aspect of the present invention, at least a gate electrode, an insulating film, an active layer, an etching stopper layer, a source electrode, and a drain electrode are formed on a substrate, and the etching stopper layer is formed on the active layer, A method of manufacturing a thin film field effect transistor in which the source electrode and the drain electrode are formed on the etching stopper layer, wherein an aqueous mixed acid solution containing phosphoric acid, acetic acid, and nitric acid is used as an etching solution. A step of forming an electrode and the drain electrode, wherein the etching stopper layer is made of an amorphous oxide containing In, Ga and Zn having a Zn concentration of less than 20%, and the active layer is made of In, Ga And an amorphous oxide semiconductor containing Zn, and the Zn concentration is the etching stopper. Higher than the Zn concentration of the is to provide a method of manufacturing a thin film field effect transistor according to claim.

In this case, the etching stopper layer preferably has an In concentration of 40% or more and a Ga concentration of 37% or more.
Moreover, it is preferable that the said mixed acid aqueous solution contains 70-75 mass% of phosphoric acid, 5-10 mass% of acetic acid, and 1-5 mass% of nitric acid.

A step of forming the gate electrode on the substrate before the step of forming the source electrode and the drain electrode; and a step of forming the insulating film on the substrate so as to cover the gate electrode; In the step of forming the active layer on the insulating film and the step of forming the etching stopper layer on the active layer, and forming the source electrode and the drain electrode, the source electrode and the drain The electrode is preferably formed on the substrate so as to cover a part of the etching stopper layer.
Preferably, after the step of forming the source electrode and the drain electrode, a step of forming a protective layer on the substrate so as to cover the etching stopper layer, the source electrode, and the drain electrode.

As yet another form, before the step of forming the source electrode and the drain electrode, the step of forming the active layer on the substrate, and the step of forming the etching stopper layer on the active layer, In the step of forming the source electrode and the drain electrode, the source electrode and the drain electrode are formed on the substrate so as to cover a part of the etching stopper layer, and the source electrode and the drain electrode are further formed. After the step of forming the drain electrode, a step of forming the insulating film on the substrate so as to cover the etching stopper layer, the source electrode, and the drain electrode, and a step of forming the gate electrode on the insulating film It is preferable to have.
Furthermore, the active layer and the etching stopper layer are preferably formed in the same shape. Moreover, it is preferable that each said process is made at the temperature of 200 degrees C or less.

According to the present invention, the etching stopper layer is made of an amorphous oxide containing In, Ga and Zn having a Zn concentration of less than 20%, thereby forming an active layer made of an amorphous oxide semiconductor containing In, Ga and Zn. The composition is close, the active layer is not damaged, and the resistance is not reduced. For this reason, a thin film field effect transistor exhibiting a good TFT operation can be obtained without the threshold value shifting to minus.
Further, by setting the etching stopper layer to the above composition, etching of the source and drain electrodes and the etching stopper layer is performed with respect to a mixed acid aqueous solution containing phosphoric acid, acetic acid, and nitric acid for forming the source electrode and the drain electrode. The rate ratio can be made sufficiently large. For this reason, when the source electrode and the drain electrode are formed, the active layer is protected by the etching stopper layer, and the active layer is not damaged. Thereby, a thin film field effect transistor having good TFT characteristics and high reliability can be obtained.

Furthermore, the etching stopper layer of the present invention has a composition close to that of the active layer, and can be etched with the same etchant as the active layer. Therefore, the etching stopper layer can be easily processed as compared with the case where the SiO ₂ film is used for the etching stopper layer. Moreover, even if an etching stopper layer is provided, the active layer is not damaged and does not have a low resistance. Therefore, it is not necessary to perform sputtering in a high concentration oxygen atmosphere, and a highly reliable TFT with a small threshold shift can be provided. .

1 is a schematic cross-sectional view showing a thin film field effect transistor according to a first embodiment of the present invention. It is a graph which shows the etching rate ratio with respect to the molybdenum of the IGZO film by Zn density | concentration when phosphoric acid 73 mass%, acetic acid 7 mass%, and nitric acid 3 mass% are contained in the etching liquid and the temperature is 25 degreeC. . The etching rate ratio of the IGZO film to molybdenum according to the In concentration and Ga concentration when a mixed acid aqueous solution containing 73 mass% phosphoric acid, 7 mass% acetic acid and 3 mass% nitric acid at a temperature of 25 ° C. is used in the etching solution is shown. It is a graph. (A)-(c) is typical sectional drawing which shows the manufacturing method of the thin film field effect transistor which concerns on the 1st Embodiment of this invention in process order. It is typical sectional drawing which shows the thin film field effect transistor which concerns on the 2nd Embodiment of this invention. (A)-(c) is typical sectional drawing which shows the manufacturing method of the thin film field effect transistor which concerns on the 2nd Embodiment of this invention in process order. It is typical sectional drawing which shows the thin film field effect transistor which concerns on the 3rd Embodiment of this invention. (A)-(d) is typical sectional drawing which shows the manufacturing method of the thin film field effect transistor which concerns on the 3rd Embodiment of this invention in process order. It is typical sectional drawing which shows the thin film field effect transistor which concerns on the 4th Embodiment of this invention. (A)-(d) is typical sectional drawing which shows the manufacturing method of the thin film field effect transistor which concerns on the 4th Embodiment of this invention in process order.

Hereinafter, a thin film field effect transistor of the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.
FIG. 1 is a schematic cross-sectional view showing a thin film field effect transistor according to the first embodiment of the present invention.

  1 includes a substrate 12, a gate electrode 14, a gate insulating film 16, an active layer 18 functioning as a channel layer, and an etching stopper layer (hereinafter referred to as a TFT). , ES layer) 30, source electrode 20 a, drain electrode 20 b, and protective layer 22. The TFT 10 is an active element having a function of switching a current between the source electrode 20a and the drain electrode 20b by applying a voltage to the gate electrode 14 to control a current flowing through the active layer 18. The TFT 10 shown in FIG. 1 is generally called a top contact type bottom gate structure.

  In the TFT 10, a gate electrode 14 is formed on the surface 12 a of the substrate 12, and a gate insulating film 16 is formed on the surface 12 a of the substrate 12 so as to cover the gate electrode 14. An active layer 18 is formed on the surface 16 a of the gate insulating film 16. An ES layer 30 is provided on the surface 18 a of the active layer 18.

  A source electrode 20 a is formed on the surface 16 a of the gate insulating film 16 so as to cover the surface 18 a of the active layer 18 and a part of the surface 30 a of the ES layer 30. Further, the drain electrode 20b that forms a pair with the source electrode 20a covers the surface 16a of the gate insulating film 16 so as to cover a part of the surface 18a of the active layer 18 and the surface 30a of the ES layer 30. Is formed. That is, the source electrode 20 a and the drain electrode 20 b are formed so as to cover the surface 18 a of the active layer 18 and a part of the surface 30 a of the ES layer 30 with the upper side of the surface 30 a of the ES layer 30. A protective layer 22 is formed so as to cover the source electrode 20a, the ES layer 30, and the drain electrode 20b.

The substrate 12 is not particularly limited. For the substrate 12, for example, an inorganic material such as YSZ (zirconia stabilized yttrium) and glass can be used. Further, the substrate 12 includes polyesters such as polyethylene terephthalate (PET), polybutylene terephthalate (PBT), and polyethylene naphthalate (PEN), polystyrene, polycarbonate, polyethersulfone, polyarylate, allyl diglycol carbonate, polyimide, polycyclo Organic materials such as synthetic resins such as olefin, norbornene resin and poly (chlorotrifluoroethylene) can also be used.
When an organic material is used for the substrate 12, heat resistance, dimensional stability, solvent resistance, electrical insulation, workability, low air permeability, low moisture absorption, and the like are preferable.
In addition, when glass is used for the substrate 12, it is preferable to use alkali-free glass in order to reduce eluted ions from the glass. In addition, when using soda-lime glass for the board | substrate 12, it is preferable to use what gave barrier coats, such as a silica.

The substrate 12 can be a flexible substrate. The flexible substrate preferably has a thickness of 50 μm to 500 μm. This is because if the thickness of the flexible substrate is less than 50 μm, it is difficult for the substrate itself to maintain sufficient flatness. Further, if the thickness of the flexible substrate exceeds 500 μm, the flexibility of the substrate itself becomes poor, and it becomes difficult to bend the substrate itself freely.
As the flexible substrate, an organic plastic film having a high transmittance is preferable. Examples of the organic plastic film include polyesters such as polyethylene terephthalate (PET), polybutylene phthalate (PBT), and polyethylene naphthalate (PEN), polystyrene, polycarbonate, polyethersulfone, polyarylate, polyimide, polycycloolefin, and norbornene. A resin or a plastic film such as poly (chlorotrifluoroethylene) is used.
When a plastic film or the like is used for the substrate 12, an insulating layer is formed and used if the electrical insulation is insufficient.

The substrate 12 can be provided with a moisture permeation preventive layer (gas barrier layer) on the front surface or the back surface in order to prevent permeation of water vapor and oxygen.
As the material for the moisture permeation preventing layer (gas barrier layer), inorganic materials such as silicon nitride and silicon oxide are preferably used. The moisture permeation preventing layer (gas barrier layer) can be formed by, for example, a high frequency sputtering method.
In addition, when using a thermoplastic substrate, you may provide a hard-coat layer, an undercoat layer, etc. further as needed.

  The gate electrode 14 is made of, for example, a metal such as Al, Mo, Cr, Ta, Ti, Au, or Ag, or an alloy thereof, an alloy such as Al—Nd, APC, tin oxide, zinc oxide, indium oxide, or indium tin oxide. It is formed using a metal oxide conductive material such as (ITO) or indium zinc oxide (IZO), an organic conductive compound such as polyaniline, polythiophene, or polypyrrole, or a mixture thereof. As the gate electrode 14, it is preferable to use Mo, Mo alloy or Cr from the viewpoint of reliability of TFT characteristics. The thickness of the gate electrode 14 is, for example, 10 nm to 1000 nm.

  The method for forming the gate electrode 14 is not particularly limited. The gate electrode 14 is formed by using, for example, a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, or a chemical method such as CVD or plasma CVD method. It is formed. Among these, a forming method is appropriately selected in consideration of suitability with the material constituting the gate electrode 14. For example, when the gate electrode 14 is formed using Mo or Mo alloy, a DC sputtering method is used. Further, when an organic conductive compound is used for the gate electrode 14, a wet film forming method is used.

The gate insulating film 16 is made of an insulator such as SiO ₂ , SiNx, SiON, Al ₂ O ₃ , YsO ₃ , Ta ₂ O ₅ , or HfO ₂ , or a mixed crystal compound containing at least two of these compounds. . A polymer insulator such as polyimide can also be used for the gate insulating film 16.
The thickness of the gate insulating film 16 is preferably 10 nm to 10 μm. The gate insulating film 16 needs to be thick to some extent in order to reduce leakage current and increase voltage resistance. However, when the thickness of the gate insulating film 16 is increased, the driving voltage of the TFT 10 is increased. Therefore, the thickness of the gate insulating film 16 is more preferably 50 nm to 1000 nm in the case of an inorganic insulator, and more preferably 0.5 μm to 5 μm in the case of a polymer insulator.
Note that when a high dielectric constant insulator such as HfO ₂ is used for the gate insulating film 16, the transistor can be driven at a low voltage even when the film thickness is increased. It is particularly preferable to use a high dielectric constant insulator.

The source electrode 20a and the drain electrode 20b are made of, for example, a metal such as Al, Mo, Cr, Ta, Ti, Au, or Ag, or an alloy thereof, an alloy such as Al—Nd, APC, tin oxide, zinc oxide, or indium oxide. , Indium tin oxide (ITO), indium zinc oxide (IZO), and other metal oxide conductive materials.
As the source electrode 20a and the drain electrode 20b, Mo or Mo alloy is preferably used from the viewpoint of reliability of TFT characteristics and an etching rate ratio with the ES layer 30, and Mo is particularly preferable. In addition, the thickness of the source electrode 20a and the drain electrode 20b is 10 nm-1000 nm, for example.

The source electrode 20a and the drain electrode 20b are formed by forming the above-described film, forming a resist pattern on the film using a photolithography method, and etching the film.
Note that there is no particular limitation on the method of forming the above-described film formed by the source electrode 20a and the drain electrode 20b. The above-mentioned film is formed using, for example, a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, or a chemical method such as CVD or plasma CVD method. It is formed.

For example, when the source electrode 20a and the drain electrode 20b are formed of Mo or Mo alloy, for example, a Mo film or a Mo alloy film is formed by using a DC sputtering method.
Then, using a photolithography method, a resist pattern is formed on the Mo film or the Mo alloy film, and the Mo film or the Mo alloy film is etched with an etchant to form the source electrode 20a and the drain electrode 20b.
As the etching solution, a mixed acid aqueous solution containing phosphoric acid, acetic acid, and nitric acid is used. This mixed acid aqueous solution contains, for example, 70 to 75% by mass of phosphoric acid, 5 to 10% by mass of acetic acid, 1 to 5% by mass of nitric acid, and the balance is water.

The active layer 18 is composed of an amorphous oxide semiconductor containing In, Ga, and Zn. The active layer 18 has a Zn concentration higher than that of the ES layer 30.
In the active layer 18, the Zn concentration (Zn / (Zn + In + Ga)) is preferably 20 to 50% when the total atomic weight excluding oxygen is 100%.

The ES layer 30 protects the active layer 18 from being etched when the source electrode 20a and the drain electrode 20b are formed. The ES layer 30 is composed of an amorphous oxide containing In, Ga, and Zn.
In the ES layer 30, the Zn concentration (Zn / (Zn + In + Ga)) is less than 20% when the entire atomic weight excluding oxygen is 100%. In the ES layer 30, the In concentration (In / (Zn + In + Ga)) is preferably 40% or more, and the Ga concentration (Ga / (Zn + In + Ga)) is preferably 37% or more.

Here, the Zn concentration in the active layer 18 and the ES layer 30 indicates the concentration of Zn atoms contained in the amorphous oxide semiconductor film or amorphous oxide film excluding oxygen atoms, as described above.
The Zn concentration in the active layer 18 and the ES layer 30 is calculated as follows: Zn concentration = [Amount of Zn atom contained in the amorphous oxide semiconductor film (amorphous oxide film) / (Amorphous oxide semiconductor film (amorphous oxide film)] In atomic weight contained therein + Ga atomic weight contained in amorphous oxide semiconductor film (amorphous oxide film) + Zn atomic weight contained in amorphous oxide semiconductor film (amorphous oxide film))] can be used. The In concentration and the Ga concentration in the active layer 18 and the ES layer 30 are also defined in the same manner as the Zn concentration, and the In concentration and the Ga concentration are obtained in the same manner as the Zn concentration.
Note that values obtained by XRF (fluorescence X-ray analysis) are used as the Zn atomic weight, In atomic weight, and Ga atomic weight in the amorphous oxide semiconductor film (amorphous oxide film).

The entire ES layer 30 may be used as the Zn concentration, In concentration, and Ga concentration in the ES layer 30, and the concentration at the surface 30a portion where the ES layer 30 is in contact with the source electrode 20a and the drain electrode 20b, or the upper surface may be used.
Note that the Zn concentration of the ES layer 30 is preferably 5% or more and less than 20%. This is because when the Zn concentration is less than 5%, the amorphous property of the oxide semiconductor film is deteriorated and crystallization is easily caused.
The In concentration of the ES layer 30 is preferably 40% to 58%, and the Ga concentration of the ES layer 30 is preferably 37% to 55%.

  When the source electrode 20a and the drain electrode 20b made of Mo or Mo alloy are formed using the above-described mixed acid aqueous solution as an etching solution, the ES layer 30 is also in contact with the etching solution. In this case, if the ES layer 30 is not resistant to the etching solution, the ES layer 30 is also etched. For this reason, in this invention, the etching rate with respect to the mixed acid aqueous solution of ES layer 30 is reduced so that ES layer 30 may not be etched. That is, the ES layer 30 has a sufficiently high etching rate ratio (selection ratio) with Mo constituting the source electrode 20a and the drain electrode 20b.

In the present invention, when the Zn concentration of the ES layer 30 is less than 20%, the etching rate ratio with molybdenum exceeds 10 with respect to a mixed acid aqueous solution containing phosphoric acid, acetic acid, and nitric acid, as shown in FIG. . For this reason, the etching of the active layer 18 is suppressed when the source electrode 20a and the drain electrode 20b are formed.
When the Ga concentration of the ES layer 30 is 37% or more, as shown in FIG. 3, the etching rate ratio with molybdenum exceeds 10 with respect to the mixed acid aqueous solution containing phosphoric acid, acetic acid, and nitric acid. Therefore, etching of the ES layer 30 is suppressed when forming the source electrode 20a and the drain electrode 20b.
Even when the In concentration of the ES layer 30 is 40% or more, the etching rate ratio with molybdenum exceeds 10 with respect to the mixed acid aqueous solution containing phosphoric acid, acetic acid, and nitric acid, as shown in FIG. Therefore, etching of the ES layer 30 is suppressed when forming the source electrode 20a and the drain electrode 20b.

As described above, in the present invention, the composition of the ES layer 30 is such that the Zn concentration is less than 20%, and the etching rate ratio between the source electrode 20a and the drain electrode 20b with respect to the mixed acid aqueous solution is sufficiently high. It is said. Thereby, when forming the source electrode 20a and the drain electrode 20b, the etching of the ES layer 30 can be suppressed and the function as an etching stopper layer can be sufficiently achieved.
Note that the composition of the ES layer 30 is such that the Zn concentration is less than 20%, the In concentration is 40% or more, and the Ga concentration is 37% or more, thereby etching the source electrode 20a and the drain electrode 20b with respect to the mixed acid aqueous solution. The rate ratio can be made sufficiently higher. Thereby, the etching of the ES layer 30 can be suppressed more reliably.

The protective layer 22 is formed for the purpose of protecting the active layer 18, the ES layer 30, the source electrode 20 a and the drain electrode 20 b from the deterioration due to the atmosphere and insulating the electronic device manufactured on the transistor.
The protective layer 22 of the present embodiment is formed by, for example, photosensitive acrylic resin being heat-cured in a nitrogen atmosphere.

The protective layer 22 is, for example, MgO, SiO, SiO ₂ , Al ₂ O ₃ , GeO, NiO, CaO, BaO, Fe ₂ O ₃ , Y ₂ O ₃ , Ga ₂ O ₃ other than the above-described photosensitive acrylic resin. Or metal oxides such as TiO ₂ , metal nitrides such as SiNx, SiNxOy, metal fluorides such as MgF ₂ , LiF, AlF ₃ , or CaF ₂ , polyethylene, polypropylene, polymethyl methacrylate, polyimide, polyurea, polytetrafluoro Copolymerization obtained by copolymerizing ethylene, polychlorotrifluoroethylene, polydichlorodifluoroethylene, a copolymer of chlorotrifluoroethylene and dichlorodifluoroethylene, and a monomer mixture containing tetrafluoroethylene and at least one comonomer Combined and copolymerized main chain with cyclic structure Fluorine-containing copolymer to water absorption of 1% by weight of the water absorbing material, it is also possible to use a water absorption of 0.1% or less of the proof substance.

  The method for forming the protective layer 22 is not particularly limited. The protective layer 22 is formed by, for example, vacuum deposition, sputtering, reactive sputtering, MBE (molecular beam epitaxy), cluster ion beam, ion plating, plasma polymerization (high frequency excitation ion plating), plasma. A CVD method, a laser CVD method, a thermal CVD method, a gas source CVD method, a coating method, a printing method, or a transfer method can be applied.

Next, a manufacturing method of the TFT 10 of this embodiment will be described with reference to FIGS.
First, for example, a glass substrate is prepared as the substrate 12.
Next, a molybdenum film (not shown) having a thickness of, for example, 40 nm is formed on the surface 12a of the substrate 12 by using a DC sputtering method.
Next, a resist film (not shown) is formed on the molybdenum film, and a resist pattern is formed using a photolithography method.
Next, for example, the molybdenum film is etched using a mixed acid aqueous solution containing 70 to 75% by mass of phosphoric acid, 5 to 10% by mass of acetic acid, 1 to 5% by mass of nitric acid, and the balance being water. To do. Thereafter, the resist film is peeled off. As a result, a gate electrode 14 made of molybdenum is formed on the surface 12a of the substrate 12 as shown in FIG.

Next, an SiO ₂ film (not shown) to be the gate insulating film 16 is formed on the entire surface 12a of the substrate 12 so as to cover the gate electrode 14 by using an RF sputtering method to a thickness of 200 nm, for example. Form.
Next, a first IGZO film (not shown) to be the active layer 18 is formed on the surface of the SiO ₂ film to a thickness of, for example, 30 nm using a DC sputtering method.
Next, a second IGZO film (not shown) to be the ES layer 30 is formed on the surface of the first IGZO film to a thickness of 20 nm using a DC sputtering method under a pressure of 0.37 Pa. Film. As described above, the SiO ₂ film, the first IGZO film, and the second IGZO film are successively formed on the substrate 12 in this order.

Next, a resist film (not shown) is formed on the second IGZO film. Then, a resist pattern is formed using a photolithography method. Then, for example, the second IGZO film and the first IGZO film are etched using 5% oxalic acid water. Thereafter, the resist film is peeled off. Thereby, the active layer 18 is formed.
Next, a resist film (not shown) is formed on the second IGZO film. Then, a resist pattern is formed using a photolithography method. Then, for example, only the second IGZO film is etched using 5% oxalic acid water. Thereafter, the resist film is peeled off. Thereby, the ES layer 30 is formed.

Again, a resist film (not shown) is formed on the SiO ₂ film / first IGZO film / second IGZO film, and a resist pattern is formed by photolithography. Then, for example, the SiO ₂ film is etched using buffered hydrofluoric acid. Thereafter, the resist film is peeled off. In this way, as shown in FIG. 4B, the ES layer 30, the active layer 18, and the gate insulating film 16 are patterned.

The first IGZO film constituting the active layer 18 includes In, Ga, and Zn, has a Zn concentration of 20% or more, and is higher in Zn concentration than the ES layer 30.
The second IGZO film constituting the ES layer 30 contains In, Ga, and Zn and has a Zn concentration of less than 20%, preferably an In concentration of 40% or more and a Ga concentration of 37% or more.
In addition, when the first IGZO film and the second IGZO film are formed by the DC sputtering method, targets whose compositions are adjusted in advance so as to have the respective compositions of the first IGZO film and the second IGZO film described above are used. Used.

Next, for example, a molybdenum film (not shown) to be the source electrode 20a and the drain electrode 20b is formed on the surface 16a of the gate insulating film 16 so as to cover the ES layer 30 and the active layer 18, and a DC sputtering method is used. The film is formed to a thickness of 100 nm under the condition of a pressure of 0.37 Pa.
Next, a resist film (not shown) is formed on the molybdenum film, and a resist pattern is formed using a photolithography method in the same manner as the gate electrode 14. Thereafter, for example, the molybdenum film is etched using a mixed acid aqueous solution containing 70 to 75% by mass of phosphoric acid, 5 to 10% by mass of acetic acid, 1 to 5% by mass of nitric acid, and the balance being water. Etching is preferably performed at a liquid temperature of the mixed acid aqueous solution at the time of etching of 35 ° C. or lower, more preferably at a liquid temperature of 15 ° C. to 25 ° C. After the etching, the resist film is peeled off. Thereby, as shown in FIG. 4C, the source electrode 20a and the drain electrode 20b formed so as to cover a part of the surface 30a of the ES layer 30 and a part of the surface 18a of the active layer 18 are obtained. .

Next, for example, a photosensitive acrylic resin is applied so as to cover the ES layer 30, the source electrode 20a, and the drain electrode 20b. Then, an acrylic resin film is patterned by using a photolithography method. In addition, the curing conditions of the acrylic resin at the time of pattern formation are, for example, a temperature of 180 ° C. and 30 minutes.
Next, post-annealing is performed for 1 hour at a temperature of 180 ° C. in a nitrogen atmosphere. As described above, the TFT 10 shown in FIG. 1 can be formed.

In the TFT 10 of the present embodiment, even when the ES layer 30 that protects the active layer 18 from being etched is provided on the surface 18a of the active layer 18, the ES layer 30 and the active layer 18 are close in composition, so the active layer 18 Is not damaged and does not reduce resistance. For this reason, the TFT 10 exhibits a good TFT operation without the threshold value shifting to minus.
Further, the etching rate ratio of the source electrode 20a and the drain electrode 20b to the etching solution and the ES layer 30 is increased to 10 or more, and the etching resistance of the ES layer 30 is increased. Thus, the etching of the underlying ES layer 30 is reduced during the etching for forming the source electrode 20a and the drain electrode 20b, and the underlying active layer 18 is not damaged. For this reason, it is possible to uniformly form the TFT 10 exhibiting good TFT characteristics and high reliability in the surface.

Furthermore, in the manufacturing process of the TFT 10, the ES layer 30 can be etched with the same etching solution as the active layer 18, and the ES layer 30 can be easily formed as compared with the case where an SiO ₂ film is used as an etching stopper layer. Can be processed. In addition, even if the ES layer 30 is provided, the active layer 18 is not damaged and does not have a low resistance. Therefore, it is not necessary to form the ES layer using a sputtering method in a high concentration oxygen atmosphere, and the threshold shift is small. A highly reliable TFT can be provided.

  In the manufacturing process of the TFT 10, the resist film formation, resist pattern formation, various film formation, and protective layer 22 formation are all performed at a temperature of 200 ° C. or less. Thus, since each process is performed at a temperature of 200 ° C. or lower, for example, PET, PEN or the like having low heat resistance can be used for the substrate 12. Since these PET and PEN are flexible, a flexible transistor can be obtained.

Next, a second embodiment will be described.
FIG. 5 is a schematic sectional view showing a thin film field effect transistor according to the second embodiment of the present invention.
In this embodiment, the same components as those of the TFT 10 of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The TFT 10a shown in FIG. 5 is different from the TFT 10 shown in FIG. 1 in that the ES layer 32 has the same shape as that of the active layer 18, and other configurations are the same as those of the TFT 10 shown in FIG. Since the ES layer 32 is the same as the ES layer 30 of the first embodiment except for the shape, detailed description thereof is omitted.

Next, a manufacturing method of the TFT 10a of this embodiment will be described.
6A to 6C are schematic cross-sectional views showing a method of manufacturing a thin film field effect transistor according to the second embodiment of the present invention in the order of steps.
In the manufacturing method of the TFT 10a, detailed description of the same steps as those of the manufacturing method of the TFT 10 of the first embodiment shown in FIGS.

  In the manufacturing method of the TFT 10a of this embodiment, the formation process of the ES layer 32 is the same as the manufacturing method of the TFT 10 of the first embodiment, except that the manufacturing method of the TFT 10 of the first embodiment is different. For this reason, the detailed description of the steps of FIGS. 6A and 6C other than the step of forming the ES layer 32 is omitted.

In the manufacturing method of the TFT 10a of this embodiment, first, as in the first embodiment, the gate electrode 14 is formed on the surface 12a of the substrate 12 as shown in FIG.
Next, in the same manner as in the first embodiment, the SiO ₂ film that becomes the gate insulating film 16, the first IGZO film (not shown) that becomes the active layer 18, and the second IGZO film that becomes the ES layer 32 ( (Not shown) are successively formed on the substrate 12.

Next, a resist film (not shown) is formed on the second IGZO film. Then, after forming a resist pattern using a photolithography method, the second IGZO film and the first IGZO film are etched. Thereafter, the resist film is peeled off. Thereby, the ES layer 32 and the active layer 18 are formed.
Again, a resist film (not shown) is formed on the second IGZO film, and a resist pattern is formed using a photolithography method. Then, the SiO ₂ film is etched. Thereafter, the resist film is peeled off. As a result, the ES layer 32 and the active layer 18 are patterned on the surface 16a of the gate insulating film 16, as shown in FIG. 6B. In this case, the ES layer 32 formed on the surface 18 a of the active layer 18 is formed in the same shape as the active layer 18.

Note that the gate insulating film 16, the ES layer 32, and the active layer 18 can be etched in the same manner as in the first embodiment.
Further, the second IGZO film constituting the ES layer 32 has the same composition as the second IGZO film constituting the ES layer 30 of the first embodiment.
When the first IGZO film and the second IGZO film are formed by a DC sputtering method as in the first embodiment, a target whose composition is adjusted in advance is used.

  Next, in the same manner as in the first embodiment, a molybdenum film (not shown) that becomes the source electrode 20 a and the drain electrode 20 b on the surface 16 a of the gate insulating film 16 so as to cover the ES layer 32 and the active layer 18. ). Then, a resist pattern is formed using a photolithography method. Thereafter, the molybdenum film is etched using a mixed acid aqueous solution having the same components as those in the first embodiment. Thereby, as shown in FIG. 6C, the source electrode 20a and the drain electrode 20b formed so as to cover a part of the surface 32a of the ES layer 32 are obtained.

Next, as in the first embodiment, the protective layer 22 that covers the ES layer 32, the source electrode 20a, and the drain electrode 20b is formed. As described above, the TFT 10a shown in FIG. 5 can be formed.
Although the ES layer 32 and the active layer 18 are formed together at one time, the present invention is not limited to this. The ES layer 32 and the active layer 18 may be formed by forming and etching a resist pattern using a photolithography method, respectively.

In this embodiment, even if the ES layer 32 has the same shape as the active layer 18, the ES layer 32 has a composition close to that of the active layer 18, and the ES layer 32 also functions as an active layer and operates as a TFT.
Further, by making the ES layer 32 the same shape as the active layer 18, the ES layer 32 and the active layer 18 can be formed using a resist pattern formed with the same mask. As a result, the number of masks necessary for forming the resist pattern can be reduced, the cost can be reduced, and the manufacturing process can be simplified. Thereby, production efficiency can also be improved.

In addition, in this embodiment, the same effects as those of the TFT 10 of the first embodiment and the manufacturing method thereof can be obtained. For this reason, the TFT 10a of the present embodiment exhibits a good TFT operation without the threshold value shifting to minus. In addition, the TFT 10a exhibiting good TFT characteristics and high reliability can be uniformly formed in the surface.
Furthermore, the ES layer 32 can be easily formed as compared with the prior art, and processing can be facilitated.
Also in the manufacturing process of the TFT 10a, the formation of the resist film, the formation of the resist pattern, the formation of various films, and the formation of the protective layer 22 are all performed at a temperature of 200 ° C. or less. Thus, since each process is performed at a temperature of 200 ° C. or lower, a substrate 12 having low heat resistance such as PET or PEN can be used. Thus, a flexible transistor can be obtained.

Next, a third embodiment will be described.
FIG. 7 is a schematic cross-sectional view showing a thin film field effect transistor according to the third embodiment of the present invention.
In this embodiment, the same components as those of the TFT 10 of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The TFT 10b shown in FIG. 7 is generally called a top contact type top gate structure. The TFT 10b is different from the TFT 10 shown in FIG. 1 in that the arrangement position of the gate electrode 14 and the arrangement positions of the ES layer 30, the active layer 18, the source electrode 20a, and the drain electrode 20b are upside down. Differently, the other configuration is the same as that of the TFT 10 shown in FIG.

In the TFT 10 b shown in FIG. 7, an active layer 18 is formed on the surface 12 a of the substrate 12. An ES layer 30 is formed on the surface 18 a of the active layer 18. A source electrode 20 a is formed on the surface 12 a of the substrate 12 so as to cover a part of the surface 18 a of the active layer 18 and a part of the surface 30 a of the ES layer 30. Further, the drain electrode 20b paired with the source electrode 20a covers the surface 12a of the substrate 12 so as to cover a part of the surface 18a of the active layer 18 and the surface 30a of the ES layer 30, and is opposed to the source electrode 20a. Is formed. An insulating film 24 is formed on the substrate 12 so as to cover the ES layer 30, the active layer 18, the source electrode 20a, and the drain electrode 20b. A gate electrode 14 is formed on the surface 24 a of the insulating film 24. A protective layer 22 is formed on the surface 24 a of the insulating film 24 so as to cover the gate electrode 14.
The insulating film 24 is for insulating the ES layer 30, the active layer 18, the source electrode 20a, the drain electrode 20b, and the gate electrode 14. Since the insulating film 24 has the same configuration as that of the gate insulating layer 16 of the TFT 10 shown in FIG. 1, detailed description thereof is omitted.

Next, a manufacturing method of the TFT 10b of this embodiment will be described.
FIGS. 8A to 8D are schematic cross-sectional views showing a method of manufacturing a thin film field effect transistor according to the third embodiment of the present invention in the order of steps.
In the manufacturing method of the TFT 10b, detailed description of the same steps as those of the manufacturing method of the TFT 10 of the first embodiment shown in FIGS.

In the manufacturing method of the TFT 10b of this embodiment, first, for example, a glass substrate is prepared as the substrate 12.
Next, a first IGZO film (not shown) to be the active layer 18 is formed on the surface 12a of the substrate 12 to a thickness of, for example, 30 nm using a DC sputtering method.
Next, a second IGZO film (not shown) to be the ES layer 30 is formed on the surface of the first IGZO film to a thickness of 20 nm using a DC sputtering method under a pressure of 0.37 Pa. Film. In this way, the first IGZO film and the second IGZO film are continuously formed.

Next, a resist film (not shown) is formed on the second IGZO film. Then, after forming a resist pattern using a photolithography method, the second IGZO film and the first IGZO film are etched using, for example, 5% oxalic acid water. Thereafter, the resist film is peeled off.
Again, a resist film (not shown) is formed on the second IGZO film, and a resist pattern is formed using a photolithography method. Then, only the second IGZO film is etched using, for example, 5% oxalic acid water. Thereafter, the resist film is peeled off. As a result, as shown in FIG. 8A, the active layer 18 is formed on the surface 12a of the substrate 12, and the ES layer 30 is formed on the surface 18a.

Next, a source electrode 20a and a drain electrode 20b are formed on the surface 12a of the substrate 12 so as to cover the ES layer 30 and the active layer 18, for example, a molybdenum film (not shown) is formed to a thickness of 100 nm by DC sputtering. It forms on the conditions of 0.37 Pa using a method.
Next, a resist film (not shown) is formed on the molybdenum film, and a resist pattern is formed using a photolithography method. Then, the molybdenum film is etched using a mixed acid aqueous solution having the same component as that of the first embodiment. After the etching, the resist film is peeled off. Thereby, as shown in FIG. 8B, the source electrode 20a and the drain electrode 20b formed so as to cover the surface 30a of the ES layer 30 and a part of the surface 18a of the active layer 18 are obtained.

Next, as shown in FIG. 8C, for example, a SiO ₂ film (not shown) having a thickness of 200 nm, which becomes the insulating film 24 so as to cover the active layer 18, the source electrode 20a, and the drain electrode 20b. Is formed using an RF sputtering method. A resist film (not shown) is formed on the SiO ₂ film, and a resist pattern is formed using a photolithography method. Then, for example, the insulating film 24 is formed by etching the SiO ₂ film using buffered hydrofluoric acid.
Next, for example, a molybdenum film (not shown) to be the gate electrode 14 having a thickness of 40 nm is formed on the surface 24a of the insulating film 24 by using a DC sputtering method.
Next, a resist film (not shown) is formed on the molybdenum film, and a resist pattern is formed using a photolithography method.
Next, the molybdenum film is etched using a mixed acid aqueous solution having the same components as in the first embodiment. Thereafter, the resist film is peeled off. As a result, a gate electrode 14 made of molybdenum is formed on the surface 24 a of the insulating film 24 as shown in FIG.

Next, for example, a photosensitive acrylic resin is applied to the surface 24 a of the insulating film 24 so as to cover the gate electrode 14. Then, an acrylic resin film is patterned by using a photolithography method. In addition, the curing conditions of the acrylic resin at the time of pattern formation are, for example, a temperature of 180 ° C. and 30 minutes.
Next, post-annealing is performed for 1 hour at a temperature of 180 ° C. in a nitrogen atmosphere. As described above, the TFT 10b shown in FIG. 7 can be formed.

Also in this embodiment, the same effects as those of the TFT 10 of the first embodiment and the manufacturing method thereof can be obtained. For this reason, the TFT 10b of the present embodiment exhibits a good TFT operation without the threshold value shifting to minus. In addition, the TFT 10b exhibiting good TFT characteristics and high reliability can be uniformly formed in the surface.
Furthermore, the ES layer 32 can be easily formed as compared with the prior art, and processing can be facilitated.
Also in the manufacturing process of the TFT 10b of this embodiment, the formation of the resist film, the formation of the resist pattern, the formation of various films, and the formation of the protective layer 22 are all carried out at a temperature of 200 ° C. Thus, since each process is performed at a temperature of 200 ° C. or lower, a substrate 12 having low heat resistance such as PET or PEN can be used. Thereby, a flexible TFT can be obtained.

Next, a fourth embodiment will be described.
FIG. 9 is a schematic cross-sectional view showing a thin film field effect transistor according to the fourth embodiment of the present invention.
In this embodiment, the same components as those of the TFT 10b of the third embodiment shown in FIG. 7 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The TFT 10c shown in FIG. 9 is different from the TFT 10b shown in FIG. 7 in that the ES layer 32 has the same shape as that of the active layer 18, and other configurations are the same as those of the TFT 10b shown in FIG. . As described above, the ES layer 32 has the same composition as the ES layer 30 of the first embodiment. For this reason, the detailed description is abbreviate | omitted.

Next, a manufacturing method of the TFT 10c of this embodiment will be described.
10A to 10D are schematic cross-sectional views showing a method of manufacturing a thin film field effect transistor according to the fourth embodiment of the present invention in the order of steps.
In the manufacturing method of the TFT 10c, detailed description of the same steps as the manufacturing method of the TFT 10b of the third embodiment shown in FIGS. 8A to 8D is omitted.

  In the manufacturing method of the TFT 10c of this embodiment, the formation process of the ES layer 32 is the same as the manufacturing method of the TFT 10b of the third embodiment, except that the manufacturing method of the TFT 10b of the third embodiment is different. For this reason, the detailed description of the steps of FIGS. 10B to 10D other than the step of forming the ES layer 32 is omitted.

In the manufacturing method of the TFT 10c of this embodiment, first, similarly to the third embodiment, a first IGZO film (not shown) that becomes the active layer 18 on the surface 12a of the substrate 12, and the first A second IGZO film (not shown) to be the ES layer 32 is continuously formed on the surface of the IGZO film.
Next, a resist film (not shown) is formed on the second IGZO film. Then, a resist pattern is formed using a photolithography method. Then, the second IGZO film and the first IGZO film are etched using, for example, 5% oxalic acid water. Thereafter, the resist film is peeled off. As a result, as shown in FIG. 10A, the ES layer 32 and the active layer 18 are patterned. In this case, the ES layer 32 formed on the surface 18 a of the active layer 18 is formed in the same shape as the active layer 18.

In addition, the 2nd IGZO film | membrane which comprises the ES layer 32 is the same composition as the 2nd IGZO film | membrane which comprises the ES layer 30 of 1st Embodiment.
As in the third embodiment, when the first IGZO film and the second IGZO film are formed by DC sputtering, a target whose composition is adjusted in advance is used.

  Next, similarly to the third embodiment, a molybdenum film (not shown) to be the source electrode 20a and the drain electrode 20b is formed on the surface 12a of the substrate 12 so as to cover the ES layer 32 and the active layer 18. Form. Then, a resist pattern is formed using a photolithography method. Thereafter, the molybdenum film is etched using a mixed acid aqueous solution having the same components as those in the first embodiment, as in the third embodiment. Thereby, as shown in FIG. 10B, the source electrode 20a and the drain electrode 20b formed so as to cover a part of the surface 32a of the ES layer 32 are obtained.

Next, as in the third embodiment, as shown in FIG. 10C, an insulating film 24 that covers the ES layer 32, the source electrode 20a, and the drain electrode 20b is formed.
Next, as in the third embodiment, as shown in FIG. 10D, the gate electrode 14 made of molybdenum is formed on the surface 24a of the insulating film 24, and the gate electrode 14 is covered. A protective layer 22 is formed on the surface 24 a of the insulating film 24. Thereafter, post-annealing is performed for 1 hour at a temperature of 180 ° C. in a nitrogen atmosphere, whereby the TFT 10c can be formed.
Although the ES layer 32 and the active layer 18 are formed together at one time, the present invention is not limited to this. The ES layer 32 and the active layer 18 may be formed by forming and etching a resist pattern using a photolithography method, respectively.

In this embodiment, even if the ES layer 32 has the same shape as the active layer 18, the ES layer 32 has a composition close to that of the active layer 18, and the ES layer 32 functions as an active layer and operates as a TFT.
Further, by making the ES layer 32 the same shape as the active layer 18, the ES layer 32 and the active layer 18 can be formed using a resist pattern formed with the same mask. As a result, the number of masks necessary for forming the resist pattern can be reduced, the cost can be reduced, and the manufacturing process can be simplified. Thereby, production efficiency can also be improved.

In addition, in the present embodiment, similar to the third embodiment, the same effects as those of the TFT 10 of the first embodiment and the manufacturing method thereof can be obtained. For this reason, the TFT 10c exhibits a good TFT operation without the threshold value shifting to minus. In addition, the TFT 10c which exhibits good TFT characteristics and high reliability can be uniformly formed in the surface.
Furthermore, the ES layer 32 can be easily formed as compared with the prior art, and processing can be facilitated.
Also in the manufacturing process of the TFT 10c, the formation of the resist film, the formation of the resist pattern, the formation of various films, and the formation of the protective layer 22 are all performed at a temperature of 200 ° C. or less. Thus, since each process is performed at a temperature of 200 ° C. or lower, a substrate 12 having low heat resistance such as PET or PEN can be used. Thereby, a flexible TFT can be obtained.

  The present invention is basically as described above. As described above, the thin film field effect transistor and the manufacturing method thereof according to the present invention have been described in detail. However, the present invention is not limited to the above embodiment, and various improvements or modifications can be made without departing from the gist of the present invention. Of course it is also good.

Examples of the thin film field effect transistor of the present invention will be specifically described below.
In this example, TFTs shown in the following Example 1, Example 2, and Comparative Examples 1 to 3 were prepared, and the TFTs of Examples 1, Example 2, and Comparative Examples 1 to 3 were evaluated. did. In addition, TFT10 of the structure shown in FIG. 1 was used for TFT of Example 1, Example 2, and Comparative Examples 1-3.

The TFTs of Example 1, Example 2, and Comparative Examples 1 to 3 were basically manufactured by the manufacturing method shown in FIGS. 4 (a) to 4 (c).
In each of the TFTs of Example 1, Example 2, Comparative Example 1, and Comparative Example 2, for the gate electrode 14, a molybdenum film having a thickness of 40 nm is formed by DC sputtering, and a photolithography method is used for this molybdenum film. A resist pattern was formed by etching using a mixed acid aqueous solution (liquid temperature 35 ° C.) containing 73% by mass of phosphoric acid, 7% by mass of acetic acid, 3% by mass of nitric acid, and the balance being water.

Next, a 200 nm thick SiO ₂ film to be the gate insulating film 16 is formed by RF sputtering. Next, a first IGZO film having a composition to be described later to be the active layer 18 is formed on the surface of the SiO ₂ film to a thickness of 30 nm by using a DC sputtering method. On the surface of the first IGZO film, a second IGZO film of each composition to be described later to be the ES layer 30 is formed to a thickness of 30 nm using a DC sputtering method. Then, a resist pattern is formed on the second IGZO film by using a photolithography method. Then, the second IGZO film and the first IGZO film were etched using 5% oxalic acid water.

  The active layer 18 includes a first IGZO having a Zn concentration (Zn / In + Ga + Zn) of 26.9%, a Ga concentration (Ga / In + Ga + Zn) of 34.6%, and an In concentration (In / In + Ga + Zn) of 38.5%. A membrane was used. Note that the concentration analysis of the first IGZO film was performed by XRF analysis as described above.

For the ES layer 30, after forming the active layer 18, a resist pattern is formed on the second IGZO film using a photolithography method. Then, only the second IGZO film was etched using 5% oxalic acid water.
For the gate insulating film 16, a resist pattern is formed on the SiO ₂ film / first IGZO film / second IGZO film using a photolithography method, and the SiO ₂ film is etched using buffered hydrofluoric acid. Formed.

  For the source electrode 20a and the drain electrode 20b, a molybdenum film is formed to a thickness of 100 nm under a pressure of 0.37 Pa using a DC sputtering method. A resist pattern is formed on the molybdenum film using a photolithography method. Then, a molybdenum film is formed by etching using a mixed acid aqueous solution (liquid temperature 25 ° C.) containing 73% by mass of phosphoric acid, 7% by mass of acetic acid and 3% by mass of nitric acid as an etchant and the balance being water. did.

  As for the protective layer 22, a photosensitive acrylic resin (PC405G (manufactured by JSR Corporation)) is applied so as to cover the active layer 18, the source electrode 20a, and the drain electrode 20b, and an acrylic resin film is used by photolithography. The pattern was formed. The curing conditions for the acrylic resin during pattern formation are a temperature of 180 ° C. and 30 minutes. Thereafter, post-annealing was performed for 1 hour at a temperature of 180 ° C. in a nitrogen atmosphere to form the TFT 10.

In Example 1, the ES layer has a Zn concentration (Zn / In + Ga + Zn) of 14.6%, a Ga concentration (Ga / In + Ga + Zn) of 41.6%, and an In concentration (In / In + Ga + Zn) of 43.8%. A second IGZO film was used. Note that the concentration analysis of the second IGZO film was performed by XRF analysis as described above.
In Example 1, the etching rate with the above-described etching liquid (molybdic acid aqueous solution of 73% by mass of phosphoric acid, 7% by mass of acetic acid and 3% by mass of nitric acid (liquid temperature 25 ° C.)) with molybdenum constituting the source electrode and the drain electrode. The ratio (IGZO: Mo) is 1: 13.8. Example 1 corresponds to the symbol A shown in FIG.

In Example 2, the ES layer has a Zn concentration (Zn / In + Ga + Zn) of 19.2%, a Ga concentration (Ga / In + Ga + Zn) of 38.8%, and an In concentration (In / In + Ga + Zn) of 42.0%. A second IGZO film was used.
In Example 2, the etching rate with the above-described etching liquid (molybdic acid aqueous solution (liquid temperature 25 ° C.) of 73% by mass of phosphoric acid, 7% by mass of acetic acid and 3% by mass of nitric acid) with molybdenum constituting the source electrode and the drain electrode. The ratio (IGZO: Mo) is 1: 10.6. Example 2 corresponds to the symbol B shown in FIG.

In Comparative Example 1, a SiO ₂ film having a thickness of 20 nm is used as the ES layer. Comparative Example 1 is the same as Example 1 except that the configuration and formation method of the ES layer are different. In Comparative Example 1, the ES layer was formed as follows.
In Comparative Example 1, after forming the first IGZO film, the active layer 18 was patterned. Thereafter, an SiO ₂ film having a thickness of 20 nm was formed on the surface 16a of the gate insulating film 16 by using an RF sputtering method so as to cover the active layer 18. Next, a resist pattern is formed on the SiO ₂ film was formed ES layer by etching the SiO ₂ film using a buffered hydrofluoric acid.

In Comparative Example 2, the ES layer has a Zn concentration (Zn / In + Ga + Zn) of 34.7%, a Ga concentration (Ga / In + Ga + Zn) of 30.3%, and an In concentration (In / In + Ga + Zn) of 35.0%. A second IGZO film was used.
In Comparative Example 2, the etching rate with molybdenum constituting the source electrode and the drain electrode by the above-described etching solution (mixed acid aqueous solution of phosphoric acid 73 mass%, acetic acid 7 mass% and nitric acid 3 mass% (liquid temperature 25 ° C.)). The ratio (IGZO: Mo) is 1: 3.1. Comparative example 2 corresponds to the symbol C shown in FIG.

In Comparative Example 3, the ES layer has a Zn concentration (Zn / In + Ga + Zn) of 25.1%, a Ga concentration (Ga / In + Ga + Zn) of 36.5%, and an In concentration (In / In + Ga + Zn) of 35%. IGZO film was used.
In Comparative Example 3, the etching rate with molybdenum constituting the source electrode and the drain electrode by the above-described etching solution (mixed acid aqueous solution of phosphoric acid 73 mass%, acetic acid 7 mass% and nitric acid 3 mass% (liquid temperature 25 ° C.)) The ratio (IGZO: Mo) is 1: 9.0. Comparative Example 3 corresponds to the symbol D shown in FIG.

For the transistors of Example 1, Example 2, and Comparative Examples 1 to 3, the mobility was measured. As a result, Examples 1 and 2 were TFTs having a mobility of 10 cm ² / Vs or more and good uniformity in TFT characteristics.
On the other hand, in Comparative Example 1, the underlying active layer is also etched due to the etching at the time of forming the ES layer, the contact with the source electrode and the drain electrode becomes insufficient, the on-current is deteriorated, and the reliability test is performed. The results were inferior to those of Examples 1 and 2.
In Comparative Example 2, the ES layer did not function, the active layer disappeared by etching during formation of the source electrode and the drain electrode, the TFT could not be formed, and the TFT operation was not performed. In Comparative Example 3, the ES layer function was insufficient, and although the TFT operation was performed, the in-plane uniformity of TFT characteristics was poor.

In this example, TFTs shown in the following Example 3 and Comparative Example 4 were produced, and the TFTs of Examples 3 and Comparative Example 4 were evaluated. As the TFTs of Example 3 and Comparative Example 4, the TFT 10a having the configuration shown in FIG. 5 was used.
This embodiment is the same as the first embodiment except that the ES layer and the active layer have the same shape compared to the first embodiment, and therefore detailed description thereof is omitted.

  In Example 3, the ES layer and the active layer have the same shape. Example 3 is the same as Example 1 of the first example except that the ES layer and the active layer have the same shape.

  In Comparative Example 4, the ES layer and the active layer have the same shape. Comparative Example 4 is the same as Comparative Example 1 of the first example except that the ES layer and the active layer have the same shape.

For the TFTs of Example 3 and Comparative Example 4, the mobility was measured. As a result, Example 3 was a TFT having a mobility of 10 cm ² / Vs or higher and good uniformity in TFT characteristics. On the other hand, Comparative Example 4 did not show TFT operation.
In Example 3, since the ES layer and the active layer can be formed using the same mask, the number of masks can be reduced and the cost can be reduced.

10, 10a Thin film field effect transistor (TFT)
DESCRIPTION OF SYMBOLS 12 Substrate 14 Gate electrode 16 Gate insulating film 18 Active layer 20a Source electrode 20b Drain electrode 22 Protective layer 24 Insulating film 30, 32 Etching stopper layer (ES layer)

Claims (11)

At least a gate electrode, an insulating film, an active layer, an etching stopper layer, a source electrode, and a drain electrode are formed on the substrate, the etching stopper layer is formed on the active layer, and the source electrode is formed on the etching stopper layer And a thin film field effect transistor in which the drain electrode is formed,
The etching stopper layer is made of an amorphous oxide containing In, Ga, and Zn having a Zn concentration of less than 20% , an In concentration of 40% or more, and a Ga concentration of 37% or more ,
The thin film field effect transistor characterized in that the active layer is composed of an amorphous oxide semiconductor containing In, Ga and Zn, and the Zn concentration is higher than the Zn concentration of the etching stopper layer. The thin film field effect transistor according to claim 1 , wherein the source electrode and the drain electrode are made of molybdenum or a molybdenum alloy. 3. The thin film field effect transistor according to claim 1, wherein the thin film field effect transistor has a top contact type bottom gate structure. 3. The thin film field effect transistor according to claim 1, wherein the thin film field effect transistor has a top contact type top gate structure. The active layer and the thin film field effect transistor according to any one of claims 1 to 4, which is the same shape and the etching stopper layer. At least a gate electrode, an insulating film, an active layer, an etching stopper layer, a source electrode, and a drain electrode are formed on the substrate, the etching stopper layer is formed on the active layer, and the source electrode is formed on the etching stopper layer And a method of manufacturing a thin film field effect transistor in which the drain electrode is formed,
Using a mixed acid aqueous solution containing phosphoric acid, acetic acid, and nitric acid as an etchant, and forming the source electrode and the drain electrode,
The etching stopper layer is made of an amorphous oxide containing In, Ga, and Zn having a Zn concentration of less than 20% , an In concentration of 40% or more, and a Ga concentration of 37% or more ,
The active layer is composed of an amorphous oxide semiconductor containing In, Ga, and Zn, and the Zn concentration is higher than the Zn concentration of the etching stopper layer. . The method of manufacturing a thin film field effect transistor according to claim 6 , wherein the mixed acid aqueous solution contains 70 to 75% by mass of phosphoric acid, 5 to 10% by mass of acetic acid, and 1 to 5% by mass of nitric acid. Before the step of forming the source electrode and the drain electrode, the step of forming the gate electrode on the substrate, the step of forming the insulating film on the substrate so as to cover the gate electrode, and the insulation Forming the active layer on the film, and forming the etching stopper layer on the active layer,
The thin film field effect according to claim 6 or 7 , wherein in the step of forming the source electrode and the drain electrode, the source electrode and the drain electrode are formed on the substrate so as to cover a part of the etching stopper layer. Type transistor manufacturing method. The thin film electric field according to claim 8 , further comprising a step of forming a protective layer on the substrate so as to cover the etching stopper layer, the source electrode, and the drain electrode after the step of forming the source electrode and the drain electrode. Method for producing effect transistor. Before the step of forming the source electrode and the drain electrode, the step of forming the active layer on the substrate, and the step of forming the etching stopper layer on the active layer,
In the step of forming the source electrode and the drain electrode, the source electrode and the drain electrode are formed on the substrate so as to cover a part of the etching stopper layer,
Further, after the step of forming the source electrode and the drain electrode, the step of forming the insulating film on the substrate so as to cover the etching stopper layer, the source electrode and the drain electrode, and the step of forming the insulating film on the insulating film. A method of manufacturing a thin film field effect transistor according to claim 6 , further comprising a step of forming a gate electrode. The method for manufacturing a thin film field effect transistor according to any one of claims 6 to 10 , wherein the active layer and the etching stopper layer are formed in the same shape.

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