TW201405791A - 封裝結構及其製作方法 - Google Patents

封裝結構及其製作方法 Download PDF

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TW201405791A
TW201405791A TW102123769A TW102123769A TW201405791A TW 201405791 A TW201405791 A TW 201405791A TW 102123769 A TW102123769 A TW 102123769A TW 102123769 A TW102123769 A TW 102123769A TW 201405791 A TW201405791 A TW 201405791A
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photodiode
semiconductor substrate
wafer
lifted
image sensor
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TWI503963B (zh
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Meng-Hsun Wan
Yi-Shin Chu
Szu-Ying Chen
Pao-Tung Chen
Jen-Cheng Liu
Dun-Nian Yaung
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Taiwan Semiconductor Mfg
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Abstract

本發明提供一種封裝結構，包括：一影像感測器晶片，具有一提昇式光電二極體形成於內，以及一裝置晶片，其位於影像感測器晶片下方且接合至影像感測器晶片。裝置晶片具有一讀取電路，其電性耦接至提昇式光電二極體。本發明亦提供一種封裝結構之製作方法。

Description

封裝結構及其製作方法
本發明係有關於封裝結構及其製作方法，且特別是有關於一種影像感測器之封裝結構及其製作方法。
影像感測器，特別是背照式(Back Side Illumination，BSI)影像感測器，正日益風行並用於各種應用中。如同積體電路技術的趨勢，其朝向使影像感測器的特徵部件越來越小，以允許更低的成本及更大的封裝密度。當像素線寬縮小到次微米範圍時，光電二極體的面積受限且因而難以維持其性能，例如信噪比(Signal to Noise Ratio，SNR)、量子效率(Quantum Efficiency，QE)、靈敏度等等。
提昇式光電二極體可克服傳統結構及其製作方法的一些缺點，然而提昇式光電二極體需要特定製程參數，故其會受到特殊應用積體電路(Application Specific Integrated Circuit，ASIC)製程條件的限制。
本發明一實施例提供一種封裝結構，包括：一影像感測器晶片，具有一提昇式光電二極體形成於內；以及一裝置晶片，位於影像感測器晶片下方並接合至影像感測器晶片，裝置晶片具有一讀取電路，電性耦接至提昇式光電二極體。
本發明另一實施例提供一種封裝結構，包括：一 影像感測器晶片，包括：一第一半導體基板；一提昇式光電二極體，位於第一半導體基板上方；以及一第一內連接結構，電性耦接至提昇式光電二極體；以及一裝置晶片，位於影像感測器晶片下方且接合至影像感測器晶片，其中裝置晶片包括：一第二半導體基板；一讀取電路，位於第二半導體基板之一頂部表面，其中讀取電路電性耦接至提昇式光電二極體；以及一第二內連接結構，位於第一半導體基板上。
本發明又一實施例提供一種封裝結構之製作方法，包括：於一影像感測晶圓之一半導體基板上形成一提昇式光電二極體；以及接合影像感測晶圓及一裝置晶圓，其中裝置晶圓包括一讀取電路，其電性耦接至提昇式光電二極體。
54‧‧‧載板
56‧‧‧接著層
58‧‧‧氧化物層
60‧‧‧通孔電極
100‧‧‧影像感測晶圓
100’‧‧‧影像感測晶片
110‧‧‧像素單元
112‧‧‧儲存節點
114、214‧‧‧內連接結構
116‧‧‧浮接擴散區域
118‧‧‧轉換閘極電晶體
120‧‧‧半導體基板
120A‧‧‧半導體基板的前側表面
120B‧‧‧半導體基板的背側表面
121、221‧‧‧介電層
124‧‧‧隔離特徵(深溝槽隔離結構)
124A‧‧‧深溝槽結構之頂端
125、225‧‧‧虛線
142、242‧‧‧金屬焊墊
144‧‧‧像素電極
145‧‧‧箭頭
146‧‧‧光電轉換層
148‧‧‧透明頂部電極
149‧‧‧提昇式光電二極體
150‧‧‧彩色濾光片
152‧‧‧微透鏡
200‧‧‧裝置晶圓
200’‧‧‧裝置晶片
220‧‧‧基板
222‧‧‧讀取電路
223‧‧‧邏輯電路
226‧‧‧列選擇器
228‧‧‧源極隨耦器
230‧‧‧重置電晶體
第1圖為依據本發明實施例之第一結構實施例的剖面示意圖。
第2圖為依據本發明實施例之第一結構實施例的剖面示意圖。
第3a至3c圖為依據本發明實施例所繪示之製作第1圖實施例的中間步驟之剖面圖。
第4a至4c圖為依據本發明實施例所繪示之製作第2圖實施例的中間步驟之剖面圖。
本發明實施例的製造及使用詳述如下。然而，可理解的是，這些實施例中係提供實施於多種特定上下文之許多 可應用的發明概念，所討論之具體實施例係用以說明性，並非用以限制本發明之範圍。
依據本發明數個實施例，本發明提供一種封裝結構及其製作方法，包括一第一晶片，其包括了一提昇式光電二極體堆疊於一第二晶片上。本發明亦說明了形成封裝結構的中間步驟，並討論實施例的不同變化。在各種觀點及說明用之實施例中，相似的參考數字可用於表示相似的元件。
在具體說明特定實施例之前，首先一般性地討論所說明之實施例的各種型態。本發明實施例提供一堆疊裝置，包括具有一提昇式光電轉換層(此處，有時可視為一光電轉換層)之一感測晶圓，以及一裝置晶圓，以形成一提昇式光電二極體影像感測器。在一些實施例中，影像感測晶圓100及裝置晶圓200(第1圖)以面對面接合(face-to-face bonding)方式進行堆疊。在其它實施例中，影像感測晶圓100及裝置晶圓200(第2圖)以面對背接合(face-to-back bonding)方式進行堆疊。在一些實施例中，於像素之間形成隔離結構以改善串擾(cross-talk)隔離性能。本發明不同實施例可提供所得之影像感測器高的填充因子(fill factor)。避免相鄰像素之間的電子串擾為本發明一些實施例的有利特徵。本發明實施例更提供了各個晶圓靈活的製程調變。
回頭來看說明的實施例，第1圖繪示了一說明用之裝置實施例的剖面示意圖，其中影像感測晶圓100及裝置晶圓200被堆疊為一面對面接合的排列。二像素單元110繪示於影像感測晶圓100上，但亦可有更多像素單元110形成於影像感測晶 圓100上。本發明所屬技術領域中具有通常知識者可知影像感測器晶圓100的構件，包括繪示之像素單元110，為了簡明此處並無詳細描述。同樣地，裝置晶圓200的構件，藉此可接受並處理由像素單元110來的電子信號，亦繪示於此處但未詳細描述，如那些對於本發明非必需理解及/或對本發明所屬技術領域中具有通常知識者為顯而易見者的詳細描述。
第2圖繪示了堆疊之影像感測晶圓100及裝置晶圓200，其中晶圓100及200被配置為一面對背接合之配置。需注意的是用於面對背接合之配置的影像感測晶圓100的不同配置，特別是儲存節點112及內連接結構114的位置。
第3a至3c圖示意性地繪示了製作一封裝結構的中間步驟，例如第1圖中所繪示的封裝結構。第3a圖繪示了製作中間步驟的一結構，在第3a圖所示的步驟中，形成影像感測晶圓100，其包括複數相同之影像感測晶片100'於其中。儲存節點112及內連接結構114形成於感測晶圓100上，且影像感測晶圓100以一面對面配置接合至裝置晶圓200(適當的主動及被動裝置及內連接已預先形成於其中)。儲存節點112以佈植區域形成。在一些實施例中，儲存節點112連接至轉換閘極電晶體118，其被配置以電性耦接及中斷同一像素單元110中的儲存節點112與對應之浮接(floating)擴散區域116。在另一實施例中，轉換閘極電晶體118形成於裝置晶圓200中而非形成於影像感測晶圓100上。在此說明之實施例中，內連接結構114繪示為包括單層內連接。可理解的是，複數層內連接結構114可形成於複數介電層121中，在一些實施例中其可包括低介電常數介 電層。
影像感測晶圓100亦包括半導體基板120，其可為一矽基板，或可以其他半導體材料形成，例如矽化鍺、碳化矽、Ⅲ-V族化合物半導體材料等等。在本發明說明中，基板120包括內連接結構114的一側，可視為基板120的前側(亦可視為影像感測晶圓100的前側)且其相反側被視為背側。因此，在第3a圖中，影像感測晶圓100的前側朝下。
為了簡明目的，二像素單元110繪示於影像感測晶圓100中，本發明範圍顯然可包括更多像素單元110。像素單元110藉由隔離特徵124分離，例如深溝槽隔離(Deep Trench Isolation，DTI)結構，其由一介電材料形成或包括該材料，如氧化物(例如氧化矽)及/或氮化物(例如氮化矽)。深溝槽隔離結構124可由基板120的背側表面延伸進基板120中。此外，在一些實施例中，深溝槽隔離結構124可穿透基板120，且由基板120的前側表面120A(朝下之表面)延伸至背側表面120B。在第3a圖之結構的俯視圖中，深溝槽隔離結構124可相互連接以形成連續柵格，像素單元110包括柵格開口中的部份、以及柵格開口之外並垂直對齊於柵格開口的部份。換句話說，深溝槽隔離結構124包括複數環，每個環包圍各個像素單位110的一部分。
第3a圖亦繪示了裝置晶片200的剖面圖，其包括複數相同裝置晶片200'於其中。裝置晶圓200包括基板220以及形成於基板220前側表面上之邏輯電路223。在一些實施例中，基板220為一矽基板。或者，基板220可由其它半導體材料形成， 例如矽化鍺、碳化矽、Ⅲ-V族化合物半導體材料等等。依據本發明一些實施例，邏輯電路223包括讀取電路222。每個讀取電路222包括複數電晶體，例如列選擇器226、源極隨耦器228、及重置電晶體230。列選擇器226、源極隨耦器228、及重置電晶體230可形成像素單元110的一部分，每個像素單元110包括列選擇器226之其中一者、源極隨耦器228之其中一者、及重置電晶體230之其中一者。因此，每個像素單元110可延伸進裝置晶圓200以包括讀取電路222之其中一者。
邏輯電路222亦可包括一個或多個影像信號處理(Image Signal Processing，ISP)電路，例如類比數位轉換器(Analog-to-Digital Converters，ADC)、相關性雙重取樣(Correlated Double Sampling，CDS)電路、列解碼器等等，其亦可視為讀取電路的一部分。內連接結構214形成於電路223上並電性耦接至邏輯電路223。內連接結構214包括複數介電層221中之複數金屬層，其中金屬線及通孔電極設置於介電層221中。在一些實施例中，介電層221包括低介電常數介電層。低介電常數介電層可包括低於約3.0之低介電常數值。介電層221可更包括以具有大於3.9之介電常數的非低介電常數介電材料所形成之鈍化保護層。在一些實施例中，鈍化保護層包括氧化矽層、氮化矽層、未摻雜矽玻璃(Un-doped Silicate Glass，USG)層等等。
金屬焊墊142及242分別形成於晶圓100及200的表面上，其中金屬焊墊142及242之頂部表面實質上與頂部介電層121及221之頂部表面分別切齊。金屬焊墊142及242亦可包括 銅、鋁、且可能包括其它金屬。金屬焊墊142接合至對應之金屬焊墊242，使晶圓100及200中的裝置彼此電性耦接。在一些實施例中，接合的結果，每個像素單元110包括晶圓100中的一部分及晶圓200中的一部分，其彼此電性耦接以形成可產生電子信號相應於光子刺激之一整合性功能像素單元，並儲存及輸出與讀取及重置命令之電子信號相應的電子信號。
如第3a圖所示，在晶圓100與200接合之後薄化影像感測晶圓100之背側(以箭頭145標示)。所得之半導體基板120可具有小於約10微米或小於約5微米之厚度。影像感測晶圓100可藉由例如機械研磨/拋光、化學機械研磨、蝕刻等等薄化。厚度為考慮技術節點及所需性質後的人為結果，其可藉由例行實驗來調整。
如第3b圖所示，基板120之背側部分被進一步薄化以露出各個像素單元110中的各個儲存節點112。此薄化可藉由選擇性蝕刻基板120而實施，且不蝕刻深溝槽結構124。其結果，基板120之背側表面120B低於深溝槽結構124之頂端124A。形成像素電極144以電性耦接各個儲存節點112。在一些實施例中，像素電極144亦可視為底部電極144。
雖然其它導電材料亦包括於本發明範圍之內，底部電極144之可用材料的例子包括鋁、氮化鈦、鉻等等。底部電極144可使用例如化學氣相沉積法(Chemical Vapor Deposition，CVD)、物理氣相沉積法(Physical Vapor Deposition，PVD)、電漿輔助化學氣相沉積法(Plasma Enhanced Chemical Vapor Deposition，PECVD)、有機金屬化學氣相沉 積法(Metal Organic Chemical Vapor Deposition，MOCVD)、濺鍍法等技術沈積。在說明之實施例中，所形成的底部電極144的厚度約0.3微米至約0.8微米之間。底部電極144可與其下方對應之儲存節點112接觸以建立電性耦接。
光電轉換層146形成於底部電極144上且電性耦接(亦可接觸)底部電極144，如第3c圖所示。透明頂部電極148形成於光電轉換層146上且與光電轉換層146電性耦接。光電轉換層146可包括非晶矽、量子點層、有機材料等等，此處作為例示而非用以限制本發明之範例。同樣地，頂部電極148可包括銦錫氧化物(Indium Tin Oxide，ITO)，但本發明所屬技術領域中具有通常知識者可知，藉由本發明揭露內容及例行實驗亦可使用其它適當替代品。光電轉換層146可藉由深溝槽結構124彼此分離。頂部電極148可為一連續膜層，其底部表面與光電轉換層146及深溝槽結構124之頂部表面接觸。每個底部電極144、光電轉換層146及其上方對應之頂部電極148部份形成提昇式光電二極體149，其不同於形成於半導體基板中之傳統光電二極體。
回頭參照第1圖，依據一些例示性的實施例，額外構件例如彩色濾光片150、微透鏡152等等，進一步形成於影像感測晶圓100的背側上。所得之堆疊晶圓100及200隨後被切割為封裝結構，其中每個封裝結構包括影像感測晶圓100之一晶片100'及裝置晶圓200之一晶片200'。
第4a至4c圖繪示了製作一封裝結構的中間步驟，例如第2圖所繪示之面對背結構。除非另有說明，在這些實施例 之構件的材料及形成方法實質上與其它構件相同，其由與第1圖及第3a至3c圖所示之實施例中相似的代號標示。關於第2圖及第4a至4c圖所繪示之構件的形成製程、材料、及說明書的細節可因而在第1圖及第3a至3c圖所繪示之實施例的討論中找到。
如上所述，用於一面對背配置之影像感測晶圓100不同於適用於一面對面配置之影像感測晶圓100。例如，如第4a圖所繪示，光電二極體149(包括透明頂部電極148、光電轉換層146、及底部電極144)形成於基板120及內連接結構114上。儲存節點112及對應之光電二極體149彼此藉由一個或多個居中的導電內連接結構114電性耦接，如圖所示。這些實施例之隔離結構124'可具有與光電轉換層146頂部表面切齊之頂部表面及與底部電極144底部表面切齊之底部表面。
影像感測晶圓100在第4a圖所繪示之製造步驟中為實質完整，其中彩色濾光片150及/或微透鏡152已形成為鄰接於光電二極體149。影像感測晶片100安裝於載板54上，例如一玻璃基板。此可藉由使用接著層56以接著載板54至影像感測晶圓100而完成。可用石英、矽、或其它材料以代替玻璃。在將影像感測晶圓100安裝至載板54之後，進行影像感測晶圓100的背側薄化(如箭頭145所示)，例如，使用與第3a圖所繪示之相似製程。
注意在這些實施例中，在晶圓薄化製程中並不需露出儲存節點112。部分原因是因為儲存節點112是藉由儲存節點的頂部電極進行電性接觸，即遠離晶圓100之背側表面的表 面。影像感測晶圓100薄化至所需厚度之後，氧化物層58形成於背側上，如第4b圖所示。在一些實施例中，氧化物層58包括氧化矽，其可使用例如物理氣相沉積法形成。通孔電極60(有時可視為穿孔電極(through vias)60，有時亦可視為基板通孔電極或矽通孔電極(through-silicon vias，TSV)60)亦可形成為由影像感測晶圓100之背側表面延伸至內連接結構114。以這種方式可製作出各種電性耦接。雖然第4b圖僅繪示一通孔電極60，亦可形成數個通孔電極(及數個電性耦接)。此外，每個像素單元110可包括一個或多個通孔電極。繪示的虛線125用以代表通孔電極60與晶圓100中的裝置之間可能的電性耦接。
第4c圖繪示了將影像感測晶圓100背側表面接合至一裝置晶圓的前側。亦繪示了虛線225以代表通孔電極60與邏輯電路223之間的電性耦接。裝置晶圓200可實質上與例如第3a圖所繪示者相同。然而在第4c圖之實施例中，所要的是裝置晶圓200在其前側(具有內連接結構214的一側)具有適當接合表面，以確保與影像感測晶圓100有充足的接著性及接合性。此表面可為處理過之氧化物表面、高度拋光之矽表面、或其它任何可提供氧化物層與影像感測晶圓100之「背側」充足接合性之表面。應注意在接合過程中需對齊影像感測晶圓100與裝置晶圓200，以確保彼此對齊之晶圓100及200形成接觸，而形成晶圓100及200上之裝置之間良好的電性接觸。隨後可移除載板54及接著層56，並實施單粒化(singulation)以將接合之晶圓100及200切割為複數封裝結構，每個包括一來自於晶圓100的晶片100'及一來自於晶圓200的晶片200’，而得到依據例示性 實施例繪示於第2圖的結構。
所說明之實施例提供了影像感測晶圓製程的有利特徵，其可最佳化影像感測晶圓的製程以形成像素單元。此外，可最佳化製程以形成支援電路，例如裝置晶圓中的讀取電路。這是有利的，因為影像感測晶圓與裝置晶圓具有不同製程需求。因此，藉由分離這些製程，影像感測晶圓與裝置晶圓的製程不會彼此影響。此外，藉由形成提昇式光電二極體，可最大化光電二極體的填充因子，因為其不受各晶圓中的金屬佈線或任何電晶體影響。
依據一些實施例，本發明提供一種封裝結構，包括：一影像感測器晶片，具有一提昇式光電二極體形成於內；以及一裝置晶片，位於影像感測器晶片下方並接合至影像感測器晶片，該裝置晶片具有一讀取電路，電性耦接至提昇式光電二極體。
依據其它實施例，本發明提供一種封裝結構，包括：一影像感測器晶片，包括：一第一半導體基板；一提昇式光電二極體，位於第一半導體基板上方；以及一第一內連接結構，電性耦接至提昇式光電二極體；以及一裝置晶片，位於影像感測器晶片下方且接合至影像感測器晶片，其中裝置晶片包括：一第二半導體基板；一讀取電路，位於第二半導體基板之一頂部表面，其中讀取電路電性耦接至提昇式光電二極體；以及一第二內連接結構，位於第一半導體基板上。
依據另外一些實施例，本發明提供一種封裝結構之製作方法，包括：於一影像感測晶圓之一半導體基板上形成 一提昇式光電二極體；以及接合影像感測晶圓及一裝置晶圓，其中裝置晶圓包括一讀取電路，其電性耦接至提昇式光電二極體。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。舉例來說，任何所屬技術領域中具有通常知識者可輕易理解此處所述的許多特徵、功能、製程及材料可在本發明的範圍內作更動。再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。
100‧‧‧影像感測晶圓
100’‧‧‧影像感測晶片
110‧‧‧像素單元
112‧‧‧儲存節點
114、214‧‧‧內連接結構
116‧‧‧浮接擴散區域
118‧‧‧轉換閘極電晶體
120‧‧‧半導體基板
121、221‧‧‧介電層
124‧‧‧隔離特徵(深溝槽隔離結構)
142、242‧‧‧金屬焊墊
144‧‧‧像素電極
146‧‧‧光電轉換層
148‧‧‧透明頂部電極
150‧‧‧彩色濾光片
152‧‧‧微透鏡
200‧‧‧裝置晶圓
200’‧‧‧裝置晶片
220‧‧‧基板
222‧‧‧讀取電路
223‧‧‧邏輯電路
226‧‧‧列選擇器
228‧‧‧源極隨耦器
230‧‧‧重置電晶體

Claims (10)

  1. 一種封裝結構，包括：一影像感測器晶片，具有一提昇式光電二極體形成於內；以及一裝置晶片，位於該影像感測器晶片下方並接合至該影像感測器晶片，該裝置晶片具有一讀取電路，電性耦接至該提昇式光電二極體。
  2. 如申請專利範圍第1項所述之封裝結構，其中該影像感測器晶片包括：一半導體基板，位於該提昇式光電二極體下方；以及一第一內連接結構，位於該半導體基板下方且藉由該半導體基板中的特徵部件電性耦接至該提昇式光電二極體，該影像感測器晶片更包括位於該半導體基板中的一儲存節點，其中該儲存節點內耦接該提昇式光電二極體與該第一內連接結構。
  3. 如申請專利範圍第1項所述之封裝結構，其中該影像感測器晶片包括：一半導體基板；以及一通孔電極，由該半導體基板之一頂部表面延伸至一底部表面，其中該通孔電極電性耦接耦接該讀取電路與該提昇式光電二極體；以及一內連接結構，位於該半導體基板上，其中該提昇式光電二極體係位於該內連接結構上。
  4. 如申請專利範圍第1項所述之封裝結構，更包括一深溝槽隔離，其形成一隔離環包圍該提昇式光電二極體之一底部電 極及一光電轉換層，其中該隔離環延伸通過該影像感測器晶片之一半導體基板。
  5. 一種封裝結構，包括：一影像感測器晶片，包括：一第一半導體基板；一提昇式光電二極體，位於該第一半導體基板上方；一第一內連接結構，電性耦接至該提昇式光電二極體；以及一裝置晶片，位於該影像感測器晶片下方且接合至該影像感測器晶片，其中該裝置晶片包括：一第二半導體基板；一讀取電路，位於該第二半導體基板之一頂部表面，其中該讀取電路電性耦接至該提昇式光電二極體；以及一第二內連接結構，位於該第一半導體基板上。
  6. 如申請專利範圍第5項所述之封裝結構，其中該第一內連接結構位於該第一半導體基板下方，其中該讀取電路藉由該第一及該第二內連接結構電性耦接至該提昇式光電二極體且該封裝結構更包括一儲存節點，位於該第一半導體基板中且耦接於該提昇式光電二極體與該第一內連接結構之間。
  7. 一種封裝結構之製作方法，包括：於一影像感測晶圓之一半導體基板上形成一提昇式光電二極體；以及接合該影像感測晶圓及一裝置晶圓，其中該裝置晶圓包括 一讀取電路，其電性耦接至該提昇式光電二極體。
  8. 如申請專利範圍第7項所述之封裝結構之製作方法，更包括：薄化該影像感測晶圓之一背側，以露出該半導體基板中的一儲存節點；實施形成該提昇式光電二極體之步驟，包括：於該儲存節點上形成一底部電極且接觸該儲存節點；於該底部電極上形成一光電轉換層；以及於該光電轉換層上形成一頂部電極，其中在該接合步驟之後，該裝置晶圓及該提昇式光電二極體位於該半導體基板的相反側。
  9. 如申請專利範圍第7項所述之封裝結構之製作方法，其中形成該提昇式光電二極體之步驟包括：使該半導體基板之一背側表面凹陷，直到該背側表面低於一深溝槽隔離區域之頂部以形成一凹部，其中該深溝槽隔離區域穿透該半導體基板以形成一環；於該半導體基板之該凹部中及該背側表面上形成一底部電極，其中該底部電極被該環所包圍；以及於該底部電極上形成一光電轉換層。
  10. 如申請專利範圍第9項所述之封裝結構之製作方法，其中形成該提昇式光電二極體之步驟更包括於該深溝槽隔離區域及該光電轉換層上形成一透明頂部電極且接觸該深溝槽隔離區域及該光電轉換層。
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US9123617B2 (en) 2015-09-01
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US20190013345A1 (en) 2019-01-10
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US9530811B2 (en) 2016-12-27
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US20150064832A1 (en) 2015-03-05
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