TWI741251B - 用於形成封裝的光電感測器陣列的方法和光電積體電路 - Google Patents

用於形成封裝的光電感測器陣列的方法和光電積體電路 Download PDF

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TWI741251B
TWI741251B TW108103353A TW108103353A TWI741251B TW I741251 B TWI741251 B TW I741251B TW 108103353 A TW108103353 A TW 108103353A TW 108103353 A TW108103353 A TW 108103353A TW I741251 B TWI741251 B TW I741251B
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metal
integrated circuit
dielectric
layer
metal layer
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TW108103353A
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TW201943049A (zh
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錢胤
繆佳君
張明
幸志 戴
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美商豪威科技股份有限公司
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Abstract

封裝的光電感測器IC通過以下製備：製造具有複數個接合焊盤的積體電路(IC)；從IC背面形成穿過半導體的通孔以暴露第一金屬層；在通孔中沉積導電金屬栓塞；沉積互連金屬；在互連金屬和穿過其的開口上沉積焊料遮罩介電質；在互連金屬上在焊料遮罩介電質中的開口處形成焊料凸點；和將焊料凸點接合至封裝的導體。光電感測器IC具有基板；由形成在基板的第一表面上的介電層隔開的複數個金屬層，在基板中形成有電晶體；由複數個金屬層的至少第一金屬層形成的複數個接合焊盤結構；穿過半導體基板的第二表面上的介電質形成的具有金屬栓塞的通孔，介電質上的形成連接圖形的互連金屬，和聯接至各個導電栓塞和焊料凸點的互連層的圖形。

Description

用於形成封裝的光電感測器陣列的方法和光電積體電路
本申請涉及一種用於形成封裝的光電感測器陣列的方法和光電感測器積體電路。
互連層(interconnect layer)是必要的，以使積體電路接合佈局能夠適用於匹配某些積體電路封裝的接合位置，特別是當使用焊球接合時。該互連層將積體電路的接合焊盤(bondpad，或稱為壓焊點)連接到焊料球接合的接合點。這些焊料球接合又將積體電路連接到積體電路封裝的連接點。
積體電路的接合焊盤的頂側金屬通常為厚的金屬，其能抵抗機械應力引起的機械損壞，機械應力包括由溫度改變、接合製程或振動引起的應力。積體電路的其它部分，包括接合焊盤下方的金屬層，通常具有對機械損壞具有較小抵抗力的較薄金屬層。
大多數積體電路是透過連接至封裝的晶片頂部或晶片底部發揮功能。晶片頂部是在其中進行擴散並且在積體電路製造過程中在其上沉積互連層的一側。然而，光電感測器積體電路需要頂側或底側的特定光電感測器入光側能暴露于經由封裝的視窗或透鏡進入的光。以不同於上述所設計的暴露於光的入光側的任何其它方式所定向的這些電路會損害光電感測器的功能。
在圖1所示的現有技術中，採用這樣的互連層封裝的光電感測器陣列(photosensor array)積體電路的接合焊盤區域100具有通孔102，穿過半導體基板104刻蝕通孔102以暴露薄的第一金屬層106。該通孔102襯有絕緣體 108，其中所刻蝕的每個通孔102的中心是空的以暴露薄的第一金屬層106。互連層金屬110沉積在通孔內，接觸接合焊盤的接觸部分112中的薄的第一金屬層106。接合焊盤還具有位於薄的第一金屬層106的部分112上方的複數個通孔115和厚的接合金屬部分117；接合焊盤區域100還可以具有中間金屬層119。
根據圖1採用互連層封裝的積體電路在機械應力下會失效，因為薄的第一金屬層106缺乏足夠的機械強度，特別是在通孔102的刻蝕導致接合焊盤區域的接觸部分112中的第一金屬層106變薄的情況下，或是在第一金屬層106的金屬部分地擴散或溶入到互連層金屬的情況下。這種變薄和後來的機械應力通常在薄的第一金屬層106的部分112的邊緣處或附近導致開裂，例如裂縫121。裂縫可能由於金屬遷移而傳播並且可能最終阻礙電流流動。
在實施方案中，封裝的光電感測器陣列通過以下製備：製造具有複數個接合焊盤的第一積體電路(IC)；穿過半導體形成通孔以暴露接合焊盤的第一金屬層；在通孔內沉積導電金屬栓塞；沉積互連金屬；在互連金屬和穿過其的開口上沉積焊料遮罩介電質；在互連金屬上在焊料遮罩介電質中的開口處形成焊料凸點；和將焊料凸點接合至封裝的導體。
在另一個實施方案中，光電感測器IC具有第一基板；由形成在基板的第一表面上的介電層隔開的複數個金屬層；由複數個金屬層的至少第一金屬層形成的複數個接合焊盤結構；穿過半導體基板形成的到達第一金屬層的通孔，且該通孔中填充有金屬栓塞。IC具有形成在半導體基板的第二表面上的介電質，互連金屬形成連接圖形(shape)，互連層的圖形聯接至各個導電栓塞和聯接至焊料凸點。
100:接合焊盤區域
102:通孔
104:半導體基板
106:薄的第一金屬層
108:絕緣體
112:接合焊盤的接觸部分
112:薄的第一金屬層的部分
115:通孔
117:厚的接合金屬部分
119:中間金屬層
121:裂縫
200:改善接合焊盤結構
204:半導體基板
205:層間介電質
202:通孔
206:第一金屬層
208:介電質
210:互連金屬
220:導電金屬栓塞
212:薄的第一金屬層的部分
217:接合金屬部分
219:中間金屬層
218:介電質
225:鈍化-介電層
340:第二積體電路
342:第一積體電路
302:上層金屬
306:絕緣鈍化層
304:金屬栓塞
312:鈍化層
314:金屬互連
310:栓塞
316:通孔
322、324:介電質
318:中間互連
320:金屬
326:半導體
328:開口
330:接合焊盤金屬
332:通孔
400:方法
402:積體電路晶圓
404:晶圓的背面遮罩並刻蝕
406:晶圓的背面和通孔的壁用介電質進行加襯
408:遮罩及暴露第一金屬
410:進行沉積鎳或鎳-金合金的化學鍍金屬沉積
412:沉積遮罩和刻蝕互連金屬
414:沉積焊料遮罩介電層
416以暴露互連層:在介電質中形成開口
418:沉積焊料凸點
420:接合封裝中的第一積體電路和接合第二積體電路至第一積體電路以形成封裝的堆疊光電感測器
圖1 是前側互連光電感測器陣列的用於焊料凸點接合的現有技術互連層接觸的截面圖。
圖2 是前側互連光電感測器陣列的用於焊料凸點接合的改善的互連層接觸的實施方案的截面圖。
圖3 是堆疊光電感測器陣列的實施方案的截面圖，顯示出用於陣列焊料凸點接合改善的互連層接觸。
圖4 是用於製造光電感測器陣列焊料凸點接合改善的互連層接觸方法的實施方案的流程圖。
如圖2所顯示的用於光電感測器陣列積體電路的改善接合焊盤結構200中，透過半導體基板204和層間介電質205刻蝕通孔202以暴露薄的第一金屬層206，該薄的第一金屬層206通常具有銅和矽摻雜的鋁。電晶體，如光電感測器陣列的解碼器的電晶體，形成在半導體基板中。層間介電質205可以為二氧化矽或低電容介電質材料。晶圓背部和通孔202的側壁襯有絕緣體208，其可以為二氧化矽或另一介電質材料；從通孔的中心區域移除該襯料以重新暴露第一金屬層206。
在沉積互連金屬210之前，將導電金屬栓塞220沉積在暴露的第一金屬206上，在特定的實施方案中，導電金屬栓塞220係由第一金屬206催化沉積的化學鍍鎳所形成，並在互連金屬210和薄的第一金屬層206之間形成屏障。那麼，互連金屬210接觸形成於接合焊盤區域中薄的第一金屬層206的部分212中的導電金屬栓塞220。互連金屬210由鈦-銅-鎳合金形成。在可選的實施方案中，導電金屬栓塞220由鎳-金合金形成。
改善接合焊盤區域200還具有位於薄的第一金屬層206的部分212上方的複數個通孔215和厚的接合金屬部分217；接合焊盤區域還可以具有一個、兩個或更複數個中間金屬層219以及相關聯的金屬間介電質218和通孔。在一些實施方案中，鈍化-介電層225中可以存在開口以暴露接合金屬部分217。
根據圖2的在互連金屬210上的圖形和第一金屬206之間使用導電栓塞220封裝的積體電路在機械應力下比圖1的裝置更不易失效。能提高對機械應力的抵抗力是由於：(a)薄的第一金屬層206與互連金屬210化學隔離因而不能溶入互連金屬210中，並且(b)薄的第一金屬層206被導電金屬栓塞220的導電金屬機械性強化。這種化學隔離和機械性強化導致比常規製程更少開裂。
堆疊光電感測器陣列受益于具有形成在第二半導體晶圓中的光電二極體、解碼器-驅動器、像素選擇電路和讀出放大器、類比數位轉換器、和形成在第一半導體晶圓中的其它支援電路。在堆疊光電感測器陣列中，第一和第二半導體晶圓堆疊，並且各個晶圓的晶粒(die)之間的互連形成在像素或小組像素的等級。如果將光電二極體集成到第一半導體晶圓中，則堆疊光電感測器陣列允許形成與支援電路不同的材料的光電二極體，因而允許對波長不同於可能波長的光的敏感性，並允許光電二極體比當光電二極體與支援電路混合時具有更密集的封裝。
具有背照式光電二極體的堆疊光電感測器陣列300(圖3)具有第一積體電路，其具有下層互連金屬、通孔和介電層以及導電栓塞，類似於圖2所顯示的那些改善接合焊盤結構200。與圖2的那些層對應的層在圖3中具有相同的附圖標記。第二積體電路340包括光電二極體陣列。堆疊陣列的第一積體電路342具有上層金屬302，該上層金屬302在形成從第一積體電路至第二積體電路的連接的某些地方具有從上層金屬302延伸穿過第一積體電路絕緣鈍化層306的金屬栓塞304。第二積體電路具有從金屬栓塞304延伸穿過其最上面的鈍化層312到達其最上面的金屬互連314的相應栓塞310。通孔，如通孔316，穿過介電質322、324將金屬互連314連接至中間互連318的一個或複數個層並連接至最底部的金屬320。在一些實施方案中，可以在第二積體電路的半導體326中刻蝕開口328並在開口328中填充用於測試的接合焊盤金屬330，接合焊盤金屬330通過更多的通孔332連接至最底部的金屬320。
圖2或圖3中所示的裝置是根據圖4所示的方法400製備的。在 製造積體電路晶圓402之後，將晶圓的背面遮罩並刻蝕404以打開通孔202並暴露第一金屬層206。晶圓的背面和通孔的壁用介電質208進行加襯406，在一個實施方案中，介電質為聚醯亞胺，以及在一個實施方案中，利用遮罩步驟和刻蝕步驟再次暴露第一金屬層206。在一個實施方案中，進行沉積鎳或鎳-金合金的化學鍍金屬沉積410以在通孔202底部構建導電金屬栓塞220。進行表面預處理，然後進行沉積遮罩和刻蝕412以將互連金屬210圖案化為互連圖形，通常在互連層上針對各個通孔具有不同的圖形。接下來，在互連層上沉積焊料遮罩介電層245(414)；在特定的實施方案中，焊料遮罩介電質為聚醯亞胺，焊料遮罩介電質245可以是或可以不是保形塗層，並且在特定區域敞開以沉積焊料凸點。
在一個實施方案中，通過等離子體增強化學氣相沉積(PECVD)進行金屬栓塞220在通孔202底部的化學鍍沉積410以沉積5至10納米厚的催化納米層，其增強了開口中的化學氣相沉積或濕式無電化學鍍金屬沉積(wet electroless chemical metal deposition)。
在一些實施方案中，採用濕法化學鍍沉積來沉積互連金屬210(412)，互連金屬210可以為鈦-銅-鎳合金或另一銅合金。
然後在介電質中形成開口416以暴露互連層上將要形成焊料凸點的圖形，沉積焊料凸點418。在特定的實施方案中，焊料凸點為37%的鉛、63%的錫。在可選的實施方案中，使用無鉛低熔點合金代替鉛-錫合金用於焊料凸點248，在特定的實施方案中，這些無鉛焊料凸點由低熔點錫-銀-銅合金形成。當凸點形成後，可以通過習知回流技術將積體電路342置於並焊接至積體電路封裝(對應於圖4的步驟420，接合封裝中的第一積體電路和接合第二積體電路至第一積體電路以形成堆疊光電感測器420)。將任何第二積體電路，如積體電路340，也接合至積體電路342。
互連層的各個圖形將一個或複數個焊料凸點248聯接至一個或複數個金屬栓塞220，並由此聯接至第一金屬層。
在堆疊光電感測器實施方案的替代實施方案中，採用常規技術形成第二積體電路340。然後將其倒置並接合至第一積體電路342以形成複合晶圓。然後將複合晶圓切割並封裝，而不是在將第一積體電路安裝到封裝之後接合第一積體電路342和第二積體電路340。
然後將形成的凸點狀複合晶粒(composite die)接合至IC封裝以形成封裝的堆疊光電感測器(對應於圖4的步驟420，接合封裝中的第一積體電路和接合第二積體電路至第一積體電路以形成堆疊光電感測器420)。
特徵的組合
本文公開的特徵可以以多種方式組合。我們預期的特定組合包括：
標記為A的用於形成封裝的光電感測器陣列的方法包括製造具有複數個接合焊盤的第一積體電路；形成穿過第一積體電路的半導體的通孔以暴露複數個接合焊盤的第一金屬層；在通孔中沉積導電金屬栓塞；沉積和遮罩與導電金屬栓塞聯接的互連金屬；在互連金屬上沉積焊料遮罩介電質和形成穿過焊料遮罩介電質的開口；在焊料遮罩介電質中的開口處形成附接至互連金屬的焊料凸點；和將焊料凸點接合至積體電路封裝的導體。
包括標記為A的方法的標記為AA的方法還包括在使用介電質對通孔加襯後暴露通孔中的第一金屬層。
包括標記為A或AA的方法的標記為AB的方法還包括將第二積體電路接合至第一積體電路的頂表面，第二積體電路包括光電二極體陣列。
包括標記為A或AA的方法的標記為AC的方法，其中第一積體電路包括光電二極體陣列。
標記為B的光電感測器積體電路包括：包括電晶體的第一半導體基板；由形成在第一半導體基板的第一表面上的介電層隔開的複數個金屬層；由複數個金屬層的第一金屬層上的至少一種圖形形成的複數個結構；穿過第一半導體基板形成的複數個通孔，其中導電栓塞形成在複數個通孔中，導電栓塞聯接至第一金屬層上的圖形；沉積在第一半導體基板的第二表面上的介電質上的互連金屬，互連金屬形成連接圖形，每個連接圖形聯接至導電栓塞；和沉積在連接圖形上的複數個焊料凸點。
包括標記為B的光電感測器積體電路的標記為BA的光電感測器積體電路，其中導電栓塞由包括鎳的合金形成。
包括標記為B或BA的光電感測器積體電路的標記為BB的光電感測器積體電路，其中互連金屬包括銅。
包括標記為B、BA或BB的光電感測器積體電路的標記為BC的光電感測器積體電路，其中第一半導體基板包括光電二極體陣列。
包括標記為B、BA或BB的光電感測器積體電路的標記為BD的光電感測器積體電路還包括：第二半導體基板，該第二半導體基板包括光電二極體陣列；形成在第二半導體基板的第一表面上的複數個金屬層和複數個介電層；和其中形成在第二半導體基板的第一表面上的複數個金屬層和複數個介電層的頂表面接合至形成在第一半導體基板上的複數個金屬層和複數個介電層的頂表面。
包括標記為B、BA、BB、BC或BD的光電感測器積體電路的標記為BE的光電感測器積體電路，其中第一半導體基板包括矽。
在不脫離本發明的範圍的情況下，可以對上述方法和系統進行改變。因此應該注意，包含在以上描述中或附圖中所示的內容應該被解釋為說明性的而不是限制性的。在此，除非另外指出，否則形容詞“示例性”意味著用作示 例、實例或例證。所附的權利要求旨在涵蓋在此描述的所有通用特徵和具體特徵，以及由於語言的原因，本方法和系統的範圍的所有陳述可落在其間。
200:改善接合焊盤結構
204:半導體基板
205:層間介電質
202:通孔
206:第一金屬層
208:介電質
210:互連金屬
220:導電金屬栓塞
212:薄的第一金屬層的部分
217:接合金屬部分
219:中間金屬層
218:介電質
225:鈍化-介電層

Claims (10)

  1. 一種用於形成封裝的光電感測器陣列的方法，包括：製造具有複數個接合焊盤的一個第一積體電路；穿過該第一積體電路的半導體基板與一層間介電質形成通孔以暴露所述複數個接合焊盤的第一金屬層；利用沉積導電金屬栓塞以填充每一個通孔的一部分並且與在該通孔中該複數個接合焊盤的該第一金屬層接觸來機械性地強化該複數個鍵合焊盤的該第一金屬層；在沉積該導電金屬栓塞於該通孔中之後，沉積和遮罩一個與每一個通孔的壁共形並且與每一個通孔中相應該導電金屬栓塞接觸的互連金屬，該互連金屬延伸超過該每一個通孔；在該互連金屬上沉積焊料遮罩介電質和穿過該焊料遮罩介電質形成開口；在該焊料遮罩介電質中的該開口處形成位於該互連金屬之上的焊料凸點；將該焊料凸點接合至一個積體電路封裝的導體；其中唯一與該導電金屬栓塞接觸的金屬是該互連金屬和該第一金屬層；及其中該導電金屬栓塞化學隔離該互連金屬與該第一金屬層。
  2. 根據請求項1所述的方法，其中上述第一積體電路包括一光電二極體陣列。
  3. 一種光電感測器積體電路，包括：第一半導體基板，該第一半導體基板包括電晶體；由形成在該第一半導體基板的第一表面上的介電層隔開的複數個金屬層，該複數個金屬層包含第一金屬層；由該複數個金屬層的該第一金屬層上的至少一種圖形所形成的複數個結構； 穿過該第一半導體基板並且穿過該半導體基板與該第一金屬層上的一圖形之間的一層間介電質形成的複數個通孔；該複數個通孔中的每一個通孔在該第一金屬層上暴露至少一部分該圖形但不穿透該第一金屬層；複數個單層導電金屬栓塞，每個該導電金屬栓塞形成在該複數個通孔的相應通孔中，每個該導電栓塞沉積於該第一金屬層上的一圖形上；形成在該第一半導體基板的第二表面和該通孔的側壁上的介電質，沉積在該介電質上的互連金屬，該互連金屬形成連接圖形，每個連接圖形與該複數個通孔中相關聯的通孔的壁共形並且透過該複數個單層導電金屬栓塞中的一導電金屬栓塞電聯接至複數個金屬層的第一金屬層上以至少一種圖形形成的複數個結構中的一個結構；及透過該介電質中的開口沉積在該互連金屬的連接圖形上的複數個焊料凸點；其中每一個導電栓塞是沉積於該連接圖形的一個連接圖形以及在該第一金屬層上以至少一個圖形形成的該複數個結構中的一個結構之間，該導電栓塞電聯接該連接圖形至該結構，由該第一金屬層上的至少一圖形所形成的該複數個結構的一部分、該導電栓塞、以及該連接圖形的一部分形成一多層三明治結構；其中上述導電栓塞與該連接圖形和該第一金屬層分開；及與該導電金屬栓塞接觸的唯一金屬是該互連金屬和該第一金屬層；其中該導電金屬栓塞用以從該第一金屬層化學隔離該互連金屬。
  4. 根據請求項3所述的光電感測器積體電路，其中上述互連金屬包括銅。
  5. 根據請求項4所述的光電感測器積體電路，其中上述第一半導體基板包括光電二極體陣列。
  6. 根據請求4所述的光電感測器積體電路，更包含：一個第二半導體基板，該第二半導體基板包括光電二極體陣列； 形成在該第二半導體基板的第一表面上的複數個金屬層和複數個介電層；及其中形成在該第二半導體基板的該第一表面上的該複數個金屬層和該複數個介電層的頂表面接合至形成在該第一半導體基板上的該複數個金屬層和該複數個介電層的頂表面。
  7. 根據請求項6所述的光電感測器積體電路，其中上述第一半導體基板包括矽。
  8. 根據請求項1所述的方法，更包含在利用一介電質對上述通孔進行襯里之後，以及透過沉積上述導電金屬栓塞來增強上述複數個鍵合焊盤的該第一金屬層之前，將該第一金屬層暴露在該通孔中，其中該導電金屬栓塞與該互連金屬的沉積是分開的。
  9. 根據請求項3所述的光電感測器積體電路，其中上述第一金屬層以及上述連接圖形利用該導電金屬栓塞進行化學隔離。
  10. 根據請求項1所述的方法，其中沉積該導電栓塞是利用無電鍍沉積的方式進行。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112838073A (zh) * 2019-11-25 2021-05-25 格科微电子（上海）有限公司 用于晶圆键合的电学测试结构及其形成方法
TWI746067B (zh) * 2019-12-03 2021-11-11 義明科技股份有限公司 光感測器及其感測方法
US11682654B2 (en) * 2019-12-17 2023-06-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure having a sensor device and method of manufacturing the same
US11393746B2 (en) * 2020-03-19 2022-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Reinforcing package using reinforcing patches
CN113539946B (zh) * 2020-04-16 2023-07-07 长鑫存储技术有限公司 半导体结构及其形成方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110122303A1 (en) * 2006-12-29 2011-05-26 Manabu Bonkohara Solid-state imaging device, method of fabricating the same, and camera module
TW201130100A (en) * 2009-10-05 2011-09-01 Ibm Semiconductor device having a copper plug
TW201405791A (zh) * 2012-07-31 2014-02-01 Taiwan Semiconductor Mfg 封裝結構及其製作方法
TW201630135A (zh) * 2015-02-05 2016-08-16 Xintex Inc 晶片封裝體及其製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6537851B1 (en) * 2000-10-13 2003-03-25 Bridge Semiconductor Corporation Method of connecting a bumped compliant conductive trace to a semiconductor chip
JP4092890B2 (ja) * 2001-05-31 2008-05-28 株式会社日立製作所 マルチチップモジュール
US7038288B2 (en) * 2002-09-25 2006-05-02 Microsemi Corporation Front side illuminated photodiode with backside bump
JP5268618B2 (ja) * 2008-12-18 2013-08-21 株式会社東芝 半導体装置
US20130083229A1 (en) * 2011-09-30 2013-04-04 Omnivision Technologies, Inc. Emi shield for camera module
US9287310B2 (en) * 2012-04-18 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for glass removal in CMOS image sensors
TWI550794B (zh) * 2014-12-17 2016-09-21 精材科技股份有限公司 晶片封裝體及其製造方法
US9704827B2 (en) * 2015-06-25 2017-07-11 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bond pad structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110122303A1 (en) * 2006-12-29 2011-05-26 Manabu Bonkohara Solid-state imaging device, method of fabricating the same, and camera module
TW201130100A (en) * 2009-10-05 2011-09-01 Ibm Semiconductor device having a copper plug
TW201405791A (zh) * 2012-07-31 2014-02-01 Taiwan Semiconductor Mfg 封裝結構及其製作方法
TW201630135A (zh) * 2015-02-05 2016-08-16 Xintex Inc 晶片封裝體及其製造方法

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