TWI595535B - 積體電路結構與其形成方法 - Google Patents

積體電路結構與其形成方法 Download PDF

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Publication number
TWI595535B
TWI595535B TW105125395A TW105125395A TWI595535B TW I595535 B TWI595535 B TW I595535B TW 105125395 A TW105125395 A TW 105125395A TW 105125395 A TW105125395 A TW 105125395A TW I595535 B TWI595535 B TW I595535B
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Taiwan
Prior art keywords
pad
dielectric layer
forming
metal
bonding pad
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TW105125395A
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TW201724192A (zh
Inventor
余振華
邱文智
陳明發
陳怡秀
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台灣積體電路製造股份有限公司
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Description

積體電路結構與其形成方法
本揭露關於積體電路結構，更特別關於其接合結構與其形成方法。
在製作積體電路時，裝置如電晶體係形成於晶圓中的半導體基板表面。接著形成內連線結構於積體電路裝置上。金屬墊形成於內連線結構上並電性耦接至內連線結構。形成於金屬墊上的鈍化層與第一高分子層中的開口，可露出金屬墊。
接著形成鈍化層後內連線(PPI)以連接至金屬墊的上表面，再形成第二高分子層於PPI上。凸塊下金屬化物(UBM)延伸至第二高分子層中的開口中，且UBM電性連接至PPI。接著將焊球置於UBM上，並進行再流動製程。
本揭露一實施例提供之積體電路結構的形成方法，包括：形成第一導電結構與第二導電結構；形成金屬墊於第一導電結構上以電性連接至第一導電結構；形成鈍化層覆蓋金屬墊的邊緣部份，且鈍化層中的開口露出金屬墊之上表面的中心部份；沉積第一介電層以覆蓋金屬墊與鈍化層；形成第一接合墊於第一介電層上，其中第一接合墊電性耦接至第二導電 結構；以及沉積第二介電層，其中第二介電層圍繞第一接合墊。
本揭露一實施例提供之積體電路結構的形成方法，包括形成第一金屬結構與第二金屬結構；形成金屬墊於第一金屬結構上以接觸第一金屬結構；形成鈍化層覆蓋金屬墊之邊緣部份，且鈍化層中的開口露出金屬墊之上表面的中心部份；形成第一介電層覆蓋金屬墊的上表面與鈍化層，形成通孔穿過第一介電層與鈍化層，以接觸第二金屬結構；同時形成第一接合墊與第二接合墊，且第二接合墊位於通孔上並接觸通孔；形成第二介電層以埋置第一接合墊與第二接合墊；以及平坦化第二介電層之上表面，使第二介電層之上表面、第一接合墊之上表面、與第二接合墊之上表面齊平。
本揭露一實施例提供之積體電路結構，包括第一金屬結構與第二金屬結構彼此相鄰；墊位於第一金屬結構上以接觸第一金屬結構；鈍化層覆蓋墊的邊緣部份，且鈍化層中的開口露出墊之上表面的中心部份；第一介電層覆蓋墊的上表面與鈍化層；通孔穿過第一介電層與鈍化層以接觸第二金屬結構；以及第二介電層圍繞第一接合墊與第二接合墊，且第二接合墊位於通孔上以接觸通孔。
2、72‧‧‧封裝構件
4‧‧‧晶片
20‧‧‧半導體基板
22‧‧‧積體電路裝置
24‧‧‧ILD
28‧‧‧接點插塞
30‧‧‧內連線結構
32、32A、50、76‧‧‧介電層
34‧‧‧金屬線
36‧‧‧通孔
34A、34B‧‧‧金屬結構
35‧‧‧導電部份
40、46‧‧‧鈍化層
42、74A、74B‧‧‧金屬墊
45‧‧‧電性連接
48‧‧‧探針
52‧‧‧介電蝕刻停止層
54‧‧‧通孔
56、60、80、86‧‧‧導電的阻障層
58‧‧‧金屬
61、64、83‧‧‧光阻
62‧‧‧晶種層
66A、66B‧‧‧接合墊
68‧‧‧介電的阻障層
70‧‧‧介電材料
78、84‧‧‧開口
82、88‧‧‧導電材料
202、204、206、208、210、212、214、216‧‧‧步驟
第1至11圖係某些實施例中，形成接合結構之製程其中間階段的剖視圖。
第12至21圖係某些實施例中，形成接合結構之製程其中間階段的剖視圖。
第22至24圖係某些實施例中，形成接合結構之製程其中間階段的剖視圖。
第25圖係某些實施例中，形成接合結構之製程的流程圖。
下述內容提供的不同實施例或實例可實施本揭露的不同結構。特定構件與排列的實施例係用以簡化本揭露而非侷限本揭露。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。此外，本揭露之多種例子中可重複標號，但這些重複僅用以簡化與清楚說明，不代表不同實施例及/或設置之間具有相同標號之單元之間具有相同的對應關係。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。
多種實施例將提供接合結構與其形成方法，並說明接合結構之形成方法的中間階段。某些實施例的變化亦討論如下。在多種圖式與例示的實施例中，將以相同標號標示相同單元。
第1至11圖係某些實施例中，形成接合結構的方法其中間階段的剖視圖。第1至11圖中的步驟亦圖示於第25圖中製程的流程。
第1圖係封裝構件2的剖視圖。在本揭露某些實施例中，封裝構件2係包含主動裝置如電晶體及/或二極體，且可能包含被動裝置如電容、電感、電阻、或類似物之裝置晶圓。封裝構件2如裝置晶圓可包含多個晶片4於其中，如圖示的晶片4。在本揭露另一實施例中，封裝構件2為中介晶圓，其可包含或不包含主動裝置及/或被動裝置。在本揭露又一實施例中，封裝構件2為封裝基板條，其包含無核封裝基板或具有核心的封裝基板。在下述討論中，封裝構件2為裝置晶圓，但本揭露的封裝構件亦可作為中介晶圓、封裝基板、封裝、或類似物。
在本揭露某些實施例中，封裝構件2如晶圓包含半導體基板20，與形成於半導體基板20之上表面的結構。半導體基板20之組成可為結晶矽、結晶鍺、矽鍺、及/或III-V族化合物如GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP、或類似物。半導體基板20亦可為基體矽基板或絕緣物上矽(SOI)基板。淺溝槽隔離(STI)區(未圖示)可形成於半導體基板20中，以隔離半導體基板20中的主動區。雖然未圖示，但穿孔可延伸於半導體基板20中，其中穿孔用以電性耦接封裝構件2如晶圓之相反兩側上的結構。
在本揭露某些實施例中，封裝構件2如晶圓包含積體電路裝置22，其形成於半導體基板20之上表面上。舉例來說，積體電路裝置22包含互補式金氧半(CMOS)電晶體、電阻、電容、二極體、或類似物。積體電路裝置22之細節在此不贅述。在其他實施例中，封裝構件2如晶圓係用以形成中介物，其中基板可為半導體基板或介電基板。
ILD(層間介電物)24係形成於半導體基板20上，並填入積體電路裝置22中的電晶體(未圖示)其閘極堆疊之間的空間。在某些實施例中，ILD 24之組成為磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、掺雜硼之磷矽酸鹽玻璃(BPSG)、掺雜氟之矽酸鹽玻璃(FSG)、四乙氧矽烷(TEOS)、或類似物。ILD 24之形成方法可為旋轉塗佈、可流動化學氣相沉積(FCVD)、或類似方法。在本揭露某些實施例中，ILD 24之形成方法可為沉積法如電漿增強式化學氣相沉積(PECVD)、低壓化學氣相沉積(LPCVD)、或類似方法。
接點插塞28形成於ILD 24中，使積體電路裝置22電性連接至上方的金屬線與通孔。在本揭露某些實施例中，接點插塞28之組成為導電材料如鎢、鋁、銅、鈦、鉭、氮化鈦、氮化鉭、上述之合金、及/或上述之多層結構。接點插塞28之形成方法包含形成接點開口於ILD 24中、將導電材料填入接點開口中、並進行平坦化製程(如化學機械拋光，CMP)使接點插塞28之上表面與ILD 24之上表面齊平。
內連線結構30位於ILD 24與接點插塞28上。內連線結構30包含金屬線34與通孔36，其形成於介電層32中。形成於同一層的金屬線，之後將統稱為金屬層。在本揭露某些實施例中，內連線結構30包含以通孔36內連線之多個金屬層。金屬線34與通孔36之組成可為銅或銅合金，亦可為其他金屬。在本揭露某些實施例中，介電層32之組成為低介電常數之介電材料。舉例來說，低介電常數之介電材料的介電常數(k值)可小於約3.0，或小於於2.5。
介電層32又可稱作金屬間介電層(IMD)。在本揭露某些實施例中，至少較下層之介電層32的組成為介電常數(k值)小於約3.0、約2.5、或更低的低介電常數之介電材料。介電層32可為Black Diamond(Applied Material之註冊商標)、含碳之低介電常數的介電材料、氫倍半矽氧烷(SQ)、甲基倍半矽氧烷(MSQ)、或類似物。介電層32亦可具有低介電常數值，其可小於約3.0、2.5、或2.0。在本揭露某些實施例中，介電層32的形成方法包括沉積含沉孔劑的介電材料，接著進行硬化製程以逐出成孔劑，使介電層32具有孔洞。
金屬線34與通孔36係形成於介電層32中，其形成方法包含單鑲嵌製程或雙鑲嵌製程。在單鑲嵌製程中，先形成溝槽於介電層32中的一者，之後將導電材料填入溝槽中。接著以平坦化製程如CMP，移除高出IMD層之上表面的多餘導電材料，並保留金屬線於溝槽中。在雙鑲嵌製程中，形成溝槽與通孔的開口於IMD層中，且通孔的開口位於溝槽下並連接至溝槽。接著將導電材料填入溝槽與通孔的開口，以分別形成導電線路與通孔。導電材料可包含擴散阻障層，與擴散阻障層上的含銅金屬化材料。擴散阻障層可包含鈦、氮化鈦、鉭、氮化鉭、或類似物。
金屬線34包含頂部的金屬結構34A與34B，比如頂部金屬化層中的金屬線或墊，其位於介電層32之一者中(比如介電層32A)。可以理解的是，雖然圖式中的金屬結構34A與34B為隔有介電層32A之分隔結構，但其亦可為連續的金屬結構之一部份，比如虛線框標示的導電部份35(使金屬結構34A與34B 內連線)。在某些實施例中，介電層32A之組成與介電層32中較小者之低介電常數之介電材料相同。在其他實施例中，介電層32A之組成為非低介電常數之介電材料，其可包含氮化矽、未掺雜之矽酸鹽玻璃(USG)、氧化矽、或類似物。介電層32A亦可具有多層結構，比如包含兩層的USG層與兩者之間的氮化矽層。頂部的金屬結構34A與34B之組成亦可為銅或銅合金，且可具有雙鑲嵌或單鑲嵌結構。
金屬墊42形成於金屬結構34A上並與其接觸。在某些實施例中，金屬墊42經由導電結構如金屬線34與通孔36電性耦接至積體電路裝置22，其中電性連接45係以虛線標示。金屬墊42可為鋁墊或鋁銅墊，但亦可為其他金屬材料。在本揭露某些實施例中，金屬墊之鋁含量大於約95%。
鈍化層40(有時稱作鈍化層-1)可形成於內連線結構30上。鈍化層46(有時稱作鈍化層-2)係形成於鈍化層40上。某些部份的鈍化層46可覆蓋金屬墊42的邊緣部份，而鈍化層46中的開口露出金屬墊42之上表面的中心部份。每一鈍化層40與46可為單層或複合層，且組成可為非孔洞材料。在本揭露某些實施例中，鈍化層40與46之一或兩者為複合層，其包含氧化矽層與其上的氮化矽層。
第1圖係探測步驟，其可為晶圓接受度測試或電路測試。上述步驟如第25圖中的製程流程之步驟202所示。探測步驟可檢驗積體電路裝置22與個別的電性連接之功能。探測步驟可藉由探針48接觸金屬墊42。舉例來說，探針48可為具有多個探針之探針卡的一部份，其連接至測試設備(未圖示)。金屬 墊42係設計為尺寸大到足以進行探測。此外，金屬墊42可為鋁墊，其軟於銅而比銅墊更適於上述探測製程。
如第2圖所示，沉積介電層50後可進行平坦化步驟如化學機械拋光(CMP)製程。上述步驟如第25圖中的製程流程之步驟204所示。介電層50之上表面高於金屬墊42之上表面，且可高於鈍化層46之頂端。
接著如第3圖所示，形成介電蝕刻停止層52，之後形成通孔54。上述步驟如第25圖中的製程流程之步驟206所示。介電蝕刻停止層52之組成可為氮化物如氮化矽。通孔54之形成方法包含蝕刻介電蝕刻停止層52與介電層50以形成通孔開口，接著將導電材料填入通孔開口以形成通孔54。在本揭露某些實施例中，將導電材料填入通孔開口之步驟包含毯覆性地沉積導電的阻障層56、形成晶種層如銅層、以及進行鍍製製程如電鍍或無電鍍製以鍍製金屬58如銅或銅合金。導電的阻障層56可包含鈦、氮化鈦、鉭、氮化鉭、或類似物。平坦化步驟如CMP可移除多餘的部份導電材料、晶種層、與鍍製的金屬58。
如第4圖所示，形成導電的阻障層60與晶種層62，其形成方法可為物理氣相沉積(PVD)。上述步驟如第25圖中的製程流程之步驟208所示。導電的阻障層60之組成可為鈦、氮化鈦、鉭、或氮化鉭。晶種層62可包含銅。接著如第5圖所示，形成並圖案化光阻64，以露出某些部份的晶種層62。在第6A圖所示之後續步驟中，進行鍍製製程以自晶種層62形成接合墊66A與66B。上述步驟如第25圖中的製程流程之步驟210所示。上述鍍製步驟包含電化學鍍製(ECP)、無電鍍製、或類似方法。
如第4圖所示，晶種層62具有水平部份而不具有垂直部份。如此一來，接合墊66A與66B向上成長，而不會橫向成長。這種成長方式的好處在於接合墊66A與66B(如銅晶粒)具有(111)的表面取向。實驗結果指出某些實施例中的接合墊樣品，有8936個銅晶粒具有(111)的表面取向，且2715個銅晶粒具有(200)的表面取向，即具有(111)的表面取向之銅晶粒數目為具有(200)的表面取向之銅晶粒數目的3.3倍。由於具有(111)的表面取向之銅晶粒比具有其他表面取向之銅晶粒更易擴散，因此後續步驟中的接合墊66A與66B易於形成金屬對金屬的直接接合。
接著移除光阻64以形成第7圖中的結構，露出光阻64原本覆蓋的部份晶種層62與導電的阻障層60。接著蝕刻移除露出的部份晶種層62與導電的阻障層60，形成第8圖所示之結構。上述蝕刻步驟在蝕刻導電的阻障層60後，將停止於介電蝕刻停止層52。在第8圖與下述內容中，直接位於接合墊66A與66B下方之部份晶種層62與導電的阻障層60，亦視作部份的接合墊66A與66B(未分開標示)。在某些實施例中，接合墊66A可直接覆蓋金屬墊42。
如第9圖所示，介電的阻障層68係沉積於接合墊66A與66B之上表面與側壁上，以及介電蝕刻停止層52上。介電的阻障層68之形成方法係順應性地沉積，比如原子層沉積(ALD)。介電的阻障層68之側壁部份亦完全圍繞每一接合墊66A與66B。在本揭露某些實施例中，介電的阻障層68之組成為碳氮化矽、氮化矽、或類似物。接著沉積介電材料70。上述 步驟如第25圖中的製程流程之步驟212所示。介電材料70係用於熔融接合(亦稱作氧化物對氧化物接合)。在某些實施例中，介電材料70之組成為含矽之介電材料如氧化矽或氮化矽。
如第10圖所示之後續步驟中，以平坦化步驟如CMP步驟移除介電材料70的頂部。上述步驟如第25圖中的製程流程之步驟214所示。此步驟亦移除高於接合墊66A與66B之上表面的部份介電材料70與介電的阻障層68，並露出接合墊66A與66B。接合墊66A與66B之上表面彼此共平面，並與介電材料70之上表面共平面。
第11圖係將封裝構件72接合至封裝構件2。上述步驟如第25圖中的製程流程之步驟216所示。在本揭露某些實施例中，封裝構件72為裝置晶粒、中介晶粒、封裝基板、或封裝。封裝構件72包含金屬墊74A與74B，各自以金屬對金屬的直接接合方式接合至接合墊66A與66B。封裝構件72亦包含介電層76，其表面與金屬墊74A與74B之表面共平面。介電層76亦可為含矽介電層如氧化矽層。介電層76熔融接合至介電材料70。綜上所述，接合結果為混合接合，其包含熔融接合與金屬對金屬接合。在某些實施例中，接合包含預接合封裝構件2與72，以及回火使接合墊66A與金屬墊74A中的金屬與接合墊66B與金屬墊74B中的金屬達成金屬間擴散。由於接合墊66A與66B具有(111)表面取向，而具有(111)表面取向的銅比具有其他表面取向的銅更易擴散，因此降低回火溫度與縮短回火時間仍可達到較強的接合。
在第11圖所示之結構中，接合墊66B具有電性功 能，且可電性耦接至積體電路裝置22。另一方面，接合墊66A不具有電性功能，因此為虛置的接合墊。虛置的接合墊66A位於較低接合墊密度的區域中，且具有降低圖案負載效應的功能。如此一來，可改善接合墊66A、接合墊66B、與介電材料70之上表面的共平面性質。此外，將虛置的接合墊66A接合至虛置的金屬墊74A，可改善封裝構件2與72之接合強度。在某些實施例中，接合墊66A為電性浮置。此外，介電的阻障層68完全圍繞接合墊66A，且接合墊66A之底部與所有其他的導電結構之間亦隔有介電蝕刻停止層52與介電層50。綜上所述，接合墊66A之側壁與底部可不接觸任何導電材料(如金屬)。
此外，金屬墊42係用於探測而非用於使金屬結構34A連接至任何上方的導電結構。金屬墊42之整體上表面可接觸介電材料，且無導電結構位於金屬墊42上並與金屬墊42之上表面接觸。此外，當晶片4操作時(開啟)，金屬墊42可具有電壓(比如接地電壓或非零電壓)，但不具有電流流經金屬墊42。在某些實施例中，比金屬墊42小的接合墊66A與66B係用於接合，因此其腳距亦小。因此本揭露實施例適於小腳距的輸入/輸出(I/O)應用。
第12至21圖與第22至24圖係本揭露某些實施例中，形成接合結構之製程的中間階段剖視圖。除非特別提及，否則這些實施例中構件的材料與形成方法，基本上與第1至11圖中實施例之相同標號標示的構件類似。第12至24圖中構件的製程步驟與材料等細節，可參考第1至11圖之實施例中的討論。
第12至21圖係某些實施例之製程的中間階段其剖 視圖，其中虛置金屬墊與電性金屬墊分別形成於不同步驟。這些實施例的起始步驟如第12圖所示，其與第1圖實質上相同。在後續步驟中，形成介電層50如第13圖所示，接著進行平坦化製程使介電層50之上表面齊平。
如第14圖所示，形成介電蝕刻停止層52與介電材料70。上述材料可與第11圖所示之實施例中所用之材料相同。接著如第15圖所示，施加並圖案化光阻61，再經圖案化之光阻蝕刻介電材料70以形成開口78。在本揭露某些實施例中，蝕刻停止於介電層50如第15圖所示，且穿過蝕刻停止層52。在其他實施例中，蝕刻停止於蝕刻停止層52之上表面，且至少未蝕刻穿過蝕刻停止層52。接著移除光阻61。
如第16圖所示，導電的阻障層80沉積延伸至開口78(見第15圖)中。部份導電的阻障層80接觸介電蝕刻停止層52或介電層50之上表面。在某些實施例中，導電的阻障層80之組成可為鈦、鉭、氮化鈦、或氮化鉭。接著沉積導電材料82如銅或銅合金。接著進行平坦化製程，移除導電的阻障層80與導電材料82之多餘部份，並保留接合墊66A於介電層70中，如第17圖所示。上述接合墊66A包含導電的阻障層80接觸導電材料82之側壁與底部與含銅之導電材料82。
如第18圖所示，施加並圖案化光阻83，且經由圖案化光阻蝕刻介電材料70、介電蝕刻停止層52、介電層50、鈍化層46、與鈍化層40，以形成開口84。上述蝕刻步驟停止於金屬結構34B。接著移除光阻83。
如第19圖所示，導電的阻障層86沉積延伸至開口 84(見第18圖)中。部份導電的阻障層86延伸於介電材料70之上表面上。在某些實施例中，導電的阻障層86之組成可為鈦、鉭、氮化鈦、或氮化鉭。接著沉積含銅之導電材料88。接著進行平坦化製程移除多餘部份的導電之阻障層86與導電材料88，保留接合墊66B於介電層70中如第20圖所示。如第21圖所示，接合封裝構件2與封裝構件72。
在第21圖所示之實施例中，接合墊66B其邊緣自介電材料70之上表面，筆直且實質上垂直的延伸至金屬結構34B。綜上所述，接合墊66B與金屬結構34B之間並無窄細通孔相連。在某些實施例中，介電層50之厚度介於2μm至3μm之間。由於介電層50較厚，若形成窄細通孔，則通孔之電阻將非常高。綜上所述，本揭露實施例可避免窄細通孔所造成的電阻增加等不利現象。
第22至24圖係某些實施例中，製程之中間階段的剖視圖。這些實施例與第12至21圖之實施例類似，除了填充間隙以形成接合墊66A與66B之步驟同時進行。起始的製程步驟與第12至15圖之製程步驟類似。接著如第22圖所示，形成並圖案化光阻83。光阻83填入開口78。接著以光阻83作為蝕刻遮罩，蝕刻介電層以形成開口84。在露出金屬結構34B後，移除光阻83。
接著如第23圖所示，形成導電的阻障層80與含銅的導電材料82，其形成方法可為沉積及/或鍍製。接著進行平坦化製程，移除多餘部份之導電的阻障層80與含銅的導電材料82，保留接合墊66A與66B如第24圖所示。接合墊66A與66B各 自包含導電的阻障層與含銅的導電材料，且導電的阻障層位於導電材料82之側壁上與底部下。第24圖亦顯示封裝構件2與封裝構件72之接合。
本揭露實施例具有某些優點。本揭露實施例可實施鰭狀間距的接合。本揭露某些實施例可達較佳的銅取向(111)，使後續的混合接合更容易，亦改善接合品質。此外，某些實施例可允許接合墊穿過介電層，而鋁墊形成其中，使最終結構之電阻降低。
在本揭露某些實施例中，方法包括：形成第一導電結構與第二導電結構；形成金屬墊於第一導電結構上以電性連接至第一導電結構；以及形成鈍化層覆蓋金屬墊的邊緣部份，且鈍化層中的開口露出金屬墊之上表面的中心部份。形成第一介電層以覆蓋金屬墊與鈍化層。形成第一接合墊於第一介電層上，且接合墊電性耦接至第二導電結構。沉積第二介電層圍繞接合墊。進行平坦化步驟使第二介電層之上表面與接合墊齊平。在平坦化步驟後，金屬墊之上表面的整體接觸介電材料。
在本揭露某些實施例中，方法包括：同時形成第一金屬結構與第二金屬結構；形成鋁墊於第一金屬結構上以接觸第一金屬結構；以及形成鈍化層覆蓋鋁墊之邊緣部份，且鈍化層中的開口露出鋁墊之上表面的中心部份。上述方法亦包含形成第一介電層覆蓋鋁墊的上表面與鈍化層，形成通孔穿過第一介電層與該鈍化層，以接觸第二金屬結構；同時形成第一接合墊與第二接合墊，且第二接合墊位於通孔上並接觸通孔；形成第二介電層以埋置第一接合墊與第二接合墊；以及平坦化第 二介電層之上表面，使第二介電層之上表面、第一接合墊之上表面、與第二接合墊之上表面齊平。
在本揭露某些實施例中，積體電路結構包括：第一金屬結構與第二金屬結構彼此相鄰；鋁墊位於第一金屬結構上以接觸第一金屬結構；鈍化層覆蓋鋁墊的邊緣部份，且鈍化層中的開口露出鋁墊之上表面的中心部份。第一介電層覆蓋鋁墊的上表面與鈍化層。通孔穿過第一介電層與鈍化層以接觸第二金屬結構。第一接合墊與第二接合墊彼此共平面，且第二接合墊位於通孔上以接觸通孔。第二介電層圍繞第一接合墊與第二接合墊，其中第二介電層之上表面、第一接合墊之上表面、與第二接合墊之上表面共平面。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本揭露。本技術領域中具有通常知識者應理解可採用本揭露作基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本揭露精神與範疇，並可在未脫離本揭露之精神與範疇的前提下進行改變、替換、或更動。
2、72‧‧‧封裝構件
4‧‧‧晶片
20‧‧‧半導體基板
22‧‧‧積體電路裝置
24‧‧‧ILD
28‧‧‧接點插塞
32、32A、50、76‧‧‧介電層
34‧‧‧金屬線
36‧‧‧通孔
34A、34B‧‧‧金屬結構
35‧‧‧導電部份
40、46‧‧‧鈍化層
42、74A、74B‧‧‧金屬墊
45‧‧‧電性連接
52‧‧‧介電蝕刻停止層
54‧‧‧通孔
66A、66B‧‧‧接合墊
70‧‧‧介電材料

Claims (10)

  1. 一種積體電路結構的形成方法，包括：形成一第一導電結構與一第二導電結構；形成一金屬墊於該第一導電結構上以電性連接至該第一導電結構；形成一鈍化層覆蓋該金屬墊的邊緣部份，且該鈍化層中的一開口露出該金屬墊之上表面的中心部份；沉積一第一介電層以覆蓋該金屬墊與該鈍化層；形成一第一接合墊於該第一介電層上，其中該第一接合墊電性耦接至該第二導電結構；以及沉積一第二介電層，其中該第二介電層圍繞該第一接合墊。
  2. 如申請專利範圍第1項所述之積體電路結構的形成方法，其中該第一接合墊與該第二介電層位於一第一封裝構件中，且上述方法更包括混合接合該第一接合墊與該第二介電層至一第二封裝構件。
  3. 如申請專利範圍第1項所述之積體電路結構的形成方法，更包括進行一平坦化製程於該第二介電層與該第一接合墊上，且在形成該第一接合墊之後，該金屬墊之上表面並未連接至多個導電結構。
  4. 如申請專利範圍第1項所述之積體電路結構的形成方法，其中該第一接合墊之形成方法為鍍製，且該第二介電層之形成方法包括：沉積一介電的阻障層以接觸該第一接合墊之上表面與側壁； 沉積一額外介電層於該介電的阻障層上；以及進行一平坦化步驟以移除高於該第一接合墊的多餘部份之該介電的阻障層與該額外介電層。
  5. 如申請專利範圍第1項所述之積體電路結構的形成方法，更包括形成一通孔於該第一介電層中，其中該通孔使該第二導電構物理性地連接至該第一接合墊。
  6. 如申請專利範圍第1項所述之積體電路結構的形成方法，其中形成該第一接合墊之步驟包括：蝕刻該第二介電層、該第一介電層、與該鈍化層以形成一第一通孔開口，且該第一通孔開口其實質上筆直的邊緣自該第二介電層之上表面延伸至該第二導電結構；以及填入該第一通孔開口以形成該第一接合墊，且該第一接合墊自該第二介電層之上表面延伸至該第二導電結構之上表面。
  7. 如申請專利範圍第6項所述之積體電路結構的形成方法，更包括：蝕刻該第二介電層以形成一第二通孔開口；以及填入該第二通孔開口以形成一第二接合墊，且該第二接合墊之整體實質上高於該第一介電層之上表面，其中填入該第一通孔開口之步驟與填入該第二通孔開口之步驟為不同的製程步驟。
  8. 如申請專利範圍第6項所述之積體電路結構的形成方法，更包括：蝕刻該第二介電層以形成一第二通孔開口；以及 填入該第二通孔開口以形成一第二接合墊，且該第二接合墊之整體實質上高於該第一介電層之上表面，且填入該第一通孔開口之步驟與填入該第二通孔開口之步驟同時進行。
  9. 一種積體電路結構的形成方法，包括：形成一第一金屬結構與一第二金屬結構；形成一金屬墊於該第一金屬結構上以接觸該第一金屬結構；形成一鈍化層覆蓋該金屬墊之邊緣部份，且該鈍化層中的一開口露出該金屬墊之上表面的中心部份；形成一第一介電層覆蓋該金屬墊的上表面與該鈍化層；形成一通孔穿過該第一介電層與該鈍化層，以接觸該第二金屬結構；同時形成一第一接合墊與一第二接合墊，且該第二接合墊位於該通孔上並接觸該通孔；形成一第二介電層以埋置該第一接合墊與該第二接合墊；以及平坦化該第二介電層之上表面，使該第二介電層之上表面、該第一接合墊之上表面、與該第二接合墊之上表面齊平。
  10. 一種積體電路結構，包括：一第一金屬結構與一第二金屬結構彼此相鄰；一墊位於該第一金屬結構上以接觸該第一金屬結構；一鈍化層覆蓋該墊的邊緣部份，且該鈍化層中的一開口露 出該墊之上表面的中心部份；一第一介電層覆蓋該墊的上表面與該鈍化層；一通孔穿過該第一介電層與該鈍化層以接觸該第二金屬結構；以及一第二介電層圍繞一第一接合墊與一第二接合墊，且該第二接合墊位於該通孔上以接觸該通孔。
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