TW201306207A - 半導體封裝件及其製法 - Google Patents
半導體封裝件及其製法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 72
- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 claims abstract description 22
- 239000010410 layer Substances 0.000 claims description 54
- 239000002335 surface treatment layer Substances 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 19
- 239000011241 protective layer Substances 0.000 claims description 16
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical group [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 13
- 239000010931 gold Substances 0.000 claims description 8
- 239000008393 encapsulating agent Substances 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 229910052763 palladium Inorganic materials 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 claims description 3
- 238000007772 electroless plating Methods 0.000 claims description 2
- 238000009713 electroplating Methods 0.000 claims 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims 1
- 229910052802 copper Inorganic materials 0.000 claims 1
- 239000010949 copper Substances 0.000 claims 1
- 230000001568 sexual effect Effects 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000000059 patterning Methods 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
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- 238000003466 welding Methods 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000003755 preservative agent Substances 0.000 description 1
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Abstract
一種半導體封裝件,係包括:具有相對之第一與第二表面之介電層、設於第一表面上之晶片、埋設於第一表面且電性連接晶片之至少二個電性接觸墊、設於第二表面上之複數植球墊、以及設於介電層中且兩端分別結合電性接觸墊與植球墊之導電柱,以藉導電柱之設計,使得植球墊之位置與電性接觸墊之位置無需相互配合,因而可依需求調整植球墊之植球面積,使佈線更彈性化。本發明復提供一種半導體封裝件之製法。
Description
本發明係有關一種半導體封裝件,尤指一種使佈線更彈性化之半導體封裝件及其製法。
隨著半導體技術的演進,半導體產品已開發出不同封裝產品型態,而為追求半導體封裝件之輕薄短小,因而發展出一種四方平面無引腳(Quad Flat No leads,QFN)之封裝技術,其特徵在於導腳不凸出該膠體表面。
如第1圖所示,係第7,795,071號美國專利揭示之QFN封裝件之線路結構,其係於具有貫穿之開口100之承載板10上形成覆蓋該開口100一側之絕緣層14,該絕緣層14具有外露於該開口100之置晶側14a與相對之植球側14b,於該置晶側14a上埋設複數電性接觸墊12及導電跡線11,且於該植球側14b中埋設複數植球墊15。其中,該導電跡線11位於各該電性接觸墊12之間,且該植球墊15與該電性接觸墊12係相接合於該絕緣層14中,又該電性接觸墊12用於電性連接晶片(圖未示),而該植球墊15係結合銲球(圖未示)以接置電路板(圖未示)。
惟,習知線路結構中,該植球墊15與該電性接觸墊12的位置相同(中心對齊),使得銲球佈設(solder ball layout)與電性接觸墊12之位置需相互配合,造成相互牽制,故使該植球墊15之植球面積A’受到限制(其寬度約230μm)而無法增加,因而降低銲球之結合力。
再者,各該植球墊15之間的植球間距b’約500μm,且該電性接觸墊12之位置需配合該植球墊15,故各該電性接觸墊12(徑長d’約290μm)之間距亦需配合各該植球墊15之植球間距b’,而無法增加各該電性接觸墊12之間距,導致該導電跡線11之數量受限(導電跡線11之線寬w’與線距t’均約40μm),如圖所示之最多兩條導電跡線11,因而難以提升佈線密度。
因此,如何克服習知技術於提升佈線密度上的瓶頸,實為一重要課題。
為克服習知技術之問題,本發明遂提出一種佈線彈性化之半導體封裝件及其製法。
本發明提供一種半導體封裝件,係包括:具有相對之第一與第二表面的介電層;置於該介電層之第一表面上的半導體晶片;埋設且外露於該介電層之第一表面,並電性連接該半導體晶片的至少二個電性接觸墊;設於該介電層之第二表面上的複數植球墊;以及設於該介電層中的複數導電柱,且各該導電柱具有相對之第一端與第二端,該第一端結合該電性接觸墊,而第二端結合該植球墊,以電性連接該植球墊與該電性接觸墊。
本發明復提供一種半導體封裝件之製法,係包括:於一基板上形成至少二個電性接觸墊;形成至少二個導電柱於該電性接觸墊上;形成介電層於該基板上,以包覆該導電柱與電性接觸墊,且該介電層外露該導電柱;形成複數植球墊於該介電層與該導電柱上,以電性連接該導電柱;形成絕緣保護層於該介電層上,且該絕緣保護層外露該植球墊;貫穿該基板以形成開口,俾令該開口外露該些電性接觸墊;以及置放半導體晶片於該開口中,使該半導體晶片電性連接該些電性接觸墊。
本發明之半導體封裝件及其製法中,係先於電性接觸墊上形成導電柱,再於導電柱上形成植球墊,使植球墊之佈設與電性接觸墊之位置無需相互配合,故該植球墊之位置及植球面積可任意調整,以增加銲球佈設之設計彈性。
再者,因各該電性接觸墊的間距不需配合各該植球墊的間距,故可依需求調整各該電性接觸墊之間距,以增加電性接觸墊佈設之設計彈性,使各該電性接觸墊之間可彈性化設計導電跡線之數量,進而可調整佈線密度。
另外,依前述之本發明之半導體封裝件及其製法,本發明復提供其更具體之技術,詳如後述。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“上”及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
第2A至2G圖係繪示本發明半導體封裝件2之製法之剖面示意圖。
如第2A圖所示,提供一基板20,且進行圖案化製程,以藉由光阻210外露部分基板20表面,以電鍍形成複數導電跡線21及至少二個電性接觸墊22於該基板20上,且該些導電跡線21係位於該至少二個電性接觸墊22之間。
如第2B圖所示,進行另一圖案化製程,以於每一電性接觸墊22上藉由另一光阻230而電鍍形成一導電柱23,且該導電柱23具有相對之第一端23a與第二端23b,該第一端23a結合該電性接觸墊22上。
如第2C圖所示,移除所有之光阻210,230,再形成具有相對之第一表面24a及第二表面24b之介電層24於該基板20上,以包覆該導電跡線21、電性接觸墊22與導電柱23。於本實施例中,該介電層24之第一表面24a結合該基板20,且該介電層24之第二表面24b外露該導電柱23之第二端23b。
如第2D圖所示,進行圖案化製程,以藉由光阻(圖未示)而電鍍形成複數植球墊25於該介電層24之第二表面24b與該導電柱23之第二端23b上,以電性連接該導電柱23;再移除該光阻。接著,形成絕緣保護層26於該介電層24之第二表面24b上,且藉由整平製程,使該絕緣保護層26之表面與該植球墊25之表面齊平,令該絕緣保護層26外露該些植球墊25。
於本實施例中,該絕緣保護層26與介電層24係為相同材質,例如:封裝膠體;然而,於其他實施例中,該絕緣保護層26與介電層24可為不同材質,並無特別限制。
如第2E圖所示,藉由蝕刻製程,貫穿該基板20以形成開口200,且該開口200外露該些電性接觸墊22及該介電層24之部分第一表面24a。
再者,亦藉由蝕刻製程,使該植球墊25’微凹,令該植球墊25’之表面低於該絕緣保護層26之表面。但於其他實施例中,仍可使該絕緣保護層26之表面與該植球墊25之表面保持齊平,並無限制植球墊之高度。
如第2F圖所示,藉由預鍍引腳框架(pre-plated lead frame,PPF)方式,形成表面處理層250於該電性接觸墊22與該植球墊25’上,且形成該表面處理層250之材料係為電鍍鎳、鈀及金材(Ni/Pd/Au)之合金。
如第2E’及2F’圖所示,於另一實施例中,係先以無電電鍍(Electroless plating)銅材之方式形成金屬層251於該絕緣保護層26與該植球墊25’上,再形成該開口200;接著,形成該表面處理層250於該電性接觸墊22上,再移除該金屬層251。接著,形成另一表面處理層250’於該植球墊25’上,且形成該另一表面處理層250’之材料係為有機可銲保護材(Organic Solderability Preservatives,OSP)。
如第2G圖所示,接續第2F圖之製程,係置放半導體晶片27於該開口200中之介電層24之第一表面24a上,再進行打線製程,使該半導體晶片27之電性連接墊270以銲線28電性連接該些電性接觸墊22。
接著,形成封裝膠體29於該開口200中之介電層24之第一表面24a上,以覆蓋該半導體晶片27、銲線28、該些電性接觸墊22與其上之表面處理層250。
於後續使用本發明之半導體封裝件2中,可形成導電元件(如銲球,圖未示)於該植球墊25’(或其上之表面處理層250,250’)上,以結合電子裝置(圖未示),如電路板。
本發明之製法係先於電性接觸墊22上形成導電柱23,再於導電柱23上形成植球墊25’,使該植球墊25’之位置及植球面積A可依需求調整,以增加銲球佈設之設計彈性,如第2E圖所示。故相較於習知技術,本發明之植球墊25之植球面積A(其寬度約350μm)不受限制電性接觸墊22之位置影響而可大幅增加,因而有效提高銲球之結合力,進而提高組裝後之產品可靠度。
再者,藉由該導電柱23連接該電性接觸墊22與植球墊25’,使各該電性接觸墊22的間距不需配合各該植球墊25的植球間距b,因而可依需求調整各該電性接觸墊22之間距及徑長,以增加電性接觸墊22佈設之設計彈性。因此,當植球間距b如習知技術之約500μm時,可使該導電柱23相對該植球墊25’中心偏移而令各該電性接觸墊22(其徑長d約220μm)之間距增加,故相較於習知技術,本發明之導電跡線21之數量可彈性化,例如:增加該導電跡線21之數量(導電跡線21之線寬w與線距t均約40μm),如圖所示之四條導電跡線21,以提升佈線密度。
本發明復提供一種半導體封裝件2,係包括:具有相對之第一表面24a與第二表面24b之介電層24、置於該介電層24之第一表面24a上之半導體晶片27、埋設於該介電層24之第一表面24a,並電性連接該半導體晶片27的至少二個電性接觸墊22、埋設於該介電層24之第一表面24a,且位於該至少二個電性接觸墊22之間之複數導電跡線21、設於該介電層24之第二表面24b上之複數植球墊25,25’、以及設於該介電層24中之複數導電柱23。
所述之電性接觸墊22係外露於該介電層24之第一表面24a,以藉銲線28電性連接該半導體晶片27之電性連接墊270。
所述之導電柱23具有相對之第一端23a與第二端23b,該第一端23a係結合該電性接觸墊22,而該第二端23b係結合該植球墊25,25’,以電性連接該植球墊25,25’與該電性接觸墊22。
所述之半導體封裝件2復包括形成於該介電層24之第一表面24a上之封裝膠體29,以覆蓋該半導體晶片27、銲線28與電性接觸墊22。亦包括設於該介電層24之第二表面24b上之絕緣保護層26,係外露該植球墊25,25’。
又,所述之半導體封裝件2復包括形成於該電性接觸墊22上之表面處理層250,且形成該表面處理層250之材料係為電鍍鎳、鈀及金材之合金。亦包括形成於該植球墊25,25’上之表面處理層250,250’,且形成該表面處理層250,250’之材料係為電鍍鎳、鈀及金材之合金或有機可銲保護材。
另外,所述之半導體封裝件2復包括具有貫穿開口200之基板20,且該介電層24之第一表面24a設於該基板20上以封蓋該開口200之一側,並使該半導體晶片27與該電性接觸墊22均位於該開口200中。
綜上所述,本發明之半導體封裝件及其製法,主要藉由導電柱之兩端連接電性接觸墊與植球墊,使得銲球佈設與電性接觸墊之位置無需相互配合,故可依需求調整該植球墊之位置與植球面積、及各該電性接觸墊之間距與導電跡線之數量,以達到佈線彈性化之目的。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
10...承載板
100,200...開口
11,21...導電跡線
12,22...電性接觸墊
14...絕緣層
14a...置晶側
14b...植球側
15,25,25’...植球墊
2...半導體封裝件
20...基板
210,230...光阻
23...導電柱
23a...第一端
23b...第二端
24...介電層
24a...第一表面
24b...第二表面
250,250’...表面處理層
251...金屬層
26...絕緣保護層
27...半導體晶片
270...電性連接墊
28...銲線
29...封裝膠體
A,A’...植球面積
b,b’...植球間距
d,d’...徑長
w,w’...線寬
t,t’...線距
第1圖係為習知QFN封裝件之線路結構之剖面示意圖;以及
第2A至2G圖係為本發明半導體封裝件之製法之剖面示意圖;其中,第2E’至2F’圖係為第2E至2F圖之另一實施態樣。
2...半導體封裝件
20...基板
200...開口
21...導電跡線
22...電性接觸墊
23...導電柱
24...介電層
24a...第一表面
24b...第二表面
25’...植球墊
250...表面處理層
26...絕緣保護層
27...半導體晶片
270...電性連接墊
28...銲線
29...封裝膠體
Claims (26)
- 一種半導體封裝件,係包括:介電層,係具有相對之第一表面與第二表面;半導體晶片,係置於該介電層之第一表面上;至少二個電性接觸墊,係埋設且外露於該介電層之第一表面,並電性連接該半導體晶片;複數植球墊,係設於該介電層之第二表面上;以及複數導電柱,係設於該介電層中,且各該導電柱具有相對之第一端與第二端,該第一端結合該電性接觸墊,而第二端結合該植球墊,以電性連接該植球墊與該電性接觸墊。
- 如申請專利範圍第1項所述之半導體封裝件,其中,該半導體晶片係以打線方式電性連接該電性接觸墊。
- 如申請專利範圍第1項所述之半導體封裝件,復包括形成於該電性接觸墊上之表面處理層。
- 如申請專利範圍第3項所述之半導體封裝件,其中,形成該表面處理層之材料係為鎳、鈀及金。
- 如申請專利範圍第1項所述之半導體封裝件,復包括形成於該植球墊上之表面處理層。
- 如申請專利範圍第5項所述之半導體封裝件,其中,形成該表面處理層之材料係為鎳、鈀及金或有機可銲保護材。
- 如申請專利範圍第1項所述之半導體封裝件,復包括形成於該介電層之第一表面上之封裝膠體,以覆蓋該半導體晶片與該電性接觸墊。
- 如申請專利範圍第1項所述之半導體封裝件,復包括具有貫穿開口之基板,且該介電層之第一表面係設於該基板上以封蓋該開口之一側。
- 如申請專利範圍第8項所述之半導體封裝件,其中,該半導體晶片位於該開口中,且該電性接觸墊亦外露於該開口。
- 如申請專利範圍第1項所述之半導體封裝件,復包括絕緣保護層,係設於該介電層之第二表面上,且外露該植球墊。
- 如申請專利範圍第1項所述之半導體封裝件,復包括複數導電跡線,係埋設於該介電層之第一表面,且位於該至少二個電性接觸墊之間。
- 一種半導體封裝件之製法,係包括:於一基板上形成至少二個電性接觸墊;形成複數導電柱於該至少二個電性接觸墊上;形成介電層於該基板上,以包覆該導電柱與電性接觸墊,且該介電層外露該導電柱;形成複數植球墊於該介電層與該導電柱上,以電性連接該導電柱;形成絕緣保護層於該介電層上,且該絕緣保護層外露該植球墊;貫穿該基板以形成開口,俾令該開口外露該些電性接觸墊;以及置放半導體晶片於該開口中,使該半導體晶片電性連接該些電性接觸墊。
- 如申請專利範圍第12項所述之半導體封裝件之製法,其中,該電性接觸墊係以電鍍方式形成。
- 如申請專利範圍第12項所述之半導體封裝件之製法,其中,該導電柱係以電鍍方式形成。
- 如申請專利範圍第12項所述之半導體封裝件之製法,其中,該植球墊係以電鍍方式形成。
- 如申請專利範圍第12項所述之半導體封裝件之製法,其中,該開口係以蝕刻方式形成。
- 如申請專利範圍第12項所述之半導體封裝件之製法,其中,該半導體晶片係以打線方式電性連接該電性接觸墊。
- 如申請專利範圍第12項所述之半導體封裝件之製法,復包括於形成該開口後,形成表面處理層於該電性接觸墊與該植球墊上。
- 如申請專利範圍第18項所述之半導體封裝件之製法,其中,形成該表面處理層之材料係為鎳、鈀及金。
- 如申請專利範圍第12項所述之半導體封裝件之製法,復包括於形成該開口前,形成金屬層於該絕緣保護層與該植球墊上,且於形成該開口後,再形成表面處理層於該電性接觸墊上,接著,移除該金屬層。
- 如申請專利範圍第20項所述之半導體封裝件之製法,其中,該金屬層係為以無電電鍍方式形成之銅材。
- 如申請專利範圍第20項所述之半導體封裝件之製法,復包括於移除該金屬層後,形成另一表面處理層於該植球墊上。
- 如申請專利範圍第22項所述之半導體封裝件之製法,其中,形成該表面處理層之材料係為鎳、鈀及金或有機可銲保護材。
- 如申請專利範圍第12項所述之半導體封裝件之製法,復包括形成封裝膠體於該開口中,以覆蓋該半導體晶片與該電性接觸墊。
- 如申請專利範圍第12項所述之半導體封裝件之製法,其中,形成該電性接觸墊之步驟,復包括於該基板上形成複數導電跡線,且該複數導電跡線係位於該至少二個電性接觸墊之間。
- 如申請專利範圍第25項所述之半導體封裝件之製法,其中,該導電跡線係以電鍍方式形成。
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2011
- 2011-07-27 TW TW100126529A patent/TWI497668B/zh active
- 2011-08-09 CN CN201110229561.5A patent/CN102903680B/zh active Active
- 2011-09-23 US US13/243,021 patent/US20130026657A1/en not_active Abandoned
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI550791B (zh) * | 2014-01-16 | 2016-09-21 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
TWI581386B (zh) * | 2014-06-16 | 2017-05-01 | 恆勁科技股份有限公司 | 封裝裝置及其製作方法 |
Also Published As
Publication number | Publication date |
---|---|
CN102903680B (zh) | 2015-11-25 |
US20130026657A1 (en) | 2013-01-31 |
CN102903680A (zh) | 2013-01-30 |
TWI497668B (zh) | 2015-08-21 |
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