TW201110252A - Method for manufacturing tight pitch, flip chip integrated circuit packages - Google Patents

Method for manufacturing tight pitch, flip chip integrated circuit packages Download PDF

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Publication number
TW201110252A
TW201110252A TW099119160A TW99119160A TW201110252A TW 201110252 A TW201110252 A TW 201110252A TW 099119160 A TW099119160 A TW 099119160A TW 99119160 A TW99119160 A TW 99119160A TW 201110252 A TW201110252 A TW 201110252A
Authority
TW
Taiwan
Prior art keywords
solder paste
package substrate
die
conductive bumps
placing
Prior art date
Application number
TW099119160A
Other languages
English (en)
Inventor
Christopher James Healy
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of TW201110252A publication Critical patent/TW201110252A/zh

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    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867Applying pastes or inks, e.g. screen printing
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    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

201110252 六、發明說明: 【發明所屬之技術領域】 本發明係關於積體電路之封裝,且更特定言之係關於覆 晶積體電路封裝。
【先前技術J 在覆晶封裝之積體電路(或簡稱「覆晶」)中,含有積體 電路之晶粒(晶片)使其作用面面向封褒基板。在覆晶製程 (亦形式上稱作控制崩潰晶片連接(C4)蒸發凸塊製程”, 形成導電凸塊並將其焊接至作用面上之襯墊。接著將具有 焊料凸塊之晶粒面朝下置放至多層有機封裝基板上之=配 接合襯墊上。回焊該組件以使得導電凸塊焊接至封 上之襯墊以在積體電路之作用面與封裝基板之間提供錢 接。此電連接形成所謂之第m互連件之部分。導電凸塊 亦在晶粒與封裝基板之間提供一負載承載連接。通常,導 電凸塊包含焊料。 在晶粒附著至基板之後,環氧樹脂(或底膠)通常塗覆於 晶粒與封裝基板之間的界面處以幫助補償晶粒與封裝基板 之間的熱膨脹係數(CTE)的差異,並防止濕氣接觸到晶粒 表面。為了進一步保護,覆晶亦可以液體環氧樹脂加以覆 圖1以簡化形式說明包含將覆B a私,餘 、 ^ 3肘復日日日日板上之導電凸塊附著 並焊接至封裝基板的三個步驟之劁 丨U少哪^耘,其中以順序次序將 該三個步驟標記為「八」、4」、*「〇」。在步驟八中,將 由工具1〇4固持之晶粒1〇2浸潰至助熔樹脂1〇6中。箭頭⑽ 148997.doc 201110252 圖形化地表示此浸潰製程,其中將導電凸塊1 ίο浸潰至助 熔樹脂106中且接著拉出。在步驟B中,數字標記112指示 潤濕導電凸塊11 〇之焊料。箭頭114圖形化地表示將晶粒 102置放至封裝基板116上。在步驟C中,波形線118圖形化 地表示施加熱以引起焊料之回焊以使得導電凸塊11 〇焊接 至封裝基板116上之襯墊(未圖示)。 隨著積體電路隨較高數目之輸入及輸出襯墊以及導電凸 塊之數目的相應增加而變得較複雜,預期增加導電凸塊之 間距。然而’使用諸如圖1中所說明之回焊及附著製程的 回焊及附著製程’較緊密間距可能出現一些問題,僅列舉 少數此等問題:導致較低良率之開路或短路、導電凸塊上 之焊料的不良可濕性及可隨時間流逝出現故障的導電凸塊 與概塾之間的電連接。晶粒及封裝基板之撓屈可增加此等 問題之可能性。 在緊密間距覆晶積體電路封裝中,產生良好良率及可靠 性之將晶粒附著至封裝基板的低成本製造程序具有實用 性。 【發明内容】 在-實施例中,將-晶粒浸潰至輝錫膏中,置放至一封 裝基板上,且接著回焊該焊錫膏 肝Θ日日粒附著至該封裝 暴板。 在另一實施例中,為了將一晶粒附著至一 焊錫膏塗覆至該封裝基板,在 、土 置放…… 焊料錫膏之前將該曰曰“ 置放至該封裝基板上;且接 砰茨绊錫貧以將該晶粒ft 148997.doc 201110252 著至該封裝基板。 在另一實施射,為了將—晶粒附著至—封裝基板,將 ㈣膏施配至該封裝基板上之襯塾上’在回焊該焊錫膏之 前將該晶粒置放至該封裝基板上,且接著回焊該焊錫膏以 將該晶粒附著至該封裝基板。 【實施方式】 在隨後之描述中,術語「_些實施例」之範疇將不限於 意謂-項以上之實施例’實情為,該範疇可包括一項實施 例、一項以上之實施例、或可能所有實施例。 D」之子圖式 圖2以圖2中標記為「A」、「b」、「c」及 說明根據-實施例的將晶粒上之導電凸塊附著並焊接至封 裝基板上之襯墊的製程,其中此等標記未必暗示一順序次 序。舉例而言,在圖2中說明為「A」之製程無需為一實施 例之部分,或若其包括於-實施例中,則未必需要在執行 標記為「B」之製程之前執行說明為「a」之製程。 、 在圖2之「A」中,使用噴射助熔劑製程,藉此工具2〇2 將助熔樹脂204塗覆(例如,噴塗)至封裝基板116上。在圖2 之「B」中,將晶粒1 〇2浸潰至焊錫膏2〇6中且接著移除, 其中箭頭208圖形化地表示此浸潰製程。焊錫膏2〇6可為 (例如)助熔劑與微粒焊料之組合。在「B」中之浸潰製程 中,將導電凸塊110之底部部分與焊錫膏206接觸以使得當 工具104自焊錫膏206移除導電凸塊no時,在導電凸塊【Η 之間不存在可導致短路之潤濕。圖2之子圖式「c」說明焊 錫膏206潤濕導電凸塊110之底表面,以使得在導電凸塊之 148997.doc 201110252 間不存在造成短路之焊料橋接。箭頭212圖形化地表示將 晶粒102置放至封裝基板ι16上。 若執行圖2之「A」中所指示之製程,則在「c」之製程 中助熔樹脂204已在封裝基板116上,但對於—些實施例而 言,可不執行圖2中之「A」所指示的製程,以使得在 C」之製程中,助熔樹脂204可不存在於封裝基板116 上。對於一些實施例而言,助熔樹脂2〇4可具有約5 pm至 15 μιη之厚度。當執行圖2中之製程「c」時,助熔樹脂2〇4 之使用可增加焊錫膏2 〇 6的可濕性。 在圖2之「D」中,波形線118圖形化地表示施加熱以回 焊焊錫膏2 0 6以便將導電凸塊丨丨〇焊接並附著至封裝基板 116上之概塾(未圖示)。 圖3說明根據另一實施例的將晶粒上之導電凸塊附著並 焊接至封裝基板上之襯墊的製程。圖3中之子圖式標記為 「A」、「B」、「C」及「D」’其中此等標記之字母次序暗示 順序-人序。在圖3之製程「a」中,如箭頭3〇6圖形化地 表示,將包含多個針304之工具302浸潰至焊錫膏206中且 接著移除。針304具有與晶粒1 〇2上之導電凸塊】丨〇相同之 陣列圖案。 在圖3之製程「B」中,焊錫膏206潤濕針3〇4之尖端,其 中箭頭308圖形化地表示將針304之尖端接近封裝基板116 置放以將焊錫膏2〇6施配至封裝基板116上。 圖3之製程「C」說明已將焊錫膏206施配至封裝基板116 上以按照與導電凸塊110相同之間距形成焊錫膏2〇6之液 148997.doc 201110252 滴。箭頭310圖形化地表示將晶粒l〇2置放至封裝基板116 上以使得導電凸塊110與焊錫膏206之相應液滴接觸。 在圖3之製程「D」中,波形線118圖形化地表示熱之施 加引起焊錫膏206之回焊使得導電凸塊11 〇經焊接至在封裝 基板116上之概塾(未圖示)。 圖4說明根據另一實施例的將晶粒上之導電凸塊附著並 焊接至封裝基板上之襯塾的製程。圖4中之子圖式標記為 「A」、「B」及「C」,其中此等標記之字母次序暗示一順 序次序。在圖4之製程「A」中’包含多個針404之工具402 將焊錫膏206施配至封裝基板206上之襯塾405上。針404在 其尖端處具有小開口以便在壓力下時,焊錫膏206穿經此 等開口流動以使得焊錫膏206之液滴可施配至封裂基板i i 6 上之襯墊405上。箭頭406圖形化地表示使工具4〇2帶近封 裝基板116、施配焊錫膏206及將工具402帶離之製程。針 404具有與晶粒1〇2上之導電凸塊11〇相同之陣列圖案。 圖4中之製程「B」及「C」分別與圖3中之製程「c」及 「D」相同’因此無需關於圖4重複圖3之實施例之描述的 部分。(為了容易說明’現將襯墊405展示於圖4之製程 「B」及「C」中。) 亦可執行諸如圖2、圖3及圖4中的將底膠塗覆至晶粒1〇2 與封裝基板11 ό之間的界面之覆晶封裝技術中所熟知之額 外製程,但為了容易說明,未在此等圖式中展示此等額外 製程。且,襯墊、&塊下金屬化層及諸如氧化物表面保護 層之其他保護層為吾人所熟知’但為了容易說明,未在入 148997.doc 201110252 部此等圖式或此等圖式中之一些中加以展示。 在不脫離下文所主張之本發明之範疇的情況下’可對所 描述之實施例進行各種修改。 【圖式簡單說明】 圖1說明覆晶製造中之習知製程。 圖2說明根據一實施例的將晶粒上之導電凸塊附著並焊 接至封裝基板上之襯墊的製程。 圖3說明根據另一實施例的將晶粒上之導電凸塊附著並 焊接至封裝基板上之襯墊的製程。 圖4說明根據另一實施例的將晶粒上之導電凸塊附著並 焊接至封裝基板上之襯墊的製程。 【主要元件符號說明】 102 晶粒 104 工具 110 導電凸塊 112 焊料 116 封裝基板 118 波形線 202 工具 204 助熔樹脂 206 焊錫膏 208 箭頭 212 箭頭 302 工具 148997.doc 201110252 304 402 404 405 針 工具 針 襯塾 i48997.doc

Claims (1)

  1. 201110252 七、申請專利範圍: 種將一晶粒附著至一封裝基板之方法,該方法包含 將该晶粒之至少一部分浸潰至焊錫膏中; 將該晶粒置放至該封裝基板上;及 回焊該焊錫膏以將該晶粒附著至該封裝基板。 2. 如凊求項1之方法,該晶粒具有導電凸塊,其中將該晶 粒浸潰至料料t包含㈣科電凸塊錢至該焊錫 膏中。 3. 如睛求項2之方法,該封裝基板具有襯墊,其中回焊該 焊錫膏以將該晶粒附著至該封裝基板包含將該等導電凸 塊焊接至該等概墊。 4. 如明求項i之方法,該封裝基板具有襯墊,該晶粒具有 導電凸塊,其中回焊該焊錫膏以將該晶粒附著至該封裝 基板包含將該等導電凸塊焊接至該等襯墊。 5. 如請求項1之方法,其進_步包含: 在將該晶粒置放至該封裝基板上之前將助熔樹脂塗覆 至該封裝基板。 6. —種將—晶粒附著至—封裝基板之方法,該方法包含: 將焊錫膏塗覆至該封裝基板; 在回焊該焊錫膏之前將該晶粒置放至該封裝基板 上;及 回焊該焊錫膏以將該晶粒附著至該封裝基板。 7.如清求項6之方法,該封裝基板具有襯墊,其中將焊錫 膏塗覆至該封裝基板包含在該封裝基板上之該等襯墊上 148997.doc 201110252 形成焊錫膏之液滴。 8. 9. 10. 11. 12. 13. 14. 15. 如-月求項7之方法’該晶粒具有導電凸塊,其中在回焊 該焊錫膏之前將該晶粒置放至該封裝基板上包含置放: 等導電凸塊使之與焊錫膏之該等液滴接觸。 Λ 月求員6之方法’其中將焊錫膏塗覆至該封裝基板包 含將—工具浸潰至該焊錫膏中。 :請求項9之方法’該封裝基板具有襯墊,其中將焊锡 ,塗覆至該封裝基板包含在該封裝基板上之該等襯墊上 形成焊锡膏之液滴。 如。月求項10之方法’該晶粒具有導電凸塊,其中在回焊 該焊錫膏之前將該晶粒置放至該料基板上包含置放該 等導電凸塊使之與焊錫膏之該等液滴接觸。 / :請求項6之方法,該封裝基板具有襯塾,其中將焊錫 膏塗覆至該封裝基板包含穿經一工具中之開口施配焊錫 膏^在該封裝基板上之該等襯墊上形成焊錫膏之液滴。 如》月求項12之方法,該晶粒具有導電凸塊,其中在回焊 该焊錫膏之前將該晶粒置放至該封裝基板上包含置放該 等導電凸塊使之與焊錫膏之該等液滴接觸。 / 一種將-晶粒附著至-封裝基板之方法,該方法包含: 將焊錫膏施配至該封裝基板上之襯墊上; 在回焊該焊錫膏之前將該晶粒置放至該封裝基板 上;及 ~ 土 回焊該焊錫膏以將該晶粒附著至該封裝基板。 如請求項14之方法,其中將焊錫f施配至該封裝基板上 148997.doc 201110252 之該等襯墊上包含將一工具浸潰至該焊錫膏中以在該等 襯墊上形成焊錫膏之液滴。 16. 如請求項丨5之方法,該晶粒具有導電凸塊,其中在回焊 該焊錫膏之前將該晶粒置放至該封裝基板上包含置放該 等導電凸塊使之與焊錫膏之該等液滴接觸β 17. 如請求項14之方法,其中將焊錫膏施配至該封裝基板上 之該等襯墊上包含穿經一工具中之開口施配蟬錫膏以在 該等襯墊上形成焊錫膏之液滴。 18. 如請求項17之方法,該晶粒具有導電凸塊,其中 θ 該焊錫膏之前將該晶粒置放至該封裝基板上包含置放, 等導電凸塊使之與焊錫膏之該等液滴接觸。 Λ 148997.doc
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CN102804371B (zh) 2015-05-13
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US20100314433A1 (en) 2010-12-16

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