TW201005874A - Semiconductor devices with extended active regions - Google Patents

Semiconductor devices with extended active regions Download PDF

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Publication number
TW201005874A
TW201005874A TW098116023A TW98116023A TW201005874A TW 201005874 A TW201005874 A TW 201005874A TW 098116023 A TW098116023 A TW 098116023A TW 98116023 A TW98116023 A TW 98116023A TW 201005874 A TW201005874 A TW 201005874A
Authority
TW
Taiwan
Prior art keywords
active region
region
trench
recess
active
Prior art date
Application number
TW098116023A
Other languages
English (en)
Chinese (zh)
Inventor
Mark D Hall
Glenn C Abeln
Chong-Cheng Fu
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of TW201005874A publication Critical patent/TW201005874A/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/05—Manufacture or treatment characterised by using material-based technologies using Group III-V technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Recrystallisation Techniques (AREA)
TW098116023A 2008-07-30 2009-05-14 Semiconductor devices with extended active regions TW201005874A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/182,421 US8062953B2 (en) 2008-07-30 2008-07-30 Semiconductor devices with extended active regions

Publications (1)

Publication Number Publication Date
TW201005874A true TW201005874A (en) 2010-02-01

Family

ID=41607463

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098116023A TW201005874A (en) 2008-07-30 2009-05-14 Semiconductor devices with extended active regions

Country Status (5)

Country Link
US (2) US8062953B2 (enExample)
JP (1) JP5721178B2 (enExample)
CN (1) CN102113110B (enExample)
TW (1) TW201005874A (enExample)
WO (1) WO2010014287A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI562373B (en) * 2014-02-19 2016-12-11 Vanguard Int Semiconduct Corp Semiconductor device and method for manufacturing the same
US9978861B2 (en) 2014-04-09 2018-05-22 Vanguard International Semiconductor Corporation Semiconductor device having gate in trenches

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103367147A (zh) * 2012-03-29 2013-10-23 中芯国际集成电路制造(上海)有限公司 一种鳍型半导体器件的制造方法
CN103681325B (zh) * 2012-09-04 2016-08-03 中芯国际集成电路制造(上海)有限公司 一种鳍片场效应晶体管的制备方法
US9337079B2 (en) * 2012-10-09 2016-05-10 Stmicroelectronics, Inc. Prevention of contact to substrate shorts
US9437440B2 (en) * 2012-11-21 2016-09-06 Infineon Technologies Dresden Gmbh Method for manufacturing a semiconductor device
CN104282612B (zh) * 2013-07-01 2017-04-19 中芯国际集成电路制造(上海)有限公司 一种半导体器件浅沟槽隔离结构的制作方法
JP2017515480A (ja) * 2014-05-15 2017-06-15 キャリスタ， インコーポレイテッド 極長炭素鎖化合物を生物学的に産生するための方法
KR102675909B1 (ko) * 2017-02-20 2024-06-18 삼성전자주식회사 반도체 소자
KR102342551B1 (ko) * 2017-09-25 2021-12-23 삼성전자주식회사 아이솔레이션 영역을 포함하는 반도체 소자

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000260952A (ja) * 1999-03-05 2000-09-22 Toshiba Corp 半導体装置
US6483156B1 (en) 2000-03-16 2002-11-19 International Business Machines Corporation Double planar gated SOI MOSFET structure
JP2002158932A (ja) * 2000-11-16 2002-05-31 Sony Corp 固体撮像装置及び固体撮像素子の駆動方法
JP2002270685A (ja) * 2001-03-08 2002-09-20 Mitsubishi Electric Corp 半導体装置の製造方法
US6630288B2 (en) * 2001-03-28 2003-10-07 Advanced Micro Devices, Inc. Process for forming sub-lithographic photoresist features by modification of the photoresist surface
US6716571B2 (en) * 2001-03-28 2004-04-06 Advanced Micro Devices, Inc. Selective photoresist hardening to facilitate lateral trimming
KR20050045599A (ko) 2003-11-12 2005-05-17 삼성전자주식회사 선택적 에피텍셜 성장을 이용한 소자분리막 형성방법
KR100673896B1 (ko) * 2004-07-30 2007-01-26 주식회사 하이닉스반도체 트렌치 구조의 소자분리막을 갖는 반도체소자 및 그 제조방법
JP2006237509A (ja) * 2005-02-28 2006-09-07 Toshiba Corp 半導体装置
JP4718894B2 (ja) * 2005-05-19 2011-07-06 株式会社東芝 半導体装置の製造方法
KR100772114B1 (ko) * 2006-09-29 2007-11-01 주식회사 하이닉스반도체 반도체 소자의 제조방법

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI562373B (en) * 2014-02-19 2016-12-11 Vanguard Int Semiconduct Corp Semiconductor device and method for manufacturing the same
US9978861B2 (en) 2014-04-09 2018-05-22 Vanguard International Semiconductor Corporation Semiconductor device having gate in trenches

Also Published As

Publication number Publication date
JP2011530168A (ja) 2011-12-15
CN102113110B (zh) 2013-12-11
WO2010014287A1 (en) 2010-02-04
CN102113110A (zh) 2011-06-29
US8062953B2 (en) 2011-11-22
US20120007155A1 (en) 2012-01-12
JP5721178B2 (ja) 2015-05-20
US20100025805A1 (en) 2010-02-04

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