Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
  • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
  • H10D89/10—Integrated device layouts
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B10/00—Static random access memory [SRAM] devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/05—Manufacture or treatment characterised by using material-based technologies using Group III-V technology
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
  • H10D86/01—Manufacture or treatment

Definitions

• This disclosure relates generally to semiconductor processing, and more specifically, to forming semiconductor devices having extended active regions.
• CMOS processing technologies typically impose various dimensional constraints related to active spaces and active widths. For example, a representative 90 nm node CMOS technology may allow a minimum active space of 140 nm and a minimum active width of 1 10 nm. Typically, such dimensional constraints are imposed to allow manufacturing tolerances during semiconductor processing and to ensure adequate device isolation. In particular, imposing such dimensional constraints may result in easier patterning of active regions and the subsequent filling of the gaps created by shallow trenches.
• FIG. 1 is a cross-sectional view of a semiconductor device during a processing step
• FIG. 2 is a cross-sectional view of a semiconductor device during a processing step
• FIG. 3 is a cross-sectional view of a semiconductor device during a processing step
• FIG. 4 is a cross-sectional view of a semiconductor device during a processing step
• FIG. 5 is a cross-sectional view of a semiconductor device during a processing step
• FIG. 6 is a cross-sectional view of a semiconductor device during a processing step
• FIG. 7 is a cross-sectional view of a semiconductor device during a processing step
• FIG. 8 is a cross-sectional view of a semiconductor device during a processing step
• FIG. 9 is a cross-sectional view of a semiconductor device during a processing step
• FIG. 10 is a cross-sectional view of a semiconductor device during a processing step.
• FIG. 11 is a top view of the semiconductor device of FIG. 10 during a processing step.
• a method of forming a semiconductor device includes forming a trench adjacent to a first active area.
• the method further includes filling the trench with insulating material.
• the method further includes forming a masking feature over a center portion of the trench to expose a first side of the trench between a first side of the masking feature and the first active area.
• the method further includes etching into the first side of the trench to leave a first recess in the trench.
• the method further includes growing a first epitaxial region in the first recess to extend the first active area to include the first recess and thereby form an extended first active region.
• a method of forming a semiconductor device includes providing a semiconductor substrate.
• the method further includes forming a trench around an active region that defines a boundary of the active region.
• the method further includes filling the trench with insulating material to form an isolation region.
• the method further includes forming a masking feature over the isolation region, wherein the masking feature has an edge spaced from the active region to provide an exposed region of the isolation region between the edge of the masking feature and the active region.
• the method further includes etching into the exposed region to form a recess.
• the method further includes filling the recess with semiconductor material to form an extended active region as a combination of the recess filled with semiconductor material and the active region.
• a semiconductor device in yet another aspect, includes a semiconductor structure having a top surface.
• the semiconductor device further includes an isolation region of insulating material extending from the top surface to a first depth.
• the semiconductor device further includes an active region of semiconductor material having a central portion and an adjacent portion, wherein: (1 ) the central portion extends from the top surface to at least the first depth; (2) the adjacent portion has top portion at the top surface and a bottom portion at no more than a second depth; (3) the second depth is less than the first depth; (4) the adjacent portion is between the central portion and isolation region from the top portion to the bottom portion; and (5) the isolation region is directly under the bottom portion of the adjacent portion.
• FIG. 1 is a cross-sectional view of a semiconductor device 10 during a processing step.
• Semiconductor device 10 may be formed using a semiconductor substrate 12 using conventional semiconductor processing equipment.
• Semiconductor substrate 12 described herein can be any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above.
• SOI silicon-on-insulator
• a layer of pad oxide 14 may be grown over a top surface of substrate 12.
• the pad oxide layer may be 5 nm to 25 nm thick.
• a nitride layer 16 may be deposited over the layer of pad oxide.
• the nitride layer may be 50 nm to 200 nm thick.
• active regions 24, 26, 28, and 30 may be formed, such that these active regions are separated by trenches 18, 20, and 22, respectively.
• trenches 18, 20, and 22 may be filled using an insulating material to form shallow trench isolation regions 32, 34, and 36.
• the top surface of the shallow trench isolation regions may be planarized using chemical-mechanical polishing, for example.
• nitride layer 16 may be removed from active regions 24, 26, 28 and 30 using a wet phosphoric etch, for example.
• pad oxide layer 14 may be removed using a hydrofluoric etch, for example.
• trench divots such as a trench divot 46 may be formed as a result of the removal of the pad oxide layer.
• sacrificial oxide layers 38, 40, 42, and 44 may be grown.
• a patterned photoresist layer including photoresist sections 48, 50, and 52 may be formed.
• photoresist sections 48, 50, and 52 may be trimmed prior to etching.
• trimming may include ashing.
• masking feature 50 formed over shallow trench isolation region 34, may leave exposed regions on both sides. Each exposed region may be between the edge of masking feature 50 and the corresponding active region.
• sacrificial oxide layers 38, 40, 42, and 44 and a portion of the oxide in trench isolation regions 32, 34, and 36 may be removed creating recesses 54, 56, 58, and 60.
• an isotropic dry etch using hydrofluoric acid (HF) or an anisotropic oxide dry etch may be used as part of this step.
• the depth of the recesses may be 30 nm to 100 nm.
• photoresist sections 48, 50, and 52 may be removed.
• silicon may be epitaxially grown to form epitaxial regions 62 and 66. This step results in selective widening of active regions. Thus, for example, the original active regions 64 and 68 are widened as a result of the grown epitaxial regions. At the same time, however, unpatterned areas are protected by sacrificial oxide layers 38 and 44, for example. Because silicon is grown epitaxially, it has the same crystal orientation as the original active silicon. Thus, using this process, selective active regions can be widened to provide more drive current, as needed. Moreover, the same shallow trench isolation regions are used to provide isolation for both widened and not-widened active regions.
• FIG. 8 describes the step as epitaxial growth of silicon, silicon may be provided in the recesses using other methods, as long as the provided silicon has the same crystal structure and orientation as the original silicon in the active regions.
• the top surface device 10 may be polished to remove grown epitaxial regions, except the epitaxial growth formed in extended active regions 82 and 84, for example.
• this step may be performed using chemical- mechanical polishing techniques.
• active regions 70 and 72 may have a width 76 as opposed to original width 74.
• extensions 78 and 80 may add to original width 74, as shown in FIG. 9.
• Extended active regions 82 and 84 may provide additional surface area resulting in a higher transistor drive current.
• the extension of active regions may narrow shallow trench isolation region 34, as indicated by reference numeral 81.
• gate dielectric layers 86 and 88 may be formed over active regions 70 and 72.
• a gate electrode layer 90 may be formed, as shown in FIG. 10. Additional spacers (not shown) may be formed to form transistors.
• transistors 96 and 98 may be formed having channel widths corresponding to active regions 92 and 94, respectively, with extended width 76, as compared with original width 74.
• semiconductor device 10 may include a semiconductor structure (substrate 12, for example) having a top surface. Isolation regions 32, 34, and 36 may extend from the top surface of substrate 12 to a certain depth. Active region 92 may have a central portion (representative of area covered by active region 74, for example) and an adjacent portion (representative of area covered by active region 84, for example).
• the central portion of the active region may extend at least to the same depth as the depth of isolation regions 32, 34, and 36, for example.
• the adjacent portion may have a top portion that has a top surface that is in the same plane as the top surface of the central portion and it may have a bottom portion at no more than a certain depth that is less than the depth to which the central portion extends.
• at least a portion of isolation region 32 may be directly under the bottom portion of the adjacent portion.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Element Separation (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Semiconductor Memories (AREA)
• Recrystallisation Techniques (AREA)

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• 2008
  • 2008-07-30 US US12/182,421 patent/US8062953B2/en active Active
• 2009
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  • 2009-05-11 JP JP2011521138A patent/JP5721178B2/ja active Active
  • 2009-05-14 TW TW098116023A patent/TW201005874A/zh unknown
• 2011
  • 2011-09-19 US US13/235,580 patent/US20120007155A1/en not_active Abandoned

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