TW200926392A - Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods - Google Patents

Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods Download PDF

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Publication number
TW200926392A
TW200926392A TW097128170A TW97128170A TW200926392A TW 200926392 A TW200926392 A TW 200926392A TW 097128170 A TW097128170 A TW 097128170A TW 97128170 A TW97128170 A TW 97128170A TW 200926392 A TW200926392 A TW 200926392A
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Taiwan
Prior art keywords
individual
die
package
metal
shell
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TW097128170A
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English (en)
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TWI508260B (zh
Inventor
Meow Koon Eng
Yong Poo Chia
Suan Jeung Boon
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Micron Technology Inc
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Publication of TW200926392A publication Critical patent/TW200926392A/zh
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Description

200926392 九、發明說明： 【發明所屬之技術領域】 本揭示案大體係關於具有金屬導線之微電子晶粒封裝， 且更明確地說，係關於經組態用於堆疊晶粒封裝之金屬導 線。 . 【先前技術】 、 經封裝之微電子組合（諸如，記憶體晶片及微處理器晶 片）通常含有一安裝至一基板且裝入於一塑料保護罩中之 Φ 微電子晶粒。該晶粒含有功能特徵，諸如，記憶體單元、 處理器電路及互連電路。該晶粒亦通常含有電耦接至功能 特徵之結合襯墊。結合襯墊電連接至延伸到保護罩外部的 針腳或其他類型之端子，用於將晶粒連接至匯流排、電路 或其他微電子組合。 在一習知配置中，將晶粒安裝至支撐基板（例如，印刷 電路板），且用線結合將晶粒結合襯塾電叙接至基板之對 應的結合襯墊。在密封後，可用焊球或其他合適連接來將 ® 纟板電連接至外部裝置。因此，基板支撲晶粒，且提供晶 粒與外部裝置之間的電鏈接。 八sa 在其他習知配置中，可將晶粒安裝至具有連接至抽取式 ㈣之傳導性導線指狀物之導線架。在製造期間，該框^ 臨時地將導線指狀物支撐在相對於晶粒之適當位置中。每 -導線指狀物耦接至晶粒之對應的結合襯墊(例 ： 線結合或金屬曹公；^、 ' 屬重刀布層），且以框架及導線指狀物中之 一者的-部分延伸出密封材科之方式來密封該組合。接著 133286.doc 200926392 修剪該框架’且每-導線指狀物之暴露部分將晶粒連接至 外部組件。一般而言，個別導線指狀物可經彎曲且接著耦 接至一對應的外部結合襯塾。 晶粒製造商們已受到減小由晶粒佔據之體積且仍增加所 得經密封之組合的容量之不斷增加的壓力。為了滿足此等 ' 需求，晶粒製造商們常將多個晶粒相互疊置以増加在電路 * 板或晶粒所安裝至的其他元件上之有限表面積内的裝置之 容量或效能。 ❹ 【實施方式】 以下參照半導體裝置及製造半導體裝置之方法來描述本 揭示案之若干實施例的具體細節。在可含有基板之半導體 晶圓上製造半導體組件，將微電子裝置、微機械裝置、資 料儲存元件、光學器件、讀取/寫入組件及其他特徵製造 於半導體晶圓上或中。舉例而言，可將SRAM、DRAM(例 如，DDR/SDRAM)、快閃記憶體（例如，NAND快閃記憶 體）、處理器、成像器及其他類型之裝置建構於半導體晶 圓上。雖然以下描述關於具有積體電路之半導體裝置的許 多實施例，但製造於其他類型之基板上的其他類型之裝置 可處於本發明之範疇内。此外，本發明之若干其他實施例 • 可具有與此章節中所描述之組態、組件或程序不同的組 態、組件或程序。因此，一般熟習此項技術者將因此理解 本發明可具有帶有額外元件之其他實施例，或者本發明可 具有無以下關於圖1至圖丨2展示及描述的特徵中之若干者 之其他實施例。 133286.doc 200926392 圖1為具有複數個晶粒封裝1〇(個別地由參考數字1〇&至 1 〇d識別）之堆疊系統1 〇〇之一實施例之橫截面侧視圖。個 別晶粒封裝10可含有一微電子晶粒12、一模製介電殼14及 與殼14側向間隔開之金屬導線16(或金屬接觸）。殼14具有 側向殼側21、頂部殼側22及底部殼側23，且殼14密封晶粒 12及導線16之至少一部分。在圖1所展示之實例中，個別 - 導線1 6耦接至底部殼側23且至少部分朝向位於上部之晶粒 封裝或堆疊系統100之頂部突出。個別導線16可進一步含 〇 有一外部導線表面25及一内部導線表面26，内部導線表面 26具有一大體面向個別側向殼侧21之區域27。所說明之實 例的内部表面區域27位於個別導線16之有角度的導線部分 2 8上’有角度的導線部分2 8與側向殼側21侧向間隔該導線 之侧向導線部分29。晶粒封裝1 〇可進一步含有將導線i 6電 耦接至晶粒12之金屬跡線32及包住跡線32及晶粒12之有效 側之一部分的介電間隔層34。晶粒封裝10亦可含有輕接至 跡線32之封裝結合概塾36。舉例而言，堆疊系統1〇〇具有 ❹ 一插入式基板1 〇2,該插入式基板1〇2具有一金屬凸塊襯墊 104’該金屬凸塊襯墊丨04由結合襯墊連接1〇6電連接至在 第一晶粒封裝10a處之封裝結合襯墊36。 圖1中所示之堆疊系統100之實施例含有由黏接層112a_c 在對應之頂侧及底側處實體地耦接在一起之四個堆疊晶粒 封裝10a-d ’且該等晶粒封裝i〇a_d之導線16由外部封裝間 連接器114電搞接在一起。舉例而言，連接器η#可為丨八著 外部導線表面25之對應於垂直對準之導線丨6之集合之部分 133286.doc 200926392 及視情況沿著内部導線表面26之部分而形成的金屬焊料 線。因此’金屬襯墊104經由含有導線16及連接器114之傳 導路徑電耦接至晶粒封裝10a_d内之微電子晶粒。在許多 實施例申’且如圖1中所示，對應於晶粒封裝10a_c之導線 16延伸超出頂部殼侧22，接觸位於上部之晶粒封裝1 〇上之 • 外部導線表面25之一部分，且由個別連接器114固持至外 * 部導線表面25之該部分。另外，圖1中所展示之個別連接 器114之實施例沿著有角度的導線部分28及側向導線部分 〇 29附著至外部導線表面25及内部導線表面26的部分。在替 代實施例中，連接器114可僅沿著有角度之導線部分28附 著至外部導線表面25之一部分，且視情況，沿著側向導線 部分29附著至内部導線表面26之一部分。因此，連接器 114之若干實施例至少自有角度的導線部分28側向向外突 出’且視情況’可朝向側向殼側21在個別晶粒封裝1〇之間 延伸。 ©堆叠系統100可由一方法形成，該方法含有堆疊晶粒封 裝l〇a-d且在晶粒封裝1〇a_d之個別導線16處形成連接器 114 °堆疊且對準導線丨6可含有依次堆疊晶粒封裝丨， 使得一封裝之導線16被置放於鄰近的晶粒封裝上之對應導 線上方或下方，且使得下部封裝之導線16朝向上部封裝之 導線16向上突出。可使用波焊或回焊製程來形成連接器 1 M在波焊製程中，可將泵汲的波狀或級聯的液相金屬 焊料施加於有角度的導線部分28。在回焊製程中，具有金 屬粕末粒子之焊錫膏可經施加於有角度的導線部分28上且 133286.doc 200926392 接著經加熱以熔化金屬粒子。在此等或其他烊接製程中， 金屬焊料選擇性地潤濕（例如，當經加熱時）至外部導線表 面25之至少一部分，且視情況，内部導線表面26之一部 分，但焊料並不潤濕至殼14之介電材料。當金屬焊料冷卻 時連接器114形成，且個別晶粒封裝1 〇之個別導線丨6與 上部或下部晶粒封裝上之對應的導線耦接。在其他實施例 ' 中，個別導線16中之一些可不實體接觸在緊鄰的晶粒封裝 上之對應的導線，使得僅某些導線與鄰近的晶粒封裝互 〇 連。在任何此等實施例中，連接器114可橋接鄰近的晶粒 之垂直對準的導線16之間的垂直間隙（例如，見圖9 ,參考 68)。舉例而言，60微米或更小之垂直導線間隔距離可創 造出足夠的表面張力以用於形成個別導線16之間的焊料 橋。 一般而言，且與堆疊系統！ 00相對比，堆疊封裝或晶粒 之習知方法已具有挑戰性且花費高。舉例而言，因為習知 導線未經配置以面向介電殼或朝向位於上部的晶粒封裝突 ® 出，所以其可能難以定位，且若未準確地對準，可能在封 裝下方崩潰。此外，將一封裝上之習知導線附著至一對應 的封裝上之對應的導線耗時甚巨，且需要仔細地手動操縱 及檢查每一習知的導線間互連。舉例而言，在位於上部的 晶粒封裝上之習知的導線通常向下彎曲，使得其朝向位於 下部的晶粒封裝上之導線突出。當習知導線經歷附著製程 時’需要檢查導線間連接以驗證弯曲的導線相對於下部之 封裝正確地定位。同樣，堆疊習知封裝之製程難以標準 133286.doc 200926392 化’因為晶粒係按各種各樣的大小製造，且封裝同樣地在 大小上變化。因此，需要特製堆疊且互連習知封裝之製程 以適合於特定封裝類型之配置。 微電子晶粒封裝1 〇之若干實施例可易於堆疊且為穩固 的。舉例而言，在堆疊且對準了晶粒封裝1〇&_(1後，對應 的晶粒封裝之導線16經自動地充分對準以供連接器丨14相 ' 互耦接導線，且並不需要手動操縱來將個別導線相互對 準。另外’因為導線16自殼14之側面向外延伸，所以其提 0 供一位於個別導線之側向部分與有角度部分兩者上之接觸 表面；此致能使用簡單的焊接製程來相互耦接晶粒封裝 l〇a-d，且創造出不需要嚴格的對準容差之可靠的導線間 互連。同樣，藉由為個別導線16提供一表面以在其上壓縮 或回彈，晶粒封裝10之側向殼側21可防止導線16在晶粒封 裝堆疊期間崩潰。此外，導線16可進一步確定外部封裝尺 寸，使得可使用標準化的封裝大小來收容各種各樣的不同 大小之晶粒，如以下參看圖丨0進一步詳細地解釋。 ® 圖2A至圖8B說明根據本揭示案之若干實施例形成微電 子晶粒封裝之階段。圖2A為含有一坐落於釋放層45之頂部 上的金屬框架41之微電子組合4〇之俯視圖。框架41包含導 線部分42、開口 43及切割道44。開口 43暴露釋放層45之一 部分，用於鄰近導線部分42附著且定位晶粒12(圖丨），且切 割道44提供一切削或分裂路徑以用於自框架4丨切割個別晶 粒封裝（參看圖8A及圖8B進一步地描述）。在一實施例中， 框架41可由銅製造，且可含有沿著導線部分42之選擇性的 133286.doc -12- 200926392 銅鑛層。在其他實施例中，框架41可包含各種各樣的其他 金屬材料，諸如，鋁或鋁銅合金。舉例而言，釋放層45可 為熱或uv釋放膜。 圓2B及圖2C為展示框架41、導線部分42、釋放層杉及 支撐基板47(例如，矽晶圓或具有平坦表面之其他類型的 • 結構）的組合40之部分分解橫截面側視圖。圖2B進一步展 示一個別切割道44，及圖2C進一步展示個別導線部分“之 間的間隙48。間隙48與開口 43及支撐基板47 一起界定一空 © 穴之底部及側面，該空穴隨後將被填充有介電材料（參看 圖4A至圖4C進一步加以描述）。個別導線部分42相互間隔 開一間隔距離Sl，其應足夠大以防止連接器i 14在個別導 線上側向橋接。 圖3 A為在將微電子晶粒附著至釋放層45後的組合4〇之俯 視圖。更具體言之’圖3A展示框架41、導線部分42及開口 43 ’其中個別晶粒12經置放於開口 43内且鄰近導線部分 42。圖3B及圖3C為進一步展示開口 43及導線部分42之橫 ® 截面側視圖，導線部分42位於晶粒12之頂側表面下，且具 有厚度。在若干實施例中，導線部分42可具有在約5〇微 . 米至250微米之範圍内之厚度t丨。 圖4A為在介電材料50已形成於金屬框架41之頂側及晶粒 12之頂側上之後的組合40之俯視圖。舉例而言，介電材料 50可為聚合物或塑料，其經加熱且隨後沈積於框架μ之頂 部上及間隙内。舉例而言，介電材料5〇可經模製於框架Μ 及晶粒12之頂側上。圖48及圖4C為展示填充晶粒12周圍 133286.doc •13· 200926392 之開口 43及導線部分42之間的間隙48之介電材料50之橫截 面側視圖。在固化或冷卻後，變硬的介電材料50應在晶粒 12上、晶粒12之側面與導線部分42之間的間隙内，及導線 部分42之間的間隙48内形成一保護且電隔離罩。視情況， 介電材料50可在晶粒12上延伸厚度tz以完全密封全部晶粒 • 12及導線部分42。 圖5A及圖5B為在移除釋放層45及支撐基板47以暴露晶 粒12之底側表面52(例如，有效側）且暴露導線部分42之底 〇 側表面54後的組合40之橫截面側視圖及仰視圖。晶粒12之 底側表面52含有電耦接至晶粒12内之積體電路（未圖示）的 結合襯塾56(或有效特徵）。介電材料50將晶粒12固持於適 當位置處，且將晶粒12與導線部分42分隔開。 圖6為在晶粒12之底側表面52處形成介電間隔層34之一 實施例後之組合4〇的橫截面側視圖。間隔層34含有將結合 襯墊56電耦接至導線部分42及封裝結合襯墊％之金屬跡線 32。間隔層34可由諸如非傳導性氧化物或聚合物之材料製 造。舉例而言，金屬跡線32及封裝結合襯墊36可由銅或鋁 製造。間隔層34可因此為重分布結構。亦期望在某些實施 例中，可省略封裝結合襯墊36。舉例而言，在圖ι中，可 癌、略晶粒封裝10b々封裝結合襯墊，因為此等襯墊未電 連接至任何外部結合襯墊。 圖7為在藉由化學蝕刻、背面研磨或化學機械拋光製程 移除介電材料50之一部分以形成殼14後之組合4〇的橫截面 側視圖。舉例而言，介電材料5〇可經钱刻以暴露内部導線 133286.doc 14 200926392 表面26(圖1)及形成殼14之頂側22及側向殼側21。另外雖 然展示為具有傾斜表面，但在其他實施例中，側向殼侧21 可經形成使得其大體上與頂部殼側22垂直。然而，預期側 向殼側21之傾斜、彎的、錐形或其他分級構形向個別導線 提供位於上部之導線或晶粒封裝下方彎曲或壓縮的空間。 同樣地，傾斜的側向殼侧21可用以增加個別導線與側向殼 側21之上部分之間的侧向間隔距離，以為在内部導線表面 2 6上形成連接器提供較多空間。 © 圖8Α為在經由切割道44進行分離（例如，藉由修剪及形 成設備）以產生收容於殼14中且耦接至個別「^」型導線16 之分隔之晶粒U後之封裝10a之一實施例的橫截面側視 圓。圖8B展示在晶粒封裝6〇a之分離後的替代實施例該 晶粒封裝60a經形成以具有含有側向朝向側向殼側^延伸 之分層導線部分67之個別「C」型導線66。在兩個實施例 中，側向導線部分29離開側向殼側21突出，有角度的導線 冑分28延伸離開側向導線部分29,使得内部表面區域27大 冑與在側向殼側21處之—表面對準，且外部導線表面“大 體背向側向殼侧21，且經配置以收納一外部封裝間連接 器。有角度的導線部分28可含有各種各樣的有角度的、彎 ㈣其他傾斜的構形，視情況，其可含有大體上與侧向導 線P刀29垂直之構形或大體上朝向側向殼側m頃斜之構 形。在圖8B之實施例中，有角度的導線部分28大體上與側 向Up刀29垂直’且有角度的導線部分28將分層導線部 分67定位於側向導線部分29上方。此允許個別導線⑽納 133286.doc •15- 200926392 額外類型之外部封裝間連接器，諸如，金屬焊料凸塊（例 如’見圖9)。因此’晶粒封裝i〇a或6〇a可被置放於堆疊系 統（諸如’堆疊系統1〇〇)内’且可在有角度的導線部分28、 側向導線部分29或分層導線部分67處的導線16或66之暴露 的或其他可接取的表面中之任一者處，沿著晶粒封裝l〇a • 或6〇a形成連接器114。 圖9為含有至少部分由黏接層n2a_c實體耦接於一起之 個別晶粒封裝60a以及晶粒封裝6〇b-d的堆疊系統200之一 Ο 實施例之橫截面側視圖。晶粒封裝60a-d之導線66由外部 封裝間連接器214實體且電耦接於一起。在此·實施例中， 連接器214含有插入於分層導線部分67與對應的晶粒封裝 上之側向導線部分29之間的金屬焊料凸塊。個別晶粒封裝 60之導線66相互垂直分隔開一跨越距離t3之間隙68，距離 h可大約為60微米或更小。個別連接器214橋接間隙68且沿 著分層導線部分67以及有角度的導線部分28及侧向導線部 分29附著至外部導線表面25之部分。類似於堆疊系統 ® 100，堆疊系統200可藉由一方法形成，該方法含有堆疊晶 粒封裝60a-d使得晶粒封裝6〇a-d之導線對準且在晶粒封裝 • 60a_d之個別導線66處形成連接器214。可使用金屬焊料凸 塊製程來形成連接器214，該製程含有形成附著至外部導 線表面25之部分的金屬焊料點。如所展示，焊接點可經組 態以沿著有角度的導線部分28附著至外部導線表面25，使 得連接器214經定位於個別晶粒封裝60a_d之間，且自側向 導線部分29向外突出。在其他實施例中，連接器214可進 133286.doc -16 - 200926392 一步搞接至内部導線表面26之部分。 圖10為展示含有具有對應的微電子晶粒74&<之微電子 晶粒封裝72a-c的堆疊系統3〇〇之一實施例之橫截面侧視 圖。晶粒封裝72a-c共用一共同的側向尺寸山，但微電子晶 粒74a-c具有不同的側向尺寸旬、1及幻（不按彼次序p在 一實施例中，堆疊系統3〇〇可為一記憶體模組，其含有在 晶粒7乜處之一界面電路、在晶粒74b處之一控制電路及在 晶粒74c處之一記憶體。因為晶粒封裝72a_c共用共同的側 Ο 向尺寸di ’所以藉由堆疊較佳的晶粒封裝或交換某些晶粒 封裝’可創造出大量不同類型之堆疊系統。舉例而言，藉 由使用收容於具有側向尺寸之晶粒封裝中的較小的基於 磁阻RAM (MRAM)之晶粒，可組裝基於dram之記憶體模 組之一替代實施例。因此’可用基於MRAM之晶粒封裝替 換基於DRAM之晶粒封裝72b-c。 圖11為展示含有由介電間隔層84a-d分隔且具有分別由 第一連接器41 4a及第二連接器414b耦接於一起之第一金屬 ❹ 導線86a-d及第二金屬導線88a-d的微電子晶粒封裝82a-d之 堆疊系統400之一實施例之橫截面側視圖β在此視圖中， 間隔層84a含有對應的金屬跡線90a-b，間隔層84c含有對應 的金屬跡線91 a-b ’間隔層84d含有一單一金屬跡線92，但 間隔層84b不具有沿著第二封裝82b之此視圖的任何對應的 金屬跡線（亦即，晶粒封裝82a-d在其他橫截面圖中可具有 不同金屬跡線配置’使得第二封裝82b不具有沿著說明之 橫戴面的金屬跡線）。第一連接器414a經施加於第一導線 133286.doc •17· 200926392 86a-d上以選擇性地電耦接第一封裝82a、第三封袭82c及第 四封裝82d ;及第二連接器414b經施加於第二導線88&_(1上 以選擇性地電搞接第一封裝82a及第三封裝82c。因此，晶 粒封襞82d之一側及晶粒封裝82b之兩側與連接器4Ua b電 隔離。堆疊晶粒封裝82a-d之製程可與參看圖}及圖9描述 之製程相同。形成晶粒封裝82a_d之製程可類似於參看圖 • 2A至圖8B描述之製造方法，但替代將金屬跡線連接至每 一金屬導線，已省略了個別金屬跡線與導線的耦接。 ® 可進行對上述堆疊系統之許多其他類型之變化（含有與 此等系統相關的某些特徵之各種組合）。舉例而言，代替 結合襯墊連接"^圖丨及圖9)，線結合可將一堆疊系統電耦 接至一插入式基板。在一些實施例中，可省略插入於堆疊 封裝之間的黏接層。舉例而言，外部封裝間連接器單獨地 可用以藉由6»時地夾緊封裝直至施加金屬蟬料且形成連接 器而將個別晶粒封裝固持於一起。在其他實施例中，連接 $可經組態以藉由將金屬焊料施加於有限數目個導線上而 ㈣性地路由導線之個別集合。未經烊接之導線保持與堆 4系統電隔離。在一具體實施例中，堆疊系統含有收容同 —類型之晶粒的晶粒封裝。舉例而言，堆疊系統可為記憶 體，諸如，靜態動態存取記憶體(SRAM)。在此實施例 中個另J導線將提供對收容於個別晶粒封裝中之個別 SRAM晶粒之字綠；5 _ 及位兀線存取。因此，累積的個別 SRAM晶粒形成大的qD Λ χ | 的SRAM ’相對於相同大小之習知 SRAM ’其具有減小之佔 Λ H占據面積。同樣，堆疊系統可含有 133286.doc 200926392 具有比說明之實施例中呈現的封裝多或少之封裝之任何數 目個個別微電子晶粒封裝。 以上參看圖1至圖11描述的微電子裝置中之任一者可被 併入於大量較大或較複雜的系統490中之任一者内，系统 490之一代表示意性地展示於圖12中。系統490可含有一處 理器491、一記憶體492(例如，SRAM、DRAM '快閃記.降 • 體或其他記憶體裝置）、輸入/輸出裝置493或其他子系統或 組件494。圖12中展示之組件中的任一者中可含有微電子 〇 裝置。所得系統490可執行廣泛的各種各樣之計算、處 理、儲存、感測器、成像或其他功能中之任一者。因此， 代表性系統490含有（但不限於）電腦或其他資料處理器，例 如，桌上型電腦、膝上型電腦、網際網路器具、手持式裝 置（例如，掌上型電腦、可佩帶式電腦、蜂巢式或行動電 話、個人數位助理）、多處理器系統、基於處理器或可程 式之消費者電子器件 '網路電腦及小型電腦。其他代表性 纟統490 3有相機、光或其他輕射感測器、伺服器及相關 舰器子系統、顯示器裝置或記憶體裝置。在此等系統 中’個別晶粒可含有成像器陣列，諸如，⑽⑽成像器。 彡統490之組件可收容於一單一單元中或分布於多個互連 巧元上，例如’經由—通信網路。組件可因此含有本端 或遠端。己隐體儲存裝置及廣泛的各種各樣之電腦可讀媒體 中之任何者。 自前述内容，將瞭解，為了說明之目的，本文中已描述 了八體實施例，但尚未^細展示或描述熟知結構及功能以 133286.doc 200926392 2免不必要地使前述實施例之描述_ 許的情況下，單數戋葙赵淋扭★ π ^ 〇 亦可分別包含複數或單數術 二此外，除非詞「或」明確限制為僅意謂一單一項而排 於兩項或更多項之列表中的其它項，否則在此列表中 或」之使用應解釋為含有⑷該列表中任何單-項’⑻ 該列表中所有項’或⑷該列表中之項的任何組合。另外， 術語：包含」I包括性的，且遍及全文使用以意謂含有至 ❹
少該⑷所述特徵，使得並不排除任何更大數量之相同特 徵及/或額外類型之其他特徵。亦應瞭解，為了說明之目 的，本文中已描述了具體實施例，但在不脫離本發明之情 況下，可進行各種修改。舉例而言，&了其他實施例之元 件以外或代替其他實施例之元#，一實施例之許多元件可 與其他實施例相組合。因此，除如由隨附申請專利範圍所 限制之外，本發明不受限制。 【圖式簡單說明】 圖1為含有根據本揭示案之一實施例組態且堆疊的微電 子晶粒封裝之一堆疊系統之橫截面側視圖。 圖2Α為含有一框架、一釋放層及一支撐基板的微電子組 合之俯視圖。 圖2Β及圖2C為圖2Α之組合之部分分解橫截面側視圖。 圖3Α為圖2Α之具有定位於框架之開口中的微電子晶粒 之組合之俯視圖。 圖3Β及圖3C為圖3Α之組合之橫截面側視圖。 圖4Α為圖3Α之經密封於介電材料中的組合之俯視圖。 -20- 133286.doc 200926392 圖4B及圖4C為圖4A之組合之橫截面侧視圊。 圖5A及圖5B為在移除支撑基板後的圖4A之組合之橫截 面側視及仰視圖。 圖6為在形成一間隔層後的圖5A及圖5B之組合之橫載面 側視圖。 圖7為在介電材料之部分移除後的圖6A之組合之橫截面 側視圖。 圖8A為在分離及金屬導線之形成後的圖7之組合之橫截 面側視圖。 圖8B為根據本揭示案之一替代實施例的在分離及金屬導 線之形成後的圖7之組合之橫截面側視圖。 圖9為含有根據本揭示案之一替代實施例組態且堆養的 微電子晶粒封裝之一堆疊系統之橫截面側視圖。 圖10為根據本揭示案之一實施例的具有含有不同大小之 晶粒之微電子晶粒封裝的一堆疊系統之橫截面側視圖。 圖11為根據本揭示案之一實施例的具有用於選擇性地電 耦接個別微電子晶粒封裝之金屬跡線的一堆疊系統之橫截 面側視圖。 圖12為其中可併入有微電子晶粒封裝及堆疊系統之一系 統之示意性說明。 【主要元件符號說明】 10a 晶粒封裝 10b 晶粒封裝 10c 晶粒封裝 133286.doc -21 · 200926392
10d 晶粒封裝 12 晶粒 14 殼 16 導線 21 侧向殼側 22 頂部殼側 23 底部殼側 25 外部導線表面 26 内部導線表面 27 内部表面區域 28 有角度的導線部分 29 側向導線部分 32 跡線 34 介電間隔層 36 封裝結合襯墊 40 組合 41 框架 42 導線部分 43 開口 44 切割道 45 釋放層 47 支撐基板 48 間隙 50 介電材料 133286.doc -22- 200926392
52 晶粒之底側表面 54 導線部分之底侧表面 56 結合襯墊 60a 晶粒封裝 60b 晶粒封裝 60c 晶粒封裝 60d 晶粒封裝 66 導線 67 分層導線部分 68 間隙 72a 晶粒封裝 72b 晶粒封裝 72c 晶粒封裝 74a 晶粒 74b 晶粒 74c 晶粒 82a 晶粒封裝 82b 晶粒封裝 82c 晶粒封裝 82d 晶粒封裝 84a 間隔層 84b 間隔層 84c 間隔層 84d 間隔層 133286.doc -23- 200926392 ❹ 86a 第一導線 86b 第一導線 86c 第一導線 86d 第一導線 88a 第二導線 88b 第二導線 88c 第二導線 88d 第二導線 90a 金屬跡線 90b 金屬跡線 91a 金屬跡線 91b 金屬跡線 92 金屬跡線 100 堆疊系統 102 插入式基板 104 金屬凸塊襯墊 106 結合襯墊連接 112a 黏接層 112b 黏接層 112c 黏接層 114 連接器 214 連接器 300 堆疊系統 400 堆疊系統 133286.doc -24- 200926392 414a 連接器 414b 連接器 490 系統 491 處理器 492 記憶體 493 輸入/輸出裝置 494 其他子系統或組件 di 側向尺寸 (I2 側向尺寸 <^3 側向尺寸 d4 側向尺寸 Si 間隔距離 ti 厚度 t2 厚度 t3 距離 133286.doc -25-

Claims (1)

  1. 200926392 十、申請專利範圍： 1· 一種微電子晶粒封裝之堆疊系統，其包含： 一第一晶粒封裝，其具有一底側且含有—第—微電子 晶粒、至少部分覆蓋該第一晶粒之一第一介電殼，及耦 接至該第-晶粒且具有一第一外表面之個别第一金屬導 線； 一第二晶粒封裝，其具有一附著至該第—封裝之該底 “之頂側，且含有一第二微電子晶粒、至少 ❹ :::晶粒且具有-第二側面之-第二介電殼，及論 主孩第二晶粒且具有一篦-冰 弟一外表面及一大體面向該側面 ::表面區域之個別第二金屬導線’其令該等個別第二 、’至少大體與該等個別第一導線對準，且至少部分朝 向該第一封裝突出；及 八1:封裝間連接器’其將個別第-外表面之-第-部 ':個別第二外表面之一第二部分搞接。 ❹ 形且^項1之堆叠系統’其中該等個別第二導線具有- L 實體接觸對應的個別第一導線。 形且1 = 1之堆叠系統’其中該等個別第二導線具有-c 4.如請：Γ朝向該第二殼之該側面突出之分層部分。 該第二《to 1之堆叠系統其中該等個別第二導線柄接至 〜殼之一底側。 進—步^ 1之堆叠系統’其_該第二晶粒封裝之一底側 之封裝社:相接至與一插入式基板相關之金屬凸塊襯塾 133286.doc 200926392 6. 7. 8. ❹ 9. 10.11. 12. 如月求項1之堆疊系統’其中該等連接器自該等第一外 該第°卩分及該等第二外表面之該第二部分側向 向外突出。 如凊求項6之堆疊系統，其中該等連接器進一步朝向該 第一殼之該側面而在該第一晶粒封裝與該第二晶粒封裝 之間延伸。 如"青求項1之堆疊系統’其中該第二殼之該側面具有一 斜構形’且該等導線之該等内表面區域與該側面間隔 開一間隙。 如β求項1之堆疊系統，其中該第二晶粒封裝之該等個 別第二導線以若干垂直間隙與該第一晶粒封裝之對應的 個別第一導線分隔開，且其中個別連接器包含橋接對應 之成對之第一導線與第二導線之間之該等垂直間隙的焊料鍵接。 如請求項1之堆疊系統，其中該第一晶粒具有一第一側 向尺寸，及該第一晶粒具有一與該第一側向尺寸不同之 第二側向尺寸，且其中該第一殼及該第二殼具有相等的 側向尺寸。 一種計算系統，其包含一處理器、一記憶體及一輸入/輸 出裝置中之至少一者，其中該計算系統含有如請求項J 之堆疊系統。 一種微電子晶粒封裝之堆疊系統，其包含： 一第一微電子晶粒封裝，其含有一第一介電殼，該第 "電殼具有一第一底側及附著至該第一底側之第—么 133286.doc -2 - 200926392 屬導線 一第二微電子晶粒封裝，其附著 王减第一晶粒封裝， 且其含有一第二介電殼，該第二介 ;丨電殼具有一側面、一 第二底側及耦接至該第二底側之第_ 中一金屬導線，其中個 別第二導線含有-遠離該侧面突出之側向部分、 及-自該彎曲朝向-對應之個別第_導線突 的部分；及 月度 〇 ❹ 金屬焊料連接器，其附著至該等個別第一導線及該等 第二導線之個別有角度之部分之—表面。 13. 如睛求項12之堆疊系統，其巾& & 丹甲該有角度的部分大體上朝 向該第二殼之該侧面向内傾斜 只斜且其中該等第二導線直 接接觸對應的第一導線。 14. 如請求項12之堆疊系統，其中 畀中個別金屬焊料連接器將個 別有角度的部分附著至—對應之第—導線之一表面。 15. —種微電子裝置之堆疊系統，其包含： 一第一微電子裝置，其表古 、具有一第一底側及耦接至該第 一底側之第一金屬導線； 一第二微電子裝置，其 ^ s ^ 具具有—側面、一第二底側及耦 接至該第二底側之第-全凰 ^ 弟一金屬導線，該等第二導線含有一 遠離該側面側向突出之你丨A h、 犬出之側向部分、一朝向該側面側向突 出之分層部分，及—將缔八 將该刀層部分定位於該側向部分上 之在該側向部分與該分a邱 "刀增〇P分之間之有角度的部分；及 金屬焊料凸塊，其虚於彳 、處於個別第一導線及該等第二導線 之個別分層部分之間。 133286.doc 200926392 16.如請求項15之堆疊系統，苴 ，、中該等金屬焊料凸塊進一步 在該有角度之部分之大體背向該第二殼之該側面之一表 面處，附著至該第二微電子裝置之該等個別第二導線。 I7·如請求項15之堆疊系統，其 、甲该刀層部分與一對應之第 一導線分隔開一高達60微米之垂直距離。 18. 如請求項15之堆疊系統，其 丹甲D亥有角度的部分大體上與 該侧向部分垂直。 19. 一種微電子晶粒封裝，其包含：
    一微電子晶粒； -介電殼’其至少部分㈣該晶粒且具有—底側；及 複數個個別金屬接觸，其勒接至該晶粒及該殼之該底 側’且含有遠離該殼突出之一側向部分、遠離該底侧· 曲之-f曲部及自該彎曲部遠離該殼之該底側延伸之一 有角度的部分，該有角度的部分具有—面向該殼表面之 第一表面及一大體背向該殼表面之第二表面且其中該 第二表面經組態以接收一外部封裝間連接器。 20·如請求項19之 屬焊料線及一 微電子晶粒封裝，其中該連接器包含一金 金屬焊料凸塊中之至少一者。 21. 如請求項20之微電子晶粒封裝，其中個別接觸具有一匕 形’且該第一表面及該第二表面中之至少—者經組態為 濕的表面’以附著至該連接器。 22. 如請求項20之微電子晶粒封裝，其中個別接觸具有_ c 形，該C形含有一自該有角度的部分朝向該殼表面向内 延伸的分層部分，該分層部分具有一第三表面其大體 133286.doc -4- 200926392 背向該側向部分， 器附著在一起。 且經組態為一濕的表面 以與該連接 Ο
    23.- 在具有一含有一第二底側及_側面之第二介電殼之— 第二晶粒封裝的頂部上’堆疊具有一含有一第一底側之 第一介電殼之一第一晶粒封裝； 將輕接至該第一晶粒封裝之兮笛 玎珉义該第一底侧的第一金屬導 線與耦接至該第二晶粒封裝之钤笛_ 了垠炙該第二底側的第二金屬实 線對準；及 4 形成附著至個別第-導線之一第一部分及附著至與該 第二殼之該側面間隔開且朝向該第—封裝突出之個別第 二導線之一第二部分的個別外部封裝間連接器。 24.如請求項23之方法，進一步包含壓縮該等第二金屬導 線，使得該等第三導線朝向該第二殼之該側面彎曲。 25·如請求項23之方法，其中形成該等連接器包含將金屬焊 料潤濕至該等㈣第-導線之該第一部分及該等個別第 二導線之該第二部分。 26·如請求項25之方法，進一步包含將該金屬焊料潤濕至該 等個別第二導線之内部及外部表面部分。 27. 如請求項23之方法，其中該等個別第二導線包含一[ 形，且其中該第二部分含有該等個別第二導線之一有角 度的部分。 28. 如請求項23之方法，其中該等個別第二導線包含一 c 形，且其中該第二部分進一步含有—朝向該第二殼之該 133286.doc 200926392 側面突出的分層。 29. 如請求項28之方法，其中形成該等連接器包含將金屬焊 料凸塊潤濕至該等個別第一導線之該第一部分及該等個 別第二導線之該第二部分。 30. 如請求項23之方法，進一步包含將該第二晶粒封裝之封 裝結合襯墊耦接至與一插入式基板相關的金屬凸塊襯 塾0 31. 種製造一微電子晶粒封裝之方法，該方法包含： 〇 形成一至少部分密封一微電子晶粒且含有一底側及— 側面之介電殼；及 形成具有一側向部分及一有角度之部分之個別金屬接 觸’該側向部分耦接至該殼之該底側且遠離該殼之該側 面突出’該有角度之部分與該殼之該側面間隔開且遠離 該側向部分延伸，使得該有角度之部分之一内表面面向 該殼之該側面，且其中該有角度之部分經組態以潤濕至 一外部封裝間金屬焊料連接器。 ® 32.如請求項31之方法，進一步包含在該介電殼之該底側處 开> 成一介電間隔層，其中該間隔層含有將該晶粒電耦接 至個別接觸之金屬跡線。 33. 如請求項31之方法，其中該等金屬跡線經選擇性地路由 以用於將該等接觸之一部分耦接至該晶粒。 34. 如請求項3丨之方法，其中形成該等個別金屬接觸進一步 包含形成一自該有角度之部分向内朝向該殼之該側面延 伸的分層部分，其中該分層部分經組態以潤濕至該連接 133286.doc • 6 · 200926392 器。 3 5.如請求項31之方法，其中該等金屬接觸之該等有角度的 部分與該殼之該側面並列。
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