TW200905764A - Multi-chip stack structure having silicon channel and method for fabricating the same - Google Patents

Multi-chip stack structure having silicon channel and method for fabricating the same Download PDF

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Publication number
TW200905764A
TW200905764A TW096127941A TW96127941A TW200905764A TW 200905764 A TW200905764 A TW 200905764A TW 096127941 A TW096127941 A TW 096127941A TW 96127941 A TW96127941 A TW 96127941A TW 200905764 A TW200905764 A TW 200905764A
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Taiwan
Prior art keywords
wafer
channel
metal
insulating material
electrically connected
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TW096127941A
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English (en)
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TWI335059B (en
Inventor
Cheng-Chiang Chiang
Chien-Ping Huang
Chin-Huang Chang
Chi-Hsin Chiu
Jung-Pin Huang
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Siliconware Precision Industries Co Ltd
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Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW096127941A priority Critical patent/TWI335059B/zh
Priority to US12/220,995 priority patent/US20090032928A1/en
Publication of TW200905764A publication Critical patent/TW200905764A/zh
Application granted granted Critical
Publication of TWI335059B publication Critical patent/TWI335059B/zh
Priority to US13/151,823 priority patent/US20110227226A1/en

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    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
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    • H01L2225/06503—Stacked arrangements of devices
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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200905764 九、發明說明： 【發明所屬之技術領域】 “t發明係有關於—種半導體裝置及其製法，尤指-種 夕B日片利用矽通道堆疊之結構及其製法。 【先前技術】 '網路 '及電腦等各式可攜式（Portable) 及〃、周邊產ηα輕薄紐小之趨勢的日益重要，且該等電 子產品係朝多功能及高性能的方向發展，以滿足半導體封 ^ ^ # ^Integration)^ m ^ ,t (Miniaturization) ^ ^ ^而求_i_為求提升單一帛導體封裳件之性能⑽㈣盘容 f(CaPaeity)以符合電子產品小型化、大容量與高速化；趨 勢’習知係以半導體封裳件多晶片模組化（Mum 廳她；MCM)的形式呈現，以在單—封裝件之基板上接 置至少二個以上之晶片。 、，習知多晶片模組化之半導體封裝件係在—基板上以水 t平間隔方式排列多數晶片，並透過銲線而電性連接至該基 板，此種多晶片模組化之半導體封裝件主要缺點在於，^ 避免晶片間之導線誤觸，須以H隔來料各該晶 片，故若需黏接多數之晶片則需於基板上佈設大面積的^ 片接置區域（Die Attachment Area)以容設所需數量之^ 片，此舉將造成基板使用面積及製程成本之增加。里曰曰 另外美國專利第6,538,331號案則揭露以遇曰 / ry , , 且日日乃 (Stacked)將第一晶片及第二晶片疊接於基板上，同時各气 疊接晶片係相對下層晶片偏位（off_set) 一段距離，以=便= 110424 5 200905764 第一及第二晶片分別打設銲線至該基板。 •節省述以水平間隔方式排列多晶片之技術 須利用恤術電性連接晶片及基 ΐ致ΐ;二Γ板間電性連接品質易受銲線之 Γ:】：：同時由於該些晶片於堆疊時須偏移-段距 離且加上在干線設置空間之影塑，π雈 面積過大而無法容納更多晶片:成晶片堆疊 馨於=述問題，請參閱第“ 1(}圖，美國專利 S.K ，61及5,202,754揭露一種利用石夕通道（Th酬gh rn Via，Ts v)技術以供複數半導體晶片垂直堆疊且相 互电性連接之結構及製法。 其製法主要係提供具相對第，u…二表面 ^弟—^圓lla，該第一晶圓lla包含有複數第一晶片 、、5，其中該第一表面111形成有複數孔洞Π0，並於該孔 洞U0中形成金屬柱13，以構成矽通道（TSV)結構，及於 =金屬桎13外露端形成銲墊131，以將該第一晶圓第 一表面+U1透過膠黏層141而黏置於一如玻璃之載板151 。俾藉由該載板151提供製程所需之支撐強度（如第1A 1 圖1所不）’利用研磨作業，對該第一晶圓lu之第二表面 112+進行薄化，以外露出該金屬柱13(如第1B圖所示）；於 外路出該第二表面112之金屬柱13上形成銲墊132，以供 f 形成有石夕通道之具複數第二晶片12之第二晶圓12a 藉由其矽通道之金屬柱16垂直接置並電性連接於該 a之弟—表面Π2上（如第ic圖所示）；接著重複前 110424 6 200905764 处衣程’研磨薄化該具複數第二晶片12之第：晶圓m， 以外露出該石夕通道之金屬柱16，及於該金屬柱以外露端 形成知墊136(如第1D圖所示）；後續為供第—及 叩2與外部裝置電性連接，需於該第—晶圓之第=面 植设後數銲球，此時即需再利用另—如麵之載板Μ以 透過_ 142而將該第一及第二晶圓ιΐΜ2&黏置其 ΘΒ 上，且外露出該第-晶目lla之第一表面ιη(如第π圖 所不)，俾於該第一晶圓第一表面lu之銲墊i3i上植設銲 球17(如帛1F圖所示）；接著切割該堆疊之第—及第二晶 圓’以形成複數個相互垂直堆疊之第—及第二晶片HU， 再經拾取及透過銲球17而電性連接至基板ΐδ，以形成多 且片模組化之半導體封裝件（如第1G圖所示 ，、、'、而於前述之製程中，須額外使用複數之載板 15U52,且將第一及第二晶圓Ua，12a多次反覆黏置於載 板⑸阳上，惟此不僅增加製程成本，亦造成製程複雜 性的提* ’再者，若所使用之膠黏層141,142為例如環氧 樹脂（epoxy)之高分子材料時，於形成該銲墊i3i,i36所進 行之濺鍍（SpUttering)及後續之濕式蝕刻（strip)作業，極易 造成製程上之污染而致生產不易。 是以’如何解決上述習知多晶片模組化半導體裝裝件 於製程中所產生之問題’並開發—種不須使用载板及膠黏 層之多晶片堆疊結構及其製法，以簡化製程及降低成本， 及避免因使用高分子膠黏層而發生污染問題，實為目前亟 欲解決的課題。 Π0424 7 200905764 ’【發明内容j 鑒於以上所述先前技術之缺點，本發 提供一種於製寇中兀頌枯 目的在於 m:: 及膠黏層之具石夕通道之多 日日片堆豐結構及其製法。 、、炙夕 本發明之另一目的在於提供一種製程簡 ，、矽通道之多晶片堆疊結構及其製法。 -成本之 本發明之再一目的在於提供一種具 疊結構及苴萝法，碟备 八 、之夕晶片堆 題。一〆去2^因使用高分子谬黏層而發生污染問 曰片揭及其他目的，本發明揭露一種具石夕通道之多 曰日片堆豐結構之製法，係包括 =之夕 片之晶圓，該晶圓及第一晶片=包3有複數第-晶 面，其中該第一晶片之第一矣有相對之第-及第二表 洞形成有金屬柱及 1面形成有複數孔洞，且該孔 該第一晶月之笛_ j以構成矽通道（TSV)結構；於各 該第-.==?;以及將至少-第二晶片堆叠於 屬柱。 至外路出该凹槽之該矽通道之金 該製法復包括：於該第一曰 晶片之絕緣材料；平整化二=之凹槽中填充包覆第二 該第一晶片之Μ _主 〜巴、，材料，以令該絕緣材料與 片之昂一表面齊平；於該第曰}4筮一矣； 墊上植設導電亓杜.料# /乐一日日片弟表面之銲 晶片；以及將3有==切割’以分離各該第-而接置並電性連接至:晶片透過該導電元件 110424 8 200905764 另外，《亥第一晶片中復形成有石夕通道（tsv)，以 .續於該第二晶片上堆疊及電性連接第三晶片，亦 於該第-晶片之第一表面之銲塾上堆疊第四晶片，藉由曰 片數目之增加，以強化整體結構之電性功能。 8 Ba 透過前述製法，本發明復揭示一種具石夕通道 堆疊結構，係包括♦•第一晶片，其具有相對之第一及；二 成有複數孔洞，且於該孔洞形成有二 成石夕通道（TSV)結構，該第二表面形成 有V㈤槽以外露出該石夕通道之金屬柱；以及至 二晶片，係堆疊於該繁一 S y L、，而 槽之料叙^柱片上亚接料露出該凹 埴充多晶片堆疊結構復包括：絕緣材料，係 係植設於該第-晶片第-表面之銲塾；以及晶 係供堆豐之第二晶片及第一晶片透 ： 上並形成電性連接。 1千而接置其 構復中’該具石夕通道之多晶片堆疊結 曰 有弟二曰曰片，係堆疊於該第二晶片上，且該 日日片中形成有矽通道（TS ν)， a x 一 接。於又—者从， 於/、邊弟一日日片電性連 片，= 多晶#堆4結構復包括有第四晶 h接置亚電性連接至該第—晶片第一表面之辉墊 =:本發明之具料道之多晶片堆疊結構及 :主要係在具複數第一晶片之晶圓第一表二 孔洞’且於該孔洞形成金屬柱及銲墊，以構成^= 數 110424 9 200905764 日日/}之第 丹％、琢第 金屬柱之凹槽，以將至少—成，至乂外露出該矽通道 且容置於該凹槽中，並電性連：：片:®於該第-晶片上 之金屬柱，以形成第一及第二s 路出該凹槽之矽通道 於該凹槽中填充包覆f _ θ U之垂直维叠，接著即可 緣材料，以令其與該;：c並平整化該絕 -晶片第-表面之銲墊上 二面齊平，再於該第 藉以將堆疊有第二晶片之;：r片 =進行晶圓切割， 並電性連接至晶片承載件上，元件而接置 之具複數第一晶片之s圓柞& 4』利用該未經整體薄化 免習知利用石夕通道結構垂直 =载錢，避 置於B H s莽从 F且^數日日片及將該些晶片接 製程“ it時須多MS載板及膠黏層’所產生的 繁雜成本南以及可能遭受污染等問題。 【實施方式】 以下係藉由特定的具體實施例說明本創作之實施 式1 Μ技術領域中具有通常知識者可由本說明書^示 ^内谷輕易地瞭解本創作之其他優點與功效。 實施例 請參閱第2A至2F圖，係為本發明之具矽通道之多晶 片堆豐結構及其製法第一實施例之示意圖。 。如第2 A圖所示，提供一包含有複數第一晶片2丨之晶 圓21a’該晶圓2la及各該第一晶片21具有相對之第一表 面211及第二表面212，其中該第一晶片21第一表面212 形成有複數孔洞210，以對應該孔洞210處形成金屬柱23 110424 10 200905764 及銲墊231，而構成矽通道（TSV)結構。 该石夕通道之孔洞21 0與金屬柱2 3間係設有如二氧化發 或氮化矽之絕緣層23”，且該絕緣層23”與金屬柱23間係 设有如鎳之阻障層23 ’’而該金屬柱23之材質係例如為 銅、金、链等。 如第2B圖所示，對該第一晶片21之第二表面212利 用如深層钱刻（Deep Reactive Ion Etching, DRIE)之方式钱 刻形成至少一凹槽2120，且令該矽通道之金屬柱23顯露
於該凹槽2120底部，其中該金屬柱23係可凸出於該凹槽 2120底部》 S 晶片22堆疊於該第一 並電性連接至外露出 如第2C圖所示，將至少一第二 晶片21上且容置於該凹槽2120中， 該凹槽2120之石夕通道之金屬柱23。 如第2D及2E圖所示，於該凹槽212〇中填充包覆第 二晶片22之絕緣材料25(例如為封裝膠體），接利用 磨作業以平整化該絕緣材料25，以令該絕 面與該第一晶片21之第二表面212齊平。 外表 遠第一晶片22之接置高度係可選擇小於該 曰 21之第二表面212高度，而於平整 日日片 傕兮裳-曰h π ~ 十I化该輓緣材料25後仍 曰該絕緣材料25中(如第2Ε圖所 ，Χ ^ —日日片22之接置高度係可選擇等於Κ大 於該第一晶片21之第二矣而、释等於或略大 表面212咼度，而於平整 材料25後，使該第二曰η 化該、、邑、、彖 及託，圖所示）。422外露出該絕緣材料（如第瓜 110424 13 200905764 -如第2F圖所示，於該第-晶片21之第一表面211之 -銲墊23 1上植設導電元件27，並 業以分離各該第一晶片21，及進行切割作 第二晶片22及第-晶片21透過^取作業广將堆疊之 性連接至晶片承載件28上。^几件27而接置並電 透過前述製法，本發明復揭 堆疊結構，係包括：第-晶片21，/第八石夕曰通道之多晶片 之第一表面川及第二表面212，二弟一表日日面V1具相對 孔洞210，且㈣孔、、同21m 〜弟—表面211形成有 这孔洞210形成金屬柱幻 構成矽通道結構，該第二表面212形 ，以 以外露出該料道之金屬柱23;以及至少_/二^20 係堆疊於該第一晶片21上 ^曰月22, 2】2〇切通道之金屬柱^ $接至外路出該凹槽 該具矽通道之多晶片堆疊 25，係填充於該第一曰片+ 设匕括有.絕緣材料 片比導電元件27，^=凹槽2120中且包覆第二晶 之銲墊231;以及曰：Ϊ:Γ 晶片21第-表面⑴ 及第-晶…:二載件:;物 連接。 〜電讀27而接置其上並形成電性 本發明之具矽通道之多晶片堆聂a Μ 法，主要係在具複數第日μ 片隹宜結構及其製 孔洞，且於該孔洞开成八二 圓第一表面形成有複數 再於該第-晶片之第墊，以構成石夕通道結構， 金屬枝之凹槽，以將至^形成有至少—外露出該秒通道 、v —第二晶片堆疊於該第—晶片上 130424 12 200905764 —且容置於該凹槽中，並電性連接至外露 -之金屬柱，以形成第一 μ凹槽之矽通道 ^ /入牙》—日日月之番古协田 於該凹槽中填充包覆第二晶片之絕緣材料隹豐，接著即可 緣材料，以令其與該第一晶片之第 亚平整化該絕 =晶片第-表面之銲墊上植設導電元件、及：：：再於該第 藉以將堆疊有第二晶 仃晶圓切割’ 並電性連接至晶片承載件上，俾 f 之具複數第-晶片之晶圓作為製程進行中體薄化 免習知利用石夕通道結構垂直堆疊複數晶片及將^構，避 置於晶月承載件上時須多次使用載板及 /些晶片接 雜、成本高以及可能遭受污染等問題：，所產生的 ^ —霄施例 、 請參閱第从至3〇圖，係為本發明之 片堆疊結構及其製法第二實 、之夕晶 m_ 思圖。同時為簡化太 囷不，本貫施例中對應前述相同$ 標號表示。 "次相似之兀件係採用相同 本貫施例之具㊉通道之多晶片堆疊結構及 述實施例大致相同’主要差異在於第二晶片中形 f(/SV) ’/7該第m垂直堆疊及電性連接第= :沪，俾糟由晶片堆疊數目之增加以強化整體結構之電性 如第3A圖所示，於具複數第一晶片21之晶圓仏上， 將至少-第二晶片22堆疊於該第一晶片21第二表面212 之凹槽2120中’並電性連接至外露出該凹槽212〇之第一 130424 13 200905764 晶片21矽通這之金屬柱23’其中該第二晶片22中形成有 -金屬才主223以構成石夕通道，並於該凹槽212〇中填充絕緣材 料25’且經如研磨之平整化作業而使該第二晶片22石夕通 道之金屬柱223外露出該絕緣材料25。 如第3B圖所示，利用例如濺鑛（sputtering)之方式於 外露之第U 22料道之金屬柱223上方形成銲塾 2231。 如第3C圖所示，蔣笙_曰，， 、， 、弟二日日片20接置於該第二晶片22 上，亚笔性連接至該第二晶片22之銲墊2231。 二曰茶閱第奶圖，亦可利用濺鍍方式於該第 川上形成電性連接至及，-晶片21第二表面 的線路重佈置層2232(RDT；'曰曰片22石夕通道之金屬柱223 之故端Ψ a )，並於該線路重佈置層2232 之、Ά形成有銲墊2231 置層則 銲墊2231。 乐—日日片26電性連接至該 %、 後續即可於該第一晶 並對該晶圓進4表面上植設導電元件， -、第二及第各：第—晶片，《供堆叠之第 片承載件上。 匕“導电疋件接置並電性連接至晶 110424 14 200905764 本實施例之多晶片堆疊結構及其製 致相同，主要差異在於第一晶片21之第一表二;： 並使該第四晶片24電性連接至 弟曰曰片12弟一表面211之輝塾231，俾藉由晶片堆疊數 目之增加以強化整體結構之電性功能。 以上所述之具體實施例，僅係用以例釋本發明之特點 及功效’而非用以㈣本發明之可實施㈣，在未脫離本 發明上揭之精神與技術範，下，任何運用本發明所揭示内 容而完成之等效改變及修飾，均仍應為下述之申請專利範 【圖式簡單說明】 第1Α至ig圖係為習知美國專利US5,27〇,261及 5’202,754所揭露之藉由矽通道（TSv)技術垂直堆疊複數半 導體晶片之示意圖； —第2A至2F圖係為本發明之多晶片堆疊結構及其製法 第一實施例之示意圖； 第2D’及2E’圖係為對應第2D及2E圖中第二晶片不 同向度之示意圖； ^乐3A至3D圖係為本發明之多晶片堆疊結構及其製法 第二實施例之示意圖；以及 第4圖係為本發明之多晶片堆疊結構及其製法第三實 施例之示意圖。 【主要元件符號說明】 11 第一曰 ^ 日日片 111 第一表面 15 110424 200905764 112 第二表面 110 孔洞 12 楚一曰 Η 弟一·^日乃 13,16 金屬柱 131,132,136 銲墊 141,142 膠黏層 151,152 載板 17 鲜球 18 基板 21 第一晶片 210 孔洞 211 第一表面 212 第二表面 23 金屬柱 231 鲜塾 23，， 絕緣層 23, 阻障層 2120 凹槽 22 第二晶片 223 金屬柱 2231 銲墊 2232 線路重佈置層 24 弟四晶片 25 絕緣材料 26 第三晶片 27 導電元件 28 晶片承載件 16 110424

Claims (1)

  1. 200905764 十、申請專利範圍： i種，石夕通道之多晶片堆疊結構之製法，係包括·· 提供具複數第一晶片之晶圓，該晶圓及第一晶片具 相對之第一及第二表面，該第一晶片之第一表面形成有 複數孔洞’且該孔洞處形成金屬柱及銲墊以構成矽通 道（tsv)結構； 於该第一晶片之第二表面形成至少一凹槽，且令該 矽通道之金屬柱顯露於該凹槽底部；以及 將至少一第二晶片堆疊於該第一晶片上並電性連 接至外露出該凹槽之第一晶片石夕通道之金屬柱。 2 ·如申請專利第丨項之具料道之多晶片堆疊結構之 製法，其中’該孔洞與金屬柱間復設有絕緣層，該絕緣 層與金屬柱間復設有阻障層。 ㈣2項之具料道之多晶：堆疊結構之 -法，其中，該絕緣層為二氧化石夕及氮化石夕之盆中一 二組=層為鎳，該金屬柱之材質為銅、金、紹所組 4:=圍第一通道之多晶—之 材料之凹槽中填充包覆第二晶片之絶緣 化㈣緣材料，以令該絕緣材料舆該第 之弟一表面齊平。 日日片 5.如申請專利範圍第4項之具矽通道 曰 夕晶片堆疊結構之 110424 17 200905764 製法’復包括： 於該第一晶η楚一主工 及 片弟一表面之銲墊上植設導電元件；以 對該晶圓進行㈣以㈣各該第一晶片。 •如申請專利範圍第5項之且 製法，復包括將二多晶片堆疊結構之 讀而接置並電性連接至晶片承載件上。 電 範圍第4項之具秒通道之多晶片堆疊結構之 ，该第二晶片之接置高度小於該第-晶片之 二:緣:::整化該絕緣材料後，使該第二晶 8. =其專:範:=:具:通道之多晶片堆4結構之 -晶片之第面：：接置高度等於或略大於該第 …父度’而於平整化該絕緣材料後，使 μ弟一日日片之—表面外露出該絕緣材料。 9. Π:範圍第1項之具料道之多晶片堆疊結構之 片、/、 °亥第一晶片之第一表面上接置有第四晶 i，。亚使該第四晶片電性連接至第―晶片第-表面之銲 種^石夕通運之多晶片堆疊結構之製法，係包括： 相對=具複數第一晶片之晶圓，該晶圓及第-晶片具 複數孔洞，且，孔Λ 弟一表面形成有 道（TSV)結構；處形成金屬柱及銲塾以構成石夕通 110424 18 200905764 石"、f該乐a曰片之乐二表面形成至少-凹槽，且八’ 夕通運之金屬柱顯露於該凹槽底部； ”亥 將至少一形成有矽通道（TSV)之第二晶片掩晶 第一晶片上並電性連接 蘩於該 通道之金屬柱 接至外露出該凹槽之第-晶“夕 入於相槽中填充絕緣材料，並平整化該絕緣 1第二晶牌通道之金屬柱外露出該絕緣材料V 料：第二晶片上形成電性連接至外露出該：缘材 科之第二晶片石夕通道之金屬柱的銲墊；以及 緣材 性連接：第一sa片上接置第三晶片’並使該第三晶片· 性連接至該第二晶片上之銲墊。 曰曰片电 1〇項之具秒通道之多晶片堆疊、 !孔洞與金屬柱間復設有絕緣層，：： 、’ 金屬柱間復設有阻障層。 ° 巴 項之具料道之多晶片堆疊結構 衣去’ /、中’該絕、㈣為二氧切及氮切之 t，該阻障層為鎳，該金屬柱之材質為銅、金、二 群組之一者。 主鋁所組 =申請專利範圍第10項之具石夕通道 之製法，復包括： 隹且，、，口構 及於該第一晶片之第-表面銲墊上植設導電元件;以 對該晶圓進行切割以分離各該第一曰片 如申料利範㈣13狀具料道之^片堆疊結構 110424 19 200905764 之製法’復包括將堆疊之第一曰 P ^ ^ ^ ^ ^ . 日曰片、第二晶片及第三晶 .片透過仏電兀件而接置並電性連接 15.如申請專利範圍第1〇項之具矽通道之： 。 之製法，：M:中，誇_ 夕日日片隹$結構 一曰1乐二日日片上之銲墊係直接形成於該第 一日日片矽通道之金屬柱上方。 矛 16:Π專：f圍第10項之具梦通道之多晶片_構 之製法，其中，該篦-曰 ^门*且、、D構 層师)而連接至曰片片上：銲塾係透過線路重佈置 17心由;…， 晶片矽通道之金屬柱。 17·如申叫專利範圍第1〇 之製法，其中，該笛石夕通道之多晶片堆疊結構 成。 μ弟一曰曰片上之銲墊係透過濺鍍方式形 種:石夕通逼之多晶片堆疊結構，係： 該第 該第-表面形成有：1晶片具相對之第一及第二表面， r ^ 有複數孔洞，且該孔洞處形成有金屬 = ::::通道⑽跡 卜路出5玄矽通道之金屬桎；以及 至少—第-日 接至外霖出 > 片仏堆宜於δ玄第一晶片上並電性連 ::外路出該凹槽之矽通道之金屬柱。 19.=申請專利範圍第18項之具料 2。：:叫絕緣材料，係填充於該第一 構，其中石夕通道之多晶片堆疊結 該第一晶片之」#經過平整化，以令該絕緣材料與 之弟二表面齊平。 21.如申請專利範 圍弟20項之具矽通道之多晶片堆疊結 第一晶片 110424 20 200905764 '構，其中，該第二θμ _ 一 曰日片之尚度小於該第一晶片之第二表 J 面南度，而於平够彳卜外π 化為、纟巴緣材料後使該第二晶片包覆於 該絕緣材料中。 22. 如申請專利範圍笫 ^ ^ 弟20項之具矽通道之多晶片堆疊結 構’其中’該第二晶Η十古ώ〜 ^ 片之同度寺於或略大於該第一晶片 之弟' —表面高度，而~1· 曰 而於平整化該絕緣材料後，使該第二 日日片之一表面外露出該絕緣材料。 23. 如申請專利範圍第1 8項之具矽通道之多晶片堆疊結 構，復包括有導雷亓I H .θ,, 牛，仏植設於該第一晶片第一表面 之銲堅。 24. 如申請專利範圍第 ^^ 、 貝之具石夕通逼之多晶片堆疊結 構，设包括有晶片承载件，係供堆疊之第二 晶片透過該導電元件而接置 + 曰 接置亚私性連接至該晶片承載 件0 25. 如申請專利範圍第18項之且石々、s、、， ^ ^ ^ 貞之具矽通運之多晶片堆疊結 命八屈二曰日— 玉屬柱間復以有絕緣層，該絕緣層 與金屬柱間後設有阻障層。 26. 如申請專利範圍第25項之具矽 ,*t ^ , . 、逼之多晶片堆疊結 構、、中，該絕緣層為二氧切及氮切之其中一者， 5亥阻P早層為鎳’該金屬柱之材質為 之一者。 可貝為铜、金、鋁所組群組 27. 如申請專利範圍第18項之具矽诵、苦 < 之多晶片堆疊結 構，其中，該弟一晶片第一表面上拉 .._ ^ 接置有第四晶片，並 使该弟四晶片電性連接至該第一晶 曰曰片弟一表面之銲墊。 110424 21 200905764 28. —種具矽通道之 曰 夕日日片堆豎結構，係包括： 辞一 曰 5玄第—晶片具相對之第一及望-夹而 該弟-表面形成有複數及弟-表面， 柱及銲墊以構成禧孔洞處形成有金屬 偁成矽通暹（tsv)結構，該第_ 至少外露出該發通道之金屬表面… 該第一晶片上並：夕通道(TSV)之第二晶片，係堆疊於 功、s 片並電性連接至外露出該凹梓之兹曰μ 矽通道之金屬柱； X凹槽之弟一晶片 絕緣材料，係於該凹槽中，且 之金屬柱外I ώ 7 罘一晶片矽通道 Γ路出該絕緣材料； 銲墊，係形成於該第二晶片 該絕緣材料之第_ a μ 月上且电性連接至外露出 晶片料道之金屬柱；以及 乐一日日片，係接置於 s 該第二晶片上之銲墊。一片上，並電性連接至 2 9.如申請專利 構，苴中，令 、之具矽通道之多晶片堆疊結 :甲該孔洞與金屬柱間復設有絕 與金屬柱間復設有阻障層。 巴緣I該絕緣層 3〇.=申請專利範圍第29項之具石夕通道 士 構，其中，#r @ 夕日日片堆f口 亨心L 層為二氧切及氮切之其中-者， 之一者。 材貝為銅、金、鋁所组群組 31.如申請專利範圍 構，復包括有導/元丰^之具石夕通道之多晶片續疊結 面銲塾上。’兀件，係植設於該第-晶片之第-表 U 0424 22 200905764 32·如申請專利範圍窠 姐 卑31項之具石夕通道之多晶月摊晶壯 構’復包括有晶片备备扯^ 夕日日月堆玄，，.口 三晶片透過該導恭罘 弟一及弟 載件上。 包凡件而接置亚電性連接至該晶片承 ㈣範圍第28項之具料道之多晶片堆疊結 構其中，该第二晶片上之銲塾係直接形成於該第二晶 片之矽通道之金屬柱上方。 34.如申請專利範圍第28社具梦通道之多晶片堆疊結 構，其中，該第二晶片上之銲墊係透過線路重佈置層 (RDL)而連接至該第二晶片之矽通道之金屬柱。 110424 23
TW096127941A 2007-07-31 2007-07-31 Multi-chip stack structure having silicon channel and method for fabricating the same TWI335059B (en)

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