TW200903588A - Align mark, semiconductor chip including the same, semiconductor package including the chip and methods of fabricating the same - Google Patents

Align mark, semiconductor chip including the same, semiconductor package including the chip and methods of fabricating the same Download PDF

Info

Publication number
TW200903588A
TW200903588A TW97117550A TW97117550A TW200903588A TW 200903588 A TW200903588 A TW 200903588A TW 97117550 A TW97117550 A TW 97117550A TW 97117550 A TW97117550 A TW 97117550A TW 200903588 A TW200903588 A TW 200903588A
Authority
TW
Taiwan
Prior art keywords
metal
alignment
pad
wafer
metal block
Prior art date
Application number
TW97117550A
Other languages
English (en)
Chinese (zh)
Inventor
Sung-Jae Kim
Yong-Bok Park
Jung-Soo Nam
In-Jung Lee
Sung-Jun Kim
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200903588A publication Critical patent/TW200903588A/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/101—Marks applied to devices, e.g. for alignment or identification characterised by the type of information, e.g. logos or symbols
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07221—Aligning
    • H10W72/07223—Active alignment, e.g. using optical alignment using marks or sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/227—Multiple bumps having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/261—Functions other than electrical connecting
    • H10W72/263—Providing mechanical bonding or support, e.g. dummy bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/261—Functions other than electrical connecting
    • H10W72/267—Multiple bump connectors having different functions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/926—Multiple bond pads having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/981—Auxiliary members, e.g. spacers
    • H10W72/983—Reinforcing structures, e.g. collars

Landscapes

  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW97117550A 2007-05-14 2008-05-13 Align mark, semiconductor chip including the same, semiconductor package including the chip and methods of fabricating the same TW200903588A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR20070046768A KR100809726B1 (ko) 2007-05-14 2007-05-14 얼라인 마크, 상기 얼라인 마크를 구비하는 반도체 칩,상기 반도체 칩을 구비하는 반도체 패키지 및 상기 반도체칩과 상기 반도체 패키지의 제조방법들

Publications (1)

Publication Number Publication Date
TW200903588A true TW200903588A (en) 2009-01-16

Family

ID=39397549

Family Applications (1)

Application Number Title Priority Date Filing Date
TW97117550A TW200903588A (en) 2007-05-14 2008-05-13 Align mark, semiconductor chip including the same, semiconductor package including the chip and methods of fabricating the same

Country Status (5)

Country Link
US (1) US20080284048A1 (https=)
JP (1) JP2008283195A (https=)
KR (1) KR100809726B1 (https=)
CN (1) CN101369572B (https=)
TW (1) TW200903588A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI512862B (zh) * 2013-03-25 2015-12-11 東芝股份有限公司 Manufacturing method of semiconductor device

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7638888B2 (en) * 2007-02-16 2009-12-29 Panasonic Corporation Semiconductor chip mounting substrate, semiconductor chip mounting body, semiconductor chip stacked module, and semiconductor chip mounting substrate manufacturing method
FR2913529B1 (fr) * 2007-03-09 2009-04-24 E2V Semiconductors Soc Par Act Boitier de circuit integre,notamment pour capteur d'image, et procede de positionnement
US7875988B2 (en) * 2007-07-31 2011-01-25 Seiko Epson Corporation Substrate and manufacturing method of the same, and semiconductor device and manufacturing method of the same
KR101055432B1 (ko) * 2008-10-30 2011-08-08 삼성전기주식회사 정렬홀을 갖는 반도체칩 및 그 제조방법
JP5658442B2 (ja) * 2009-06-02 2015-01-28 株式会社東芝 電子部品とその製造方法
JP5927756B2 (ja) * 2010-12-17 2016-06-01 ソニー株式会社 半導体装置及び半導体装置の製造方法
JP5795196B2 (ja) * 2011-06-09 2015-10-14 新光電気工業株式会社 半導体パッケージ
KR20140017086A (ko) 2012-07-30 2014-02-11 삼성디스플레이 주식회사 집적회로 및 이를 포함하는 표시 장치
CN104798193B (zh) * 2012-11-21 2017-12-22 三菱电机株式会社 半导体装置及其制造方法
US8901756B2 (en) * 2012-12-21 2014-12-02 Spansion Llc Chip positioning in multi-chip package
US9355979B2 (en) * 2013-08-16 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment structures and methods of forming same
JP6287103B2 (ja) * 2013-11-22 2018-03-07 セイコーエプソン株式会社 半導体装置、半導体装置の製造方法
US20150187608A1 (en) * 2013-12-26 2015-07-02 Sanka Ganesan Die package architecture with embedded die and simplified redistribution layer
US9589900B2 (en) 2014-02-27 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Metal pad for laser marking
US9343434B2 (en) 2014-02-27 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Laser marking in packages
US9666522B2 (en) 2014-05-29 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment mark design for packages
US10170444B2 (en) * 2015-06-30 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices
CN105654856A (zh) 2016-02-04 2016-06-08 京东方科技集团股份有限公司 一种显示装置及其芯片邦定方法
US10692813B2 (en) * 2016-11-28 2020-06-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package with dummy bumps connected to non-solder mask defined pads
KR102554017B1 (ko) * 2018-10-02 2023-07-11 삼성전자주식회사 반도체 패키지
KR102606567B1 (ko) * 2018-11-07 2023-11-28 삼성디스플레이 주식회사 유기 발광 표시 장치
TWI730799B (zh) * 2020-06-04 2021-06-11 力晶積成電子製造股份有限公司 影像感測器的製造方法及對準標記結構
CN112420534B (zh) 2020-11-27 2021-11-23 上海易卜半导体有限公司 形成半导体封装件的方法及半导体封装件
US12293986B2 (en) 2020-12-04 2025-05-06 Yibu Semiconductor Co., Ltd. Method for forming chip packages and a chip package
CN112687619A (zh) 2020-12-25 2021-04-20 上海易卜半导体有限公司 形成半导体封装件的方法及半导体封装件
JP7629340B2 (ja) * 2021-05-13 2025-02-13 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
KR20230083102A (ko) 2021-12-02 2023-06-09 삼성전자주식회사 인쇄회로기판 및 이를 포함하는 반도체 패키지
KR102876389B1 (ko) 2021-12-27 2025-10-24 삼성전자주식회사 인쇄회로기판 및 그를 포함하는 반도체 패키지
KR102802969B1 (ko) * 2022-10-24 2025-05-08 세메스 주식회사 반도체 기판 장치와, 반도체 처리 방법 및 반도체 처리 장치
US20240186260A1 (en) * 2022-12-06 2024-06-06 Lx Semicon Co., Ltd. Semiconductor device
US20240213175A1 (en) * 2022-12-27 2024-06-27 Samsung Electronics Co., Ltd. Semiconductor package having alignment pattern
CN116466552A (zh) * 2023-04-28 2023-07-21 无锡兴华衡辉科技有限公司 对位标记及其应用、读出电路芯片及其应用

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940004764A (ko) * 1992-08-20 1994-03-15 문정환 솔더 범프 형성방법
JP2003124255A (ja) * 2001-10-17 2003-04-25 Seiko Epson Corp 半導体装置及びその製造方法、半導体チップ及び実装方法
US6593221B1 (en) * 2002-08-13 2003-07-15 Micron Technology, Inc. Selective passivation of exposed silicon
US6750133B2 (en) * 2002-10-24 2004-06-15 Intel Corporation Selective ball-limiting metallurgy etching processes for fabrication of electroplated tin bumps
US6975040B2 (en) * 2003-10-28 2005-12-13 Agere Systems Inc Fabricating semiconductor chips

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI512862B (zh) * 2013-03-25 2015-12-11 東芝股份有限公司 Manufacturing method of semiconductor device

Also Published As

Publication number Publication date
KR100809726B1 (ko) 2008-03-06
US20080284048A1 (en) 2008-11-20
JP2008283195A (ja) 2008-11-20
CN101369572B (zh) 2011-10-12
CN101369572A (zh) 2009-02-18

Similar Documents

Publication Publication Date Title
TW200903588A (en) Align mark, semiconductor chip including the same, semiconductor package including the chip and methods of fabricating the same
US7276780B2 (en) Semiconductor device and chip-stack semiconductor device
TWI286454B (en) Electrical connector structure of circuit board and method for fabricating the same
CN102034780B (zh) 集成电路芯片、具有该芯片的倒装芯片封装和其制造方法
KR101850121B1 (ko) 용장성 실리콘 관통 비아를 구비한 반도체 칩 및 그 제조방법
US8735276B2 (en) Semiconductor packages and methods of manufacturing the same
TWI260060B (en) Chip electrical connection structure and fabrication method thereof
US7791173B2 (en) Chip having side pad, method of fabricating the same and package using the same
CN101290930B (zh) 包含半导体芯片叠层的半导体器件及其制造方法
TWI517273B (zh) 具有支撐終端墊的半導體晶片
US20100109164A1 (en) Stacked integrated circuit package fabrication methods that use vias formed and filled after stacking, and related stacked integrated circuit package structures
CN101355044A (zh) 系统级封装及其制造方法
CN109817600A (zh) 电子封装件及其制法
CN105448755A (zh) 一种铜柱凸点的封装方法及封装结构
TWI234261B (en) Method of forming wafer backside interconnects
CN113632232A (zh) 驱动背板及其制备方法、显示面板、显示装置
CN109192717A (zh) 多晶圆堆叠结构及其形成方法
CN101192581B (zh) 半导体装置及半导体封装体
TW201712812A (zh) 玻璃基板封裝及其製造方法
US20050179120A1 (en) Process for producing semiconductor device, semiconductor device, circuit board and electronic equipment
TWI362735B (en) Semiconductor chip having tsv (through silicon via) and stacked assembly including the chips
TW200406050A (en) Selective C4 connection in IC packaging
TW202407945A (zh) 用於邏輯電路的佈線連接的系統以及積體電路及其製造方法
CN201594536U (zh) 芯片堆栈电路结构
TW202412209A (zh) 半導體互連橋封裝