CN101369572A - 对准标记及其半导体芯片和封装以及其制造方法 - Google Patents
对准标记及其半导体芯片和封装以及其制造方法 Download PDFInfo
- Publication number
- CN101369572A CN101369572A CNA2008101714342A CN200810171434A CN101369572A CN 101369572 A CN101369572 A CN 101369572A CN A2008101714342 A CNA2008101714342 A CN A2008101714342A CN 200810171434 A CN200810171434 A CN 200810171434A CN 101369572 A CN101369572 A CN 101369572A
- Authority
- CN
- China
- Prior art keywords
- metal
- pad
- chip
- aligning
- diaphragm
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05164—Palladium [Pd] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05166—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05171—Chromium [Cr] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05575—Plural external layers
- H01L2224/0558—Plural external layers being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05655—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05666—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1401—Structure
- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1751—Function
- H01L2224/17515—Bump connectors having different functions
- H01L2224/17517—Bump connectors having different functions including bump connectors providing primarily mechanical support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01049—Indium [In]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0494—4th Group
- H01L2924/04941—TiN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明公开了对准标记及其半导体芯片和封装以及其制造方法。该对准标记可以包括衬底上的对准金属焊盘并被电隔离。保护膜可以在对准金属焊盘上并可以包括暴露出对准金属焊盘的一部分的开口。对准金属凸块可以在暴露于开口中的对准金属焊盘上,从而对准金属凸块突出到保护膜之上。
Description
技术领域
本发明涉及一种具有改进的识别率的对准标记、包括该对准标记的半导体芯片、包括该半导体芯片的半导体封装以及制造该对准标记、该半导体芯片和该半导体封装的方法。
背景技术
一般地,半导体封装通过将半导体芯片装配在布线衬底上来制造。为了使布线衬底的键合焊盘和半导体芯片的端子焊盘对准,对准标记在半导体芯片中形成。如果对准标记形成得模糊以致具有低的识别率,键合焊盘和端子焊盘可能没有被对准,从而可能没有良好的电连接。
发明内容
本发明提供了一种具有较高识别率的对准标记、包括该对准标记的半导体芯片、包括该半导体芯片的半导体封装以及制造该对准标记、该半导体芯片和该半导体封装的方法。
示例性实施例可以包括一种对准标记,该对准标记包括对准金属焊盘、保护膜和/或至少一部分对准金属凸块。对准金属焊盘可以在衬底上。对准金属焊盘可以被电隔离。对准标记可以包括保护膜,该保护膜包括暴露出对准金属焊盘的一部分的第一开口。对准标记还可以包括暴露于第一开口中的对准金属焊盘上并突出到保护膜之上的对准金属凸块。对准金属凸块可以用于将该衬底对准到外部衬底。
根据至少一些示例性实施例,对准金属凸块可以延伸到保护膜之上。籽晶金属层(seed metal layer)可以在对准金属焊盘和对准金属凸块之间。
示例性实施例可以包括一种含有对准标记的半导体芯片。衬底还可以包括对准标记区和端子焊盘区。
根据至少一些示例性实施例,半导体芯片可以包括对准标记区上的对准金属焊盘和端子焊盘区上的芯片金属焊盘。根据至少一些示例性实施例,保护膜可以包括第一开口和对准金属凸块以及暴露出芯片金属焊盘的一部分的第二开口。
根据至少一些示例性实施例,芯片金属凸块可以在暴露于第二开口中的芯片金属焊盘上。芯片金属凸块可以突出到保护膜之上。
示例性实施例可以包括一种含有半导体芯片的半导体封装。至少一些示例性实施例可以提供包括用于装配该半导体芯片的键合焊盘的布线衬底。键合焊盘和芯片金属焊盘可以彼此电连接。
根据至少一些示例性实施例,半导体封装还可以包括显示单元,该显示单元与键合焊盘电连接并在布线衬底上。
示例性实施例可以包括一种制造对准标记的方法,该方法包括在衬底上提供对准金属焊盘以及提供包括暴露出对准金属焊盘的一部分的第一开口的保护膜。对准金属凸块可以在暴露于第一开口中的对准金属焊盘上形成并突出到保护膜之上。
示例性实施例可以包括一种制造半导体芯片的方法。该方法可以包括制造对准标记。衬底可以制造对准标记区和端子焊盘区。根据至少一些示例性实施例,对准金属焊盘和对准金属凸块可以在对准标记区中形成,芯片金属焊盘可以在端子焊盘区中形成。示例性实施例还可以提供在保护膜中形成暴露芯片金属焊盘的一部分的第二开口。
至少一些示例性实施例可以提供一种在形成对准金属凸块的同时形成芯片金属凸块的方法,该芯片金属凸块在第二开口中暴露的芯片金属焊盘上并突出到保护膜之上。
至少一些示例性实施例可以,在形成对准金属凸块和芯片金属凸块之前,提供一种在暴露于第一开口中的对准金属焊盘上和在暴露于第二开口中的芯片金属焊盘上形成籽晶金属层的方法。
根据示例性实施例,对准金属凸块和芯片金属凸块可以采用电镀形成。对准金属凸块可以被形成以延伸到保护膜上。
示例性实施例可以包括一种制造半导体封装的方法。该方法可以包括形成半导体芯片。该方法还可以包括提供用于装配半导体芯片的布线衬底和键合焊盘。根据至少一些示例性实施例,该方法可以包括采用对准金属凸块作为对准标记将半导体芯片对准到布线衬底。该方法还可以包括将键合焊盘和芯片金属焊盘电连接。
根据示例性实施例,布线衬底可以包括电连接到键合焊盘的显示单元。
根据至少一些示例性实施例,半导体芯片还可以包括设置在暴露于第二开口中的芯片金属焊盘上并突出到保护膜上的芯片金属凸块。该半导体芯片可以被对准从而布线衬底上的芯片金属凸块面对键合焊盘。键合焊盘和芯片金属焊盘可以通过芯片金属凸块彼此电连接。
附图说明
示例性实施例的上述和其它特征和优势将通过对附图的详细描述变得更加明显,在附图中:
图1是根据示例性实施例的半导体芯片的示例性顶视图;
图2A到2D是示例性截面图,用于描述根据示例性实施例的一种形成对准标记的方法,其根据工艺的每个阶段沿图1的线I-I和II-II得到;
图3是示例性横截面图,用于描述根据示例性实施例的一种形成对准标记的方法,其沿图1的线I-I和II-II得到;
图4A和4B是示例性顶视图,用于描述根据示例性实施例的一种制造半导体封装的方法;以及
图5A是沿图4A的线III-III和IV-IV得到的示例性横截面图,图5B是沿图4B的线III-III和IV-IV得到的示例性横截面图。
具体实施方式
现在参照附图对各种示例性实施例进行更全面的描述。然而,为了描述示例性实施例,在此公开的特定结构和功能细节仅仅是代表性的,且本领域技术人员将能理解,示例性实施例可以以多种可选的形式实施,而不应被解释为仅限于此处所述的示例性实施例。
应当理解,虽然这里可使用术语第一、第二等描述各种元件,但这些元件不应被这些术语所限制。这些术语仅用于将一个元件与另一个元件区别开。例如,第一元件可以称为第二元件,类似地,第二元件可以称为第一元件,而不背离示例性实施例的范围。如此处所使用的,术语“和/或”包括一个或多个所列相关项目的任何及所有组合。
可以理解,当称一个元件“连接到”或“耦合到”另一个元件时,其可以直接连接到或耦合到另一个元件或者可以存在插入的元件。相反,当称一个元件“直接连接到”或“直接耦合到”另一个元件时,不存在插入元件。其它用于描述于元件之间的关系的词语应以相同的方式进行理解(例如“在...之间”相对于“直接在...之间”,“相邻”相对于“直接地相邻”等)。
这里所用的术语仅仅是为了描述示例性实施例,并非要限制示例性实施例。如此处所用的,除非上下文另有明确表述,否则单数形式“一(a)”、“一(an)”和“该(the)”均同时旨在包括复数形式。需要进一步理解的是,术语“包括(comprises和/或comprising)”或“包括(includes和/或including)”,当在此使用时,指定了所述特征、整体、步骤、操作、元件和/或部件的存在,但并不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其组合的存在或增加。
除非另行定义,此处使用的所有术语(包括技术术语和科学术语)都具有示例性实施例所属领域的技术人员所通常理解的相同的含义。进一步应当理解的是,诸如通用词典中所定义的术语,除非此处加以明确定义,否则应当被解释为具有与它们在相关领域的语境中的含义相一致的含义,而不应被解释为理想化的或过度形式化的意义。
下面参照附图对示例性实施例进行描述,提供示例性实施例是为了使本公开透彻和完整,并将示例性实施例充分传达给本领域技术人员。在附图中,相同的附图标记始终指代相同的元件。而且,为了清楚起见,放大了附图中层和区域的厚度。
参照图1,半导体芯片100可以包括一个主电路区C。示例性实施例中半导体芯片100是存储器半导体芯片,主电路区C可以是存储器单元阵列区,或者可选地,在示例性实施例中半导体芯片100是非存储器半导体芯片,主电路区C可以是运算电路区。在半导体芯片100是显示驱动IC的示例性实施例中,半导体芯片100是非存储器半导体芯片的类型,作为主电路区C的运算电路区可以包括图形控制器、时序控制器、电平移位器、公用电压发生器、数字驱动器和/或栅驱动器等。
端子焊盘TP可以位于主电路区C的外部。端子焊盘TP可以向主电路区C输入电信号并从主电路区C输出电信号,对准标记AK可以将端子焊盘TP对准到布线衬底的键合焊盘上。对准标记AK可以设置在半导体芯片100的顶部、底部、左侧、右侧和/或角落处。但是,主电路区C、端子焊盘TP和对准标记AK的位置不限于此。
图2D是根据示例性实施例示出沿图1的线I-I和II-II得到的对准标记AK的横截面图。
参照图1和2D,对准金属焊盘14a可以布置在衬底10的对准标记区上并且芯片金属焊盘14b可以布置在衬底10的端子焊盘区上。对准金属焊盘14a和芯片金属焊盘14b可以在绝缘膜12上形成,它们也可以在衬底10上形成。对准金属焊盘14a和芯片金属焊盘14b可以由相同的金属膜形成,例如Al膜或者Cu膜。
在芯片金属焊盘14b可以被电连接到主电路区C的同时,对准金属焊盘14a可以被电隔离。例如,芯片金属焊盘14b可以连接到插塞电极13,该插塞电极13电连接到主电路区C并设置在绝缘膜12中。
保护膜15包括暴露出对准金属焊盘14a的一部分的第一开口15a和暴露出芯片金属焊盘14b的一部分的第二开口15b,该保护膜15可以设置在对准金属焊盘14a和芯片金属焊盘14b上。保护膜15可以是氮化硅膜、氧化硅膜、氮氧化硅或其多层。有机聚合物层(未示出)也可以设置在保护层15上。
对准金属凸块18a可以提供在暴露于第一开口15a中的对准金属焊盘14a上。对准金属凸块18a可以突出到保护膜15之上并可以用作对准标记AK。例如,对准金属凸块18a的从保护膜15突出的部分用作对准标记AK。在示例性实施例中,对准金属凸块18a的相对高的反射率可以增大对准金属凸块18a和保护膜15之间的对比度,从而当使用对准设备时改善对准标记AK的识别率。此外,由于其相对高的反射率,即使当对准金属凸块18a的厚度改变时,对准金属凸块18a能够实现稳定的对比度。
芯片金属凸块18b可以设置在暴露于第二开口中的芯片金属焊盘14b上。芯片金属凸块18b可以突出到保护膜15之上。对准金属凸块18a和芯片金属凸块18b可以是相同的金属膜,例如Al膜、Ni膜、Pd膜、Ag膜、Au膜或者其多层。而且,对准金属凸块18a和芯片金属凸块18b可以具有相同的高度。
籽晶金属层17可以布置在对准金属凸块18a和对准金属焊盘14a之间以及芯片金属凸块18b和芯片金属焊盘14b之间。在采用电镀形成对准金属凸块18a的示例性实施例中,籽晶金属层17可以用作籽晶层,其可以是Cu、Ni、NiV、TiW、Au、Al或者其多金属层。籽晶金属粘附层16可以插入在籽晶金属层17和对准金属焊盘14a之间以及籽晶金属层17和芯片金属焊盘14b之间。籽晶金属粘附层16可以提高对准金属焊盘14a和芯片焊盘14b与籽晶金属层17之间的粘附力。籽晶金属粘附层16可以由Ti、TiN、Cr、Al、Ni、Pd或其多金属层形成。然而,在不是采用电镀形成对准金属凸块18a和芯片金属凸块18b的示例性实施例中,可以省去形成籽晶金属层17和籽晶金属粘附层16。即使在此示例性实施例中,对准金属凸块18a和对准金属焊盘14a都是金属,因此它们之间的粘附力较强,从而在半导体芯片100的运输和/或封装期间对准金属凸块18a不会从衬底10上脱离。如果形成籽晶金属层17和籽晶金属粘附层16,那么对准金属凸块18a和对准金属焊盘14a之间的粘附力可以进一步增强。
对准金属凸块18a上部宽度W_18a可以等于或大于第一开口15a的宽度W_15a。在示例性实施例中,对准金属凸块18a上部宽度W_18a可以大于第一开口15a的宽度W_15a。在此示例性实施例中,对准金属凸块18a可以在保护膜15上延伸。因此,对准金属凸块18a可以布置在保护膜15上,并可以由此在对准金属凸块18a的所有侧壁处稳定地实现对准金属凸块18a和保护膜15之间的对比度。
图2A到2D是横截面图,用于描述根据示例性实施例的一种形成对准标记AK的方法,其根据工艺的每个阶段沿图1的线I-I和II-II得到。
参照图2A,半导体衬底10可以包括对准标记区和端子焊盘区。绝缘膜12可以在半导体衬底10上形成。电连接到图1的主电路区C的插塞电极13可以在绝缘膜12中形成。第一金属膜在绝缘膜12上形成,第一金属膜可以被图案化以分别在对准标记区和端子焊盘区上形成对准金属焊盘14a和连接到插塞电极13的芯片金属焊盘14b。第一金属膜可以是Al膜或Cu膜。
保护膜15可以在对准金属焊盘14a和芯片金属焊盘14b上形成。有机聚合物层(未示出)可以进一步在保护膜15上形成。保护膜15和该有机聚合物层可以被图案化以形成暴露出对准金属焊盘14a的一部分的第一开口15a和暴露出芯片金属焊盘14b的一部分的第二开口15b。
参照图2B,籽晶金属层17可以在保护膜15上形成;对准金属焊盘14a和芯片金属焊盘14b可以分别暴露于第一开口15a和第二开口15b中。在形成籽晶金属层17之前,籽晶金属粘附层16可以在保护膜15上形成。籽晶金属粘附层16和籽晶金属层17可以采用溅射依次形成。
掩模图案20可以在籽晶金属层17上形成。掩模图案20可以包括第三开口20a和第四开口20b,其分别暴露出形成于第一开口15a和第二开口15b中的籽晶金属层17。第三开口20a和第四开口20b可以被形成从而具有至少与第一开口15a和第二开口15b相同的宽度,但也可以被形成从而具有比第一开口15a和第二开口15b的宽度更大的宽度。从而,籽晶金属层17可以在与第一开口15a和第二开口15b相邻的保护膜15上形成,并在第三开口20a和第四开口20b中暴露出来。掩模图案20可以是光致抗蚀剂图案。
参照图2C,第二金属膜可以在暴露于第三开口20a和第四开口20b中的籽晶金属层17上形成。从而,对准金属凸块18a和芯片金属凸块18b可以分别在对准金属焊盘14a和芯片金属焊盘14b上形成。在第三开口20a的宽度形成得比第一开口15a的宽度更大的示例性实施例中,对准金属凸块18a的上部宽度W_18a可以大于第一开口的宽度W_15a,对准金属凸块18a可以延伸到保护膜15上。
第二金属膜可以采用电镀方法形成。在示例性实施例中,籽晶金属层17可以作为用于引晶(seeding)或电镀的引线(leading wire)。然而,在第二金属膜采用电镀以外的方法,例如无电镀、金属膜沉积和蚀刻或者印刷形成的示例性实施例中,可以省去形成籽晶金属层17和籽晶金属粘附层16。在这种情况下,对准金属凸块18b和对准金属焊盘14a可以如此形成从而彼此接触,对准金属凸块18b和对准金属焊盘14b可以如此形成从而彼此接触。
参照图2D,掩模图案20可以被去除从而暴露出籽晶金属层17。采用凸块18a和18b作为掩模,暴露出的籽晶金属层17和籽晶金属粘附层16可以被蚀刻。从而形成端子焊盘TP,其中芯片金属焊盘14b、籽晶金属粘附层16、籽晶金属层17和芯片金属凸块18a可以依次堆叠在端子焊盘区上。而且,对准金属凸块18a的从保护膜15突出的部分可以用作对准标记AK。
图3是示例性横截面图,用于描述根据示例性实施例的一种形成对准标记AK的方法,其沿图1的线I-I和II-II得到。
参照图3,采用与参照图2A所述的相同的方法,保护膜15、绝缘膜12、插塞电极13、对准金属焊盘14a、芯片金属焊盘14b、和第一开口15a以及第二开口15b可以在包括对准标记区和端子焊盘区的半导体衬底10上形成。
对准金属凸块18a可以在暴露于第一开口15a中的对准金属焊盘14a上形成。对准金属凸块18a可以采用电镀、无电镀、金属膜沉积和蚀刻或印刷形成。芯片金属焊盘14b可以直接暴露在第二开口15b中。暴露在第二开口15b中的芯片金属焊盘14b可以用作端子焊盘TP,对准金属凸块18a的从保护膜15突出的部分可以用作对准标记AK。
图4A和4B是顶视图,用于描述根据示例性实施例的一种制造半导体封装的方法。图5A是沿图4A的线III-III和IV-IV得到的示例性截面图,图5B是沿图4B的线III-III和IV-IV得到的示例性截面图。
参照图4A和5A,布线衬底200可以包括键合焊盘210。布线衬底200可以包括电连接到键合焊盘210的显示单元D。在示例性实施例中,布线衬底200可以是能够透光的玻璃衬底。显示单元D可以包括显示图像的像素阵列部分P。显示单元D可以是液晶显示装置。在这种情况下,液晶显示装置可以插入在布线衬底200和设置在该布线衬底200上的上部衬底201之间。
键合焊盘210可以是透光电极,例如,铟锡氧化物(ITO)。表面绝缘膜220可以在键合焊盘210上形成,该表面绝缘膜220包括暴露出键合焊盘210的一部分的凹槽220a。
参照图4B和5B,采用对准金属凸块18a作为对准标记AK,半导体芯片100可以被对准到布线衬底200上。例如,对准金属凸块18a的从保护膜15突出的部分可以用作对准标记AK。半导体芯片100的端子焊盘TP可以被对准到键合焊盘210上。在示例性实施例中,当使用对准设备时,对准金属凸块18a和保护膜15之间较大的对比度可以增大对准标记AK的识别率,由此可以有效地减小对准误差。
半导体芯片100可以是参照图2D描述的半导体芯片。在示例性实施例中,半导体芯片100可以被设置并对准到布线衬底200上,从而半导体芯片100的端子焊盘TP,更具体地芯片金属凸块18b,面对键合焊盘210。可以在半导体芯片100上施加压力以将芯片金属凸块18b连接到键合焊盘210上。从而键合焊盘210和芯片金属焊盘14b可以通过芯片金属凸块18b电连接。
可选地,在半导体芯片100是参照图3所述的半导体芯片的示例性实施例中,暴露于开口15b中的芯片金属焊盘14b,也就是端子焊盘TP,可以采用金属导线(未示出)电连接到键合焊盘210。
根据上述示例性实施例,来自于对准金属凸块的较大程度的反射可以增强对准金属凸块和保护膜之间的对比度,从而提高在使用对准设备时对准标记的识别率。
根据示例性实施例,通过由金属形成对准金属凸块和对准金属焊盘,其间的粘附力可以被增强。因此,在运输和/或半导体芯片的封装工艺期间,对准金属凸块不会从衬底脱离。
根据示例性实施例,通过形成在保护膜之上延伸的对准金属凸块,对准金属凸块的侧壁可以位于保护膜上,由此可以在对准金属凸块的所有侧壁处实现对准金属凸块与保护膜之间的对比度。
根据示例性实施例,通过同时形成芯片金属凸块和对准金属凸块,对准金属凸块可以被形成而不需要额外的工艺。
尽管已经具体地示出和描述了示例性实施例,但是本领域技术人员应当理解,可以作出形式和细节上的各种变化而不背离由下面的权利要求书所限定的精神和范围。
本申请要求于2007年5月14日在韩国知识产权局提交的韩国专利申请第10-2007-0046768号的权益,其全部内容引入于此作为参考。
Claims (23)
1.一种对准标记,包括:
对准金属焊盘,其在衬底上并被电隔离;
保护膜,其包括暴露出所述对准金属焊盘的一部分的第一开口;以及
对准金属凸块,其在暴露于所述第一开口中的所述对准金属焊盘上并突出到所述保护膜之上。
2.如权利要求1所述的对准标记,其中所述对准金属凸块延伸到所述保护膜上。
3.如权利要求1所述的对准标记,还包括:
所述对准金属焊盘和所述对准金属凸块之间的籽晶金属层。
4.一种半导体芯片,包括:
权利要求1的所述对准标记,其中所述衬底包括对准标记区和端子焊盘区;
所述对准标记区上的所述对准金属焊盘和所述端子焊盘区上的芯片金属焊盘;
保护膜,包括所述第一开口和所述对准金属凸块以及暴露出所述芯片金属焊盘的一部分的第二开口。
5.如权利要求4所述的半导体芯片,还包括:
芯片金属凸块,其在暴露于所述第二开口中的所述芯片金属焊盘上并突出到所述保护膜之上。
6.如权利要求4所述的半导体芯片,其中所述对准金属凸块延伸到所述保护膜的一部分上。
7.如权利要求4所述的半导体芯片,还包括:
所述对准金属焊盘和所述对准金属凸块之间的籽晶金属层。
8.一种半导体封装,包括:
权利要求4的所述半导体芯片;
布线衬底,其包括用于装配所述半导体芯片的键合焊盘,其中所述对准金属凸块将所述半导体芯片对准到所述布线衬底。
9.如权利要求8所述的半导体封装,还包括:
显示单元,其与所述键合焊盘电连接并在所述布线衬底上。
10.如权利要求8所述的半导体封装,其中所述半导体芯片还包括:
芯片金属凸块,其在暴露于所述第二开口中的所述芯片金属焊盘上并突出到所述保护膜之上;且
所述芯片金属凸块在所述键合焊盘和所述芯片金属焊盘之间。
11.如权利要求8所述的半导体封装,其中所述对准金属凸块延伸到所述保护膜的一部分上。
12.如权利要求8所述的半导体封装,还包括:
所述对准金属焊盘和所述对准金属凸块之间的籽晶金属层。
13.一种制造对准标记的方法,该方法包括:
在衬底上提供对准金属焊盘;
提供保护膜,该保护膜包括暴露出所述对准金属焊盘的一部分的第一开口;以及
提供对准金属凸块,该对准金属凸块在暴露于所述第一开口中的所述对准金属焊盘上并突出到所述保护膜之上。
14.一种制造半导体芯片的方法,该方法包括:
根据权利要求13的所述方法制造所述对准标记,其中所述衬底包括对准标记区和端子焊盘区,所述对准金属焊盘和所述对准金属凸块在所述对准标记区中形成,芯片金属焊盘在所述端子焊盘区上形成;和
在所述保护膜中形成暴露出所述芯片金属焊盘的一部分的第二开口。
15.如权利要求14所述的方法,还包括:
在形成所述对准金属凸块的同时,在暴露于所述第二开口中的所述芯片金属焊盘上形成突出到所述保护膜之上的芯片金属凸块。
16.如权利要求15所述的方法,还包括:
在形成所述对准金属凸块和所述芯片金属凸块之前,在暴露于所述第一开口中的所述对准金属焊盘上和在暴露于所述第二开口中的所述芯片金属焊盘上形成籽晶金属层。
17.如权利要求16所述的方法,其中所述对准金属凸块和所述芯片金属凸块采用电镀形成。
18.如权利要求14所述的方法,其中所述对准金属凸块被形成以延伸到所述保护膜上。
19.一种制造半导体封装的方法,该方法包括:
根据权利要求14所述的方法制造所述半导体芯片;
提供用于装配所述半导体芯片的布线衬底和键合焊盘;
采用所述对准金属凸块将所述半导体芯片对准到所述布线衬底;以及
电连接所述键合焊盘和所述芯片金属焊盘。
20.如权利要求19所述的方法,其中所述布线衬底包括电连接到所述键合焊盘的显示单元。
21.如权利要求19所述的方法,其中所述半导体芯片还包括:
芯片金属凸块,其设置在暴露于所述第二开口中的所述芯片金属焊盘上并突出到所述保护膜之上;
所述半导体芯片被对准从而所述布线衬底上的所述芯片金属凸块面对所述键合焊盘;以及
所述键合焊盘和所述芯片金属焊盘通过所述芯片金属凸块彼此电连接。
22.如权利要求19所述的方法,其中所述对准金属凸块延伸到所述保护膜上。
23.如权利要求19所述的方法,其中所述半导体芯片还包括:
籽晶金属层,其布置在所述对准金属焊盘和所述对准金属凸块之间。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR20070046768A KR100809726B1 (ko) | 2007-05-14 | 2007-05-14 | 얼라인 마크, 상기 얼라인 마크를 구비하는 반도체 칩,상기 반도체 칩을 구비하는 반도체 패키지 및 상기 반도체칩과 상기 반도체 패키지의 제조방법들 |
KR46768/07 | 2007-05-14 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101369572A true CN101369572A (zh) | 2009-02-18 |
CN101369572B CN101369572B (zh) | 2011-10-12 |
Family
ID=39397549
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2008101714342A Expired - Fee Related CN101369572B (zh) | 2007-05-14 | 2008-05-14 | 对准标记及其半导体芯片和封装以及其制造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20080284048A1 (zh) |
JP (1) | JP2008283195A (zh) |
KR (1) | KR100809726B1 (zh) |
CN (1) | CN101369572B (zh) |
TW (1) | TW200903588A (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104798193A (zh) * | 2012-11-21 | 2015-07-22 | 三菱电机株式会社 | 半导体装置及其制造方法 |
WO2017133116A1 (zh) * | 2016-02-04 | 2017-08-10 | 京东方科技集团股份有限公司 | 显示装置及其芯片连接方法 |
TWI730799B (zh) * | 2020-06-04 | 2021-06-11 | 力晶積成電子製造股份有限公司 | 影像感測器的製造方法及對準標記結構 |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7638888B2 (en) * | 2007-02-16 | 2009-12-29 | Panasonic Corporation | Semiconductor chip mounting substrate, semiconductor chip mounting body, semiconductor chip stacked module, and semiconductor chip mounting substrate manufacturing method |
FR2913529B1 (fr) * | 2007-03-09 | 2009-04-24 | E2V Semiconductors Soc Par Act | Boitier de circuit integre,notamment pour capteur d'image, et procede de positionnement |
US7875988B2 (en) * | 2007-07-31 | 2011-01-25 | Seiko Epson Corporation | Substrate and manufacturing method of the same, and semiconductor device and manufacturing method of the same |
KR101055432B1 (ko) * | 2008-10-30 | 2011-08-08 | 삼성전기주식회사 | 정렬홀을 갖는 반도체칩 및 그 제조방법 |
JP5658442B2 (ja) * | 2009-06-02 | 2015-01-28 | 株式会社東芝 | 電子部品とその製造方法 |
JP5927756B2 (ja) * | 2010-12-17 | 2016-06-01 | ソニー株式会社 | 半導体装置及び半導体装置の製造方法 |
JP5795196B2 (ja) * | 2011-06-09 | 2015-10-14 | 新光電気工業株式会社 | 半導体パッケージ |
KR20140017086A (ko) * | 2012-07-30 | 2014-02-11 | 삼성디스플레이 주식회사 | 집적회로 및 이를 포함하는 표시 장치 |
US8901756B2 (en) | 2012-12-21 | 2014-12-02 | Spansion Llc | Chip positioning in multi-chip package |
JP5763116B2 (ja) * | 2013-03-25 | 2015-08-12 | 株式会社東芝 | 半導体装置の製造方法 |
US9355979B2 (en) * | 2013-08-16 | 2016-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Alignment structures and methods of forming same |
JP6287103B2 (ja) * | 2013-11-22 | 2018-03-07 | セイコーエプソン株式会社 | 半導体装置、半導体装置の製造方法 |
US20150187608A1 (en) * | 2013-12-26 | 2015-07-02 | Sanka Ganesan | Die package architecture with embedded die and simplified redistribution layer |
US9589900B2 (en) | 2014-02-27 | 2017-03-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal pad for laser marking |
US9343434B2 (en) | 2014-02-27 | 2016-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Laser marking in packages |
US9666522B2 (en) | 2014-05-29 | 2017-05-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Alignment mark design for packages |
US10170444B2 (en) * | 2015-06-30 | 2019-01-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices |
US10692813B2 (en) * | 2016-11-28 | 2020-06-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package with dummy bumps connected to non-solder mask defined pads |
KR102554017B1 (ko) * | 2018-10-02 | 2023-07-11 | 삼성전자주식회사 | 반도체 패키지 |
KR102606567B1 (ko) * | 2018-11-07 | 2023-11-28 | 삼성디스플레이 주식회사 | 유기 발광 표시 장치 |
JP2022175499A (ja) * | 2021-05-13 | 2022-11-25 | 新光電気工業株式会社 | 配線基板、半導体装置及び配線基板の製造方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR940004764A (ko) * | 1992-08-20 | 1994-03-15 | 문정환 | 솔더 범프 형성방법 |
JP2003124255A (ja) * | 2001-10-17 | 2003-04-25 | Seiko Epson Corp | 半導体装置及びその製造方法、半導体チップ及び実装方法 |
US6593221B1 (en) * | 2002-08-13 | 2003-07-15 | Micron Technology, Inc. | Selective passivation of exposed silicon |
US6750133B2 (en) * | 2002-10-24 | 2004-06-15 | Intel Corporation | Selective ball-limiting metallurgy etching processes for fabrication of electroplated tin bumps |
US6975040B2 (en) * | 2003-10-28 | 2005-12-13 | Agere Systems Inc | Fabricating semiconductor chips |
-
2007
- 2007-05-14 KR KR20070046768A patent/KR100809726B1/ko not_active IP Right Cessation
-
2008
- 2008-05-13 JP JP2008126087A patent/JP2008283195A/ja active Pending
- 2008-05-13 TW TW97117550A patent/TW200903588A/zh unknown
- 2008-05-14 CN CN2008101714342A patent/CN101369572B/zh not_active Expired - Fee Related
- 2008-05-14 US US12/153,088 patent/US20080284048A1/en not_active Abandoned
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104798193A (zh) * | 2012-11-21 | 2015-07-22 | 三菱电机株式会社 | 半导体装置及其制造方法 |
CN104798193B (zh) * | 2012-11-21 | 2017-12-22 | 三菱电机株式会社 | 半导体装置及其制造方法 |
WO2017133116A1 (zh) * | 2016-02-04 | 2017-08-10 | 京东方科技集团股份有限公司 | 显示装置及其芯片连接方法 |
US10242605B2 (en) | 2016-02-04 | 2019-03-26 | Boe Technology Group Co., Ltd. | Display device having the bumps in the middle zone parallel to the reference line |
TWI730799B (zh) * | 2020-06-04 | 2021-06-11 | 力晶積成電子製造股份有限公司 | 影像感測器的製造方法及對準標記結構 |
Also Published As
Publication number | Publication date |
---|---|
KR100809726B1 (ko) | 2008-03-06 |
TW200903588A (en) | 2009-01-16 |
US20080284048A1 (en) | 2008-11-20 |
CN101369572B (zh) | 2011-10-12 |
JP2008283195A (ja) | 2008-11-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101369572B (zh) | 对准标记及其半导体芯片和封装以及其制造方法 | |
KR100556177B1 (ko) | 반도체 장치 및 그 제조 방법, 회로 기판 및 전자 기기 | |
US6777796B2 (en) | Stacked semiconductor chips on a wiring board | |
US8120176B2 (en) | Semiconductor device having a conductive bump | |
CN100587929C (zh) | 电子器件及其制造方法 | |
CN100555590C (zh) | 电子器件制造方法 | |
US7425766B2 (en) | Film substrate, fabrication method thereof, and image display substrate | |
US20050093151A1 (en) | Semiconductor circuit with multiple contact sizes | |
US7731506B2 (en) | Pin layout of a golden finger for flexible printed circuitboard | |
US11217508B2 (en) | Lead structure of circuit with increased gaps between adjacent leads | |
US20080119004A1 (en) | Method of packaging a device having a keypad switch point | |
US20080087995A1 (en) | Flexible film semiconductor package and method for manufacturing the same | |
US20230037785A1 (en) | Chip-on-film package | |
US11477886B2 (en) | Circuit board structure and spliced circuit board | |
US20220181244A1 (en) | Package substrate and package structure | |
CN111106097B (zh) | 膜上芯片封装件 | |
US20050190528A1 (en) | Electronic component, method of manufacturing the electronic component, and electronic apparatus | |
CN2705801Y (zh) | 用于液晶显示器基板的裸晶焊垫布局 | |
US7557455B1 (en) | System and apparatus that reduce corrosion of an integrated circuit through its bond pads | |
CN117998921A (zh) | 一种显示面板及其制备方法、显示装置 | |
KR100924553B1 (ko) | 메모리 모듈 | |
CN116207065A (zh) | 封装结构、封装系统及其成型方法 | |
CN113314564A (zh) | 电子装置 | |
KR20010020982A (ko) | 하이브리드 모듈 및 그 단자부품과 이것을 이용한 전자장치 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20111012 Termination date: 20140514 |