CN111106097B - 膜上芯片封装件 - Google Patents

膜上芯片封装件 Download PDF

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CN111106097B
CN111106097B CN201910283612.9A CN201910283612A CN111106097B CN 111106097 B CN111106097 B CN 111106097B CN 201910283612 A CN201910283612 A CN 201910283612A CN 111106097 B CN111106097 B CN 111106097B
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chip
circuit layer
patterned circuit
film package
chips
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CN111106097A (zh
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廖骏宇
游腾瑞
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Novatek Microelectronics Corp
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Abstract

本发明实施例提供一种膜上芯片封装件，其包含柔性膜、第一图案化电路层、一个或多个第一芯片、第二图案化电路层以及一个或多个第二芯片。柔性膜包含第一表面及与第一表面相对的第二表面。第一图案化电路层设置在第一表面上。一个或多个第一芯片安装在第一表面上且电连接到第一图案化电路层。第二图案化电路层设置在第二表面上。一个或多个第二芯片安装在第二表面上且电连接到第二图案化电路层。本发明实施例的膜上芯片封装件可提高基底膜的空间利用效率。

Description

膜上芯片封装件
技术领域
本公开大体上涉及芯片封装件。更具体地说，本公开涉及膜上芯片封装件。
背景技术
膜上芯片(chip on film；COF)半导体封装件可包含通过使用倒装芯片技术安装在膜衬底上的半导体芯片。COF半导体封装件可通过连接到膜衬底上的金属图案的输入/输出(input/output；I/O)引脚来连接到外部电路。
COF衬底可包含基底膜，集成电路芯片可安装到基底膜上，且导电图案可布置在基底膜上。每个导电图案可具有连接到芯片的第一端以及连接到显示面板的面板图案的第二端。
发明内容
因此，本公开的目的在于提供一种提高基底膜的空间利用效率的膜上芯片封装件。
为达上述目的，本公开提供的一种膜上芯片封装件，其包含柔性膜、第一图案化电路层、一个或多个第一芯片、第二图案化电路层以及一个或多个第二芯片。柔性膜包含第一表面和与第一表面相对的第二表面。第一图案化电路层设置在第一表面上。一个或多个第一芯片安装在第一表面上且电连接到第一图案化电路层。第二图案化电路层设置在第二表面上。一个或多个第二芯片安装在第二表面上且电连接到第二图案化电路层。
根据本公开的实施例，一个或多个第一芯片安装在第一表面的第一安装区上，一个或多个第二芯片安装在第二表面的第二安装区上，且第一安装区从俯视方向来看与第二安装区重叠。
根据本公开的实施例，一个或多个第二芯片中的至少一个位于一个或多个第一芯片中的至少一个的正下方。
根据本公开的实施例，一个或多个第一芯片安装在第一表面的第一安装区上，一个或多个第二芯片安装在第二表面的第二安装区上，且第一安装区从俯视方向来看不与第二安装区重叠。
根据本公开的实施例，柔性膜还包括电连接第一图案化电路层和第二图案化电路层的一个或多个通孔。
根据本公开的实施例，膜上芯片封装件还包含第一阻焊层，所述第一阻焊层设置在第一图案化电路层上且暴露第一图案化电路层中安装一个或多个第一芯片的部分。
根据本公开的实施例，膜上芯片封装件还包含第二阻焊层，所述第二阻焊层设置在第二图案化电路层上且暴露第二图案化电路层中安装一个或多个第二芯片的部分。
根据本公开的实施例，所述一个或多个第一芯片的数目为多个。
根据本公开的实施例，第一芯片以并排的方式安装在第一表面上。
根据本公开的实施例，所述一个或多个第二芯片的数目为多个。
根据本公开的实施例，第二芯片以并排的方式安装在第二表面上。
根据本公开的实施例，膜上芯片封装件还包含连接到柔性膜的外围区且电连接到第一图案化电路层和/或第二图案化电路层的衬底。
根据本公开的实施例，衬底包括玻璃衬底或印刷电路板。
根据本公开的实施例，柔性膜还包括电连接第一图案化电路层和第二图案化电路层的多个通孔。
根据本公开的实施例，膜上芯片封装件还包括连接到第一表面的外围区的第一衬底和连接到第二表面的外围区的第二衬底，其中第一衬底电连接到第一图案化电路层且第二衬底电连接到第二图案化电路层。
基于上述，在本公开的膜上芯片封装件中，芯片安装在柔性膜的两个相对表面上，以提高柔性膜的两侧的空间使用，从而可提高膜上芯片封装件的空间利用效率。另外，通过布置通孔来使柔性膜的两个相对表面上的图案化电路层电连接，可显着提高膜上芯片封装件的设计灵活性。
附图说明
包含附图以便进一步理解本公开，且附图并入本说明书中并构成本说明书的一部分。附图说明本公开的实施例，且与描述一起用于解释本公开的原理。
图1为本公开的实施例的膜上芯片封装件的截面视图；
图2为本公开的实施例的膜上芯片封装件的截面视图；
图3为本公开的实施例的膜上芯片封装件的截面视图；
图4为本公开的实施例的膜上芯片封装件的截面视图；
图5为本公开的实施例的膜上芯片封装件的俯视图；
图6为本公开的实施例的膜上芯片封装件的截面视图；
图7为本公开的实施例的膜上芯片封装件的截面视图。
附图标号说明
100、100a、100b、100c、100d、100e：膜上芯片封装件；
110：柔性膜；
112：第一表面；
114：第二表面；
116：通孔；
120：第一图案化电路层；
130：第一芯片；
132、152：导电凸块；
140：第二图案化电路层；
150：第二芯片；
160：第一阻焊层；
170：第二阻焊层；
180：第一衬底；
190：第二衬底；
R1：第一安装区；
R2：第二安装区。
具体实施方式
现将详细参考本公开的优选实施例，其实例在附图中示出。只要有可能，相同的附图标号在图式和描述中用以指代相同或相似部分。本文所使用的例如“在...上(on)”、“在...上方(above)”、“在...下方(below)”、“正面(front)”、“背面(back)”、“左(left)”以及“右(right)”的术语仅出于描述图中方向的目的且并不意欲限制本公开。此外，在本文中的论述和权利要求中，术语「在...上」相对于两种材料使用，一个“在”另一个“上”是指材料之间至少有一些接触，而“在...上方”和“上覆于(overlie)”是指材料接近，但可能有一种或多种额外中间材料，从而可能有物理接触但不是必须的。“在…上”或“在…上方”都不暗示如本文中所使用的任何定向性。
除非另有限制，否则术语“设置”、“连接”、“耦接”以及“安装”和其在本文中的变体是广义上使用的并且涵盖直接和间接连接、耦接以及安装。类似地，术语“面向(facing/faces)”及其在本文中的变体是广义上使用的并且涵盖直接和间接面向，且“相邻”及其在本文中的变体是广义上使用的并且涵盖直接和间接“相邻”。因此，附图和描述应被视为在本质上是说明性而非限制性的。
图1示出根据本公开的实施例的膜上芯片封装件的截面视图。参看图1，在一些实施例中，膜上芯片封装件100包含柔性膜110、第一图案化电路层120、一个或多个第一芯片130(示出一个，但不限于此)、第二图案化电路层140以及一个或多个第二芯片150(示出一个，但不限于此)。柔性膜110可包含柔性和绝缘材料。安装在其上的芯片130/芯片150可用以驱动半导体装置、显示装置(即芯片130/芯片150可为显示驱动器)等等。柔性膜110包含第一表面112和与第一表面112相对的第二表面114。第一图案化电路层120设置在第一表面112上。第一芯片130安装在第一表面112上且电连接到第一图案化电路层120。在一些实施例中，第一芯片130经由例如倒装芯片结合技术通过多个导电凸块132而安装在第一表面112的第一图案化电路层120上。在其它实施例中，第一芯片130可安装在第一表面112上且经由例如线接合技术通过多个导线而电连接到第一图案化电路层120。第二图案化电路层140设置在第二表面114上。第二芯片150安装在第二表面114上且电连接到第二图案化电路层140。在一些实施例中，第二芯片150经由例如倒装芯片结合技术通过多个导电凸块152而安装在第二表面114的第二图案化电路层140上。在其它实施例中，第二芯片150可安装在第二表面114上且经由例如线接合技术通过多个电线而电连接到第二图案化电路层140。本公开不限制芯片130、芯片150安装在柔性膜110上以及电连接到图案化电路层120、图案化电路层140的方式。
在一些实施例中，第一芯片130安装在第一表面112的第一安装区R1上，且第二芯片150安装在第二表面114的第二安装区R2上。从图1所绘示的俯视方向来看，第一安装区R1与第二安装区R2重叠。换句话说，安装第一芯片130的第一安装区R1和安装第二芯片150的第二安装区R2未完全错开而是从俯视方向来看部分重叠。在本发明实施例中，第一芯片130和第二芯片150可彼此电绝缘。即，第一图案化电路层120和第二图案化电路层140彼此电绝缘，但本公开不限于此。
在一些实施例中，膜上芯片封装件100还包含第一阻焊层160，第一阻焊层160设置在第一图案化电路层120上且暴露第一图案化电路层120安装第一芯片130的部分。换句话说，第一阻焊层160设置在第一图案化电路层120上且暴露柔性膜110的第一安装区R1。类似地，膜上芯片封装件100可还包含第二阻焊层170，第二阻焊层170设置在第二图案化电路层140上且暴露第二图案化电路层140安装第二芯片150的部分。换句话说，第二阻焊层170设置在第二图案化电路层140上且暴露柔性膜110的第二安装区R2。
图2示出根据本公开的实施例的膜上芯片封装件的截面视图。应注意，绘示于图2中的膜上芯片封装件100a包含许多与先前提到的图1的膜上芯片封装件100相同或相似的特征。出于清楚以及简单的目的，可省略相同或相似特征的详细描述，并且相同或相似附图标记指代相同或类似组件。绘示于图2中的膜上芯片封装件100a与绘示于图1中的膜上芯片封装件100之间的主要区别描述如下。
参看图2，在一些实施例中，柔性膜110可还包含一个或多个通孔116，其电连接第一图案化电路层120和第二图案化电路层140。换句话说，在本发明实施例中，第一图案化电路层120和第二图案化电路层140通过通孔116彼此电连接。因此，第一芯片130电连接到第二芯片150。
图3示出根据本公开的实施例的膜上芯片封装件的截面视图。应注意，绘示于图3中的膜上芯片封装件100b包含许多与先前提到的图1的膜上芯片封装件100相同或相似的特征。出于清楚以及简单的目的，可省略相同或相似特征的详细描述，并且相同或相似附图标记指代相同或类似组件。绘示于图3中的膜上芯片封装件100b与绘示于图1中的膜上芯片封装件100之间的主要区别描述如下。
参看图3，在一些实施例中，从如图3中绘示的俯视方向看，第一安装区R1不与第二安装区R2重叠。换句话说，从俯视方向来看，安装第一芯片130的第一安装区R1和安装第二芯片150的第二安装区R2完全错开，以避免由倒装芯片结合技术所施加的接合力损坏相对侧上的芯片130/芯片150。
图4示出根据本公开的实施例的膜上芯片封装件的截面视图。应注意，绘示于图4中的膜上芯片封装件100c包含许多与先前提到的图3的膜上芯片封装件100b相同或相似的特征。出于清楚以及简单的目的，可省略相同或相似特征的详细描述，并且相同或相似附图标记指代相同或类似组件。绘示于图4中的膜上芯片封装件100c与绘示于图3中的膜上芯片封装件100b之间的主要区别描述如下。
参看图4，在一些实施例中，第二芯片150位于第一芯片130的正下方。也就是说，从俯视方向看，第二芯片150与第一芯片130对准。换句话说，从如图4中绘示的俯视方向来看，安装第一芯片130的第一安装区R1与安装第二芯片150的第二安装区R2完全重叠。在安装在柔性膜110上的多个第一芯片130和多个第二芯片150的实施例中，第二芯片150中的至少一个位于第一芯片130中的至少一个的正下方。在一些实施例中，提供具有用于容纳至少一个第一芯片130的至少一个空腔的载体。接着，可将具有安装在第一表面112上的第一芯片130的柔性膜110设置在载体上，其中第二表面114朝上，从而使得安装在第一表面112上的第一芯片130可容纳于载体的空腔中。接着，第二芯片150可通过例如倒装芯片接合技术安装在第二表面114上而不损坏第一芯片130。上述安装工艺还可应用到其它膜上芯片封装件(例如膜上芯片封装件100、膜上芯片封装件100a、膜上芯片封装件100b等)。
图5示出根据本公开的实施例的膜上芯片封装件的俯视图。在一些实施例中，第一芯片130的数目为多个，且第一芯片130以并排的方式安装在柔性膜110的第一表面112上。在一些实施例中，第二芯片150的数目为多个，且第二芯片150以并排的方式安装在柔性膜110的第二表面114上。在一些实施例中，第二芯片150可相应地设置在第一芯片130的正下方。即，从俯视方向来看，第二芯片150相应地与第一芯片130对准。在其它实施例中，从俯视方向看，安装第一芯片130的第一安装区R1与安装第二芯片150的第二安装区R2重叠。本公开不限制第一芯片和第二芯片150的数目和位置。
图6示出根据本公开的实施例的膜上芯片封装件的截面视图。应注意，绘示于图6中的膜上芯片封装件100d包含许多与先前提到的图1的膜上芯片封装件100相同或相似的特征。出于清楚以及简单的目的，可省略相同或相似特征的详细描述，并且相同或相似附图标记指代相同或类似组件。绘示于图6中的膜上芯片封装件100d与绘示于图1中的膜上芯片封装件100之间的主要区别描述如下。
在一些实施例中，膜上芯片封装件100d可还包含衬底180，衬底180连接到柔性膜110的外围区。衬底180电连接到第一图案化电路层120。在一些实施例中，衬底180可与第二图案化电路层140电绝缘。或者，衬底180可电连接到第一图案化电路层120和第二图案化电路层两者。在本发明实施例中，柔性膜110还包含穿过柔性膜110以电连接第一图案化电路层120和第二图案化电路层140的多个通孔116。因此，衬底180连接到第一图案化电路层120，且通过通孔116电连接到第二图案化电路层。在一些实施例中，衬底180可为玻璃衬底、印刷电路板或任何其它合适的衬底。
图7示出根据本公开的实施例的膜上芯片封装件的截面视图。应注意，绘示于图7中的膜上芯片封装件100e包含许多与先前提到的图1的膜上芯片封装件100相同或相似的特征。出于清楚以及简单的目的，可省略相同或相似特征的详细描述，并且相同或相似附图标记指代相同或类似组件。绘示于图7中的膜上芯片封装件100e与绘示于图1中的膜上芯片封装件100之间的主要区别描述如下。
在一些实施例中，膜上芯片封装件100e可还包含第一衬底180和第二衬底190。第一衬底180连接到第一表面112的外围区，且第二衬底190连接到第二表面114的外围区。衬底180电连接到第一图案化电路层120，且第二衬底190电连接到第二图案化电路层140。在一些实施例中，第一衬底180可与第二衬底190电绝缘。或者，衬底180可通过至少一个通孔(例如图6中所绘示的通孔116)电连接到第二衬底190。在一些实施例中，第一衬底180和第二衬底190可为玻璃衬底、印刷电路板或其组合。
总之，根据本公开的膜上芯片封装件的实施例，芯片可安装在柔性膜的两个相对表面上。这可提高柔性膜的两侧的空间使用，从而可改提高膜上芯片封装件的空间利用效率。另外，根据一些实施例，通过布置通孔来将图案化电路层电连接在柔性膜的两个相对表面上，可显着提高膜上芯片封装件的设计灵活性。
所属领域的技术人员将显而易见，可以在不脱离本公开的范围或精神的情况下对本公开的结构作出各种修改和变化。鉴于以上内容，希望本公开涵盖本公开的修改和变化，只要所述修改和变化落入所附权利要求书和其等效物的范围内。

Claims (11)

1.一种膜上芯片封装件，其特征在于，包括：
柔性膜，包括第一表面以及与所述第一表面相对的第二表面；
第一图案化电路层，设置在所述第一表面上；
一个或多个第一芯片，安装在所述第一表面上且电连接到所述第一图案化电路层；
第二图案化电路层，设置在所述第二表面上；以及
一个或多个第二芯片，安装在所述第二表面上且电连接到所述第二图案化电路层，其中所述一个或多个第一芯片安装在所述第一表面的第一安装区上，所述一个或多个第二芯片安装在所述第二表面的第二安装区上，且所述第一安装区从俯视方向来看与所述第二安装区不重叠，其中所述柔性膜还包括电连接所述第一图案化电路层以及所述第二图案化电路层的一个或多个通孔。
2.根据权利要求1所述的膜上芯片封装件，还包括第一阻焊层，所述第一阻焊层设置在所述第一图案化电路层上且暴露所述第一图案化电路层中安装所述一个或多个第一芯片的部分。
3.根据权利要求1所述的膜上芯片封装件，还包括第二阻焊层，所述第二阻焊层设置在所述第二图案化电路层上且暴露所述第二图案化电路层中安装所述一个或多个第二芯片的部分。
4.根据权利要求1所述的膜上芯片封装件，其中所述一个或多个第一芯片的数目为多个。
5.根据权利要求4所述的膜上芯片封装件，其中所述多个第一芯片以并排的方式安装在所述第一表面上。
6.根据权利要求1所述的膜上芯片封装件，其中所述一个或多个第二芯片的数目为多个。
7.根据权利要求6所述的膜上芯片封装件，其中所述多个第二芯片以并排的方式安装在所述第二表面上。
8.根据权利要求1所述的膜上芯片封装件，还包括连接到所述柔性膜的外围区的衬底，且所述衬底电连接到所述第一图案化电路层及/或所述第二图案化电路层。
9.根据权利要求8所述的膜上芯片封装件，其中所述衬底包括玻璃衬底或印刷电路板。
10.根据权利要求8所述的膜上芯片封装件，其中所述柔性膜还包括电连接所述第一图案化电路层以及所述第二图案化电路层的多个通孔。
11.根据权利要求1所述的膜上芯片封装件，还包括连接到所述第一表面的外围区的第一衬底以及连接到所述第二表面的外围区的第二衬底，其中所述第一衬底电连接到所述第一图案化电路层，且所述第二衬底电连接到所述第二图案化电路层。
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US20200135695A1 (en) 2020-04-30

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