TW200406050A - Selective C4 connection in IC packaging - Google Patents

Selective C4 connection in IC packaging Download PDF

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Publication number
TW200406050A
TW200406050A TW092120017A TW92120017A TW200406050A TW 200406050 A TW200406050 A TW 200406050A TW 092120017 A TW092120017 A TW 092120017A TW 92120017 A TW92120017 A TW 92120017A TW 200406050 A TW200406050 A TW 200406050A
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Taiwan
Prior art keywords
contact
selected position
top surface
substrate
patent application
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TW092120017A
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Chinese (zh)
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TWI226691B (en
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Stephen W Macquarrie
Irving Memis
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Ibm
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Publication of TWI226691B publication Critical patent/TWI226691B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/485—Adaptation of interconnections, e.g. engineering charges, repair techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/05573—Single external layer
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
    • H05K1/0256—Electrical insulation details, e.g. around high voltage areas
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
  • Details Of Connecting Devices For Male And Female Coupling (AREA)
  • Control And Other Processes For Unpacking Of Materials (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

In an integrated circuit package employing solder bump technology, a metal layer placed on the surface of a substrate below an array of bonding pads is split and displaced from its axis at selected locations to preserve electrical continuity, but to also lower the height of an insulating solder mask layer at those locations.

Description

200406050 玖、發明說明： 【發明所屬之技術領域】 本發明係有關於封裝積體電路，更明確地說，有關於 ^ 被稱為’’覆晶接合”或c 4之連接技術。 於製造用以連接積體電路（IC)組之基材的製程中，製 造者有時在積體電路的底部上，完成與銲錫凸塊連接點之 選擇接觸。例如，其中可能有一組類似產品，其具有與標 準曰曰片不同之連接點，使得在晶片上之第k個凸塊在部份 封裝中被使用，而在其他封裝中則不被使用。 於過去’如第3圖之剖面圖所示，一具有銲錫凸塊接 觸30之錫球陣列的晶片1〇(稱為，，覆晶接合，，技術或c4技 術）將全部被銲接至在基材頂表面135上之對應接觸陣列 之金屬接觸墊11 〇。於此時，該晶片將必須只針對所用 之接觸加以设計及製造。美國專利第6,229,2 1 9號案例示 "有不規則組之接觸在底部之不同晶片。所有在每一晶片 即晶片上之第k槽有一空位，而容許兩 在第k位置之接觸與在該晶片上之空位 上^接觸係被黏結至在封裝上之對應接觸。該封裝藉由令 在日日片上有空位，即晶片上之笙 因此，在第k 擔間並未形成黏結。200406050 发明 Description of the invention: [Technical field to which the invention belongs] The present invention relates to a packaged integrated circuit, and more specifically, to a connection technology called ^ flip-chip bonding or c 4. For manufacturing use In the process of connecting the substrate of the integrated circuit (IC) group, the manufacturer sometimes completes the selective contact with the solder bump connection point on the bottom of the integrated circuit. For example, there may be a group of similar products that have The connection point is different from the standard chip, so that the k-th bump on the chip is used in some packages and not used in other packages. In the past, as shown in the cross-sectional view of Figure 3 A wafer 10 (referred to as, flip-chip bonding, technology, or c4 technology) with a solder ball array of solder bump contacts 30 will all be soldered to the metal contacts of the corresponding contact array on the top surface 135 of the substrate Pad 11 〇. At this time, the wafer will have to be designed and manufactured only for the contacts used. US Patent No. 6,229, 2 1 9 case " There are irregular sets of contacts on the bottom of different wafers. All in Every chip is The k-th slot on the wafer has a vacancy, and the two contacts at the k-th position and the ^ contact on the wafer are allowed to be bonded to the corresponding contacts on the package. The package has vacancies on the Japanese-Japanese film by That is to say, Sheng on the wafer therefore did not form a bond between the kth carriers.

但未被 。這表 。另外，在基 或者，一晶片 使用之接觸將為，，浮 示這接觸墊11 〇有 200406050 材上之金屬代表可能影響晶片操作的電容值。對於形成晶 片接觸之不同掩模，去除在晶片底部上之接觸將很浪費成 本。在曰曰片成形後去除接觸將需要額外之處理，並可能會 損及該晶片。去除在該位置之接觸墊1 1 0為一可能，但有 可此使知锡凸塊3 0流動以短路鄰近接觸，或已經製造於 接=塾110下之導孔，甚至以銲錫掩模130之出現，一傳 充’:電層破 >儿積並以微影方式作出圖帛。於此先前技藝中 ’予錫掩奴係如傳統被顯示為分離銲錫凸 凸塊接觸之對應金屬塾110。 期 【發明内容】 ^發明關係於一種絕緣開在IC之底 金屬内連H 合上銲錫掩模，對基材之頂面上之 、、、乍出圖案，以隔離開未使用之銲錫凸塊。 本發日月> 屬内連線：寺性為改變在未使用晶片接觸下通過之金 低在選定位置 以在介電銲錫掩模中形成一下凹，以降 位置之銲錫掩模之高度。 本發g月> s 電層放置》曰ΰ _特性為將銲錫掩模作出圖案，以將-介 、曰曰片上之一接觸與在封裝上之對應接觸之間。 【實施方式】 剖面圖 ，曰®，其中顯示- 1C封裝基材一部份之 至該封搫、，曰曰片1 0係經由一組C4銲錫凸塊3 0連接 凸塊黏結至一陣列之連接墊1 1 0。連接墊被連 200406050 接至内連線，其向下延伸穿過基材的頂面135並連接該所 示ic至其他IC及/或外面世界。銲錫掩模13〇為一介電 層，其係在頂面上之導體被作出圖案後並在晶片被黏結之 前被放下。其藉由包圍接觸墊110而隔離開銲錫凸塊3〇。 鲜錫掩模1 3 0在金屬層1 1 0被作出圖案後被放下，然 後’藉由曝露至適當特徵之光而作出圖案，然後，在作出 圖案後顯影。可以由第3圖看出，將銲錫掩模作出圖案的 方式為在銲錫凸塊間之分割及隔離特性，在每一接觸塾 U〇旁形成一壁。於第3圖之剖面圖中，這些銲錫球均未 為金屬1 1 0所短路。.如果，有金屬丨丨〇延伸於接觸間之情 形，層30將於其通過金屬n〇層上之處略高。 先前技藝之特性為1C腳位排列之修改（或至銲锡凸塊 之連接）很昂貴，成本因素之考量指示仍保有銲錫-接觸j i 〇 連接。因此，接著表示附著至晶片1 0之錫球係被銲接至 在該表面上之接觸110，因此，表示藉由在基材上之連接 作用，而具有電容加至晶片上的問題。熟習於本技藝者得 知一接觸墊110典型被連接至一向下延伸穿過基材的導 孔’使得有相當量之區域係與錫球3 0作電氣接觸。 依據本發明，在不改變1C的配置下，可容許在基材 上之不同連接，藉由一不會干擾晶片操作之圖案化介電 質，以隔離開在晶片上之未使用銲錫凸塊。 現參考第1圖，其中顯示依據本發明之封裝基材區域 的平面圖，其中，有一 3 x7陣列之接觸墊1 10，以配合— 特定1C之標準I/O。然而，並非所有接觸均被使用。於 200406050 此例子中，中間列之兩接觸未使用。 一由左至右沿著陣列中間列通過的粗線][2 〇代 電内連線’其係依據予以實施之系統需要（連接接觸 4 6及7)。於此例子中，該線通過七個鄰接之接觸 ;此例子中，兩個為編號1 2 2所表示之接觸位置未 並且位在具有六角形之線120區域中。所示佈局之 導電内連線件120偏移開晶片1 0上之銲錫凸塊之 即’其分開’在兩側間界定一六角形開口。在晶圓 作前被放下之銲錫掩模填入該六角開口並在銲錫掩 之頂表面的該位置中形成一下凹。該下凹包圍在盖 上之锡球並將之與周圍之連接器隔離，使得當加熱 玛流程序時，任何轉為熔化態導電材料被侷限。於 乍中 在晶片1 〇底部上之錫球3 0將會改變形狀， 低晶片10。於錫球30與接觸墊110間之介電材料 止電氣路徑之形成。因此，在ICl〇之下面之連接 擾，但未使用連接並未影響基材連接（例如藉由不 短路）或者晶片之操作（藉由改變電容值）。 參考第2圖之側視圖，通過内連線12〇所取之面 因此，並未顯示其剖面，即當該線通過墊丨丨〇時被 11()，及當通過六角形122時，被標示為122。因 圖中，兩區域1 3 5均顯示在每一側上之凸塊， _鍚掩模在内連線1 2 2上。 在第1圖之最上一列，盒子124界定在一接觸 區域，其將後封一由銲錫掩模材料所形成之介 表一導 1 - 3 > 位置。 使用， 功能為 位置； 黏結操 模125 i片10 及銲錫 黏結操 略微降 125防 未被干 想要之 A-A， 標示為 此，於 其中， 位置旁 電質墊 200406050 1 2 5者。此墊防止一路徑形成於在該位置之接觸1 1 0及 該位置上之晶片接觸之間。此配置係有用於當在晶片上 一接觸，其在此特定系統中並未使用，及在該基材中之 觸並未連接或可能短路至在該基材上或之中之另一内 線。 因此，本發明可以使用較大等級之晶片及/或基材 因為一具有一接觸1 1 〇連接至基材中之其他接線之堆疊 材仍可以被使用，及該基材將增加於晶片中之電路上之 容性負載（若有接觸的話）。同樣地，一短路於一系統版 中之晶片接觸Κ及L之基材中之内連線可能封閉，使 不具該短路之系統仍可以使用相同基材。 熟習於本技藝者可知並不需要一閉合六角形及單側 構將用以保留線1 2 0之連續性。線1 2 0並不必要為一直線 其可以具有一直角或其他形狀。一鑽石形、矩形、平行 邊形或其他形狀（較佳一閉合曲線）可以使用以替代六 形。 較佳地，銲錫掩模之厚度係足夠地厚，以防止電氣 觸，同時，也足夠薄，以使其他銲錫凸塊不會不與所黏 之墊1 1 0作接觸。因為銲錫凸塊將於黏結製程中迴流， 以，其也可允許部份公差本發明已經針對由IB Μ所開 之覆晶接合製程加以說明，但也可以使用其他技術，其 1C底部之一組接觸係被黏結至基材頂部上之一陣列者。 雖然，本發明已經以單一實施例方式加以說明，但 習於本技藝可以了解到本發明也可以在不脫離以下申請 在 有 接 連 基 電 本 得 結 > 四 角 接 結 所 發 中 熟 專 200406050 利範圍之精神及範圍下加以以各種版本實施。 【圖式簡單說明】 ’ 第1圖為依據本發明之結構的俯視圖。 、~ 第2圖為第1圖之剖面圖。 - 第3圖為對應於第2圖之先前技藝之剖面圖。 【元件代表符號簡單說明】 φ 10 晶片 30 銲錫凸塊 110 接觸墊 120 粗線 122 接觸位置 124 盒子 125 銲錫掩模層 130 銲錫掩模 135 頂面But not. This table. In addition, the contact used on a substrate or a wafer will be, indicating that this contact pad 11 has 200406050 metal on the material representing the capacitance value that may affect the operation of the wafer. For different masks that form wafer contacts, removing the contacts on the bottom of the wafer would be a waste of cost. Removing contact after the wafer has been formed will require additional processing and may damage the wafer. It is possible to remove the contact pad 1 1 0 at this position, but it is possible to make the solder bump 30 flow to short-circuit the adjacent contact, or it has been manufactured in the via hole under contact = 塾 110, even with a solder mask 130 The emergence, a pass charge ': electric layer break > children's product and make a picture by lithography. In this prior art, the 'Yu tin mask' system has traditionally been shown to separate the corresponding metal 塾 110 of the solder bump contact. [Contents of the invention] ^ The invention relates to an insulation opening on the bottom metal of the IC. H closes the solder mask, and the pattern on the top surface of the substrate is separated to isolate unused solder bumps. . This issue of the Sun & Moon> Inner wiring: The reason is to change the amount of gold that passes through the unused wafer to lower the selected position to form a depression in the dielectric solder mask to reduce the height of the solder mask in position. The present month > s electrical layer placement " ΰ characteristic is to pattern the solder mask to contact between one of the contacts on the chip and the corresponding contact on the package. [Embodiment] A cross-sectional view, ®, which shows-a part of the 1C packaging substrate to the seal, said chip 10 is bonded to an array through a set of C4 solder bumps 30 connecting bumps. Connection pad 1 1 0. The connection pad is connected to 200406050 to the interconnect, which extends down through the top surface 135 of the substrate and connects the IC shown to other ICs and / or the outside world. The solder mask 13 is a dielectric layer, and the conductors on the top surface are patterned and lowered before the wafer is bonded. It isolates the solder bumps 30 by surrounding the contact pads 110. The fresh tin mask 130 is lowered after the metal layer 110 is patterned, and then a pattern is formed by being exposed to light of appropriate characteristics, and then developed after patterning. As can be seen from Figure 3, the pattern of the solder mask is divided and isolated between the solder bumps, and a wall is formed next to each contact 塾 U0. In the cross-sectional view of Figure 3, none of these solder balls were shorted by the metal 110. If there is a case where the metal extends between the contacts, the layer 30 will pass slightly above the metal n0 layer. The characteristic of the previous technology is that the modification of the 1C pin arrangement (or the connection to the solder bumps) is expensive, and consideration of cost factors indicates that the solder-contact j i 〇 connection is still maintained. Therefore, it is shown that the solder ball attached to the wafer 10 is soldered to the contact 110 on the surface, and therefore, it indicates that there is a problem that capacitance is added to the wafer by the connection on the substrate. Those skilled in the art will know that a contact pad 110 is typically connected to a via hole 'that extends down through the substrate so that a considerable amount of area is in electrical contact with the solder ball 30. According to the present invention, without changing the configuration of 1C, different connections on the substrate can be tolerated, and an unused solder bump on the wafer can be isolated by a patterned dielectric that does not interfere with the operation of the wafer. Reference is now made to Fig. 1, which shows a plan view of a package substrate area according to the present invention, in which there is a 3 x 7 array of contact pads 1 10 to cooperate with-specific 1C standard I / O. However, not all contacts are used. In 200406050 this example, the two contacts in the middle column are not used. A thick line passing from left to right along the middle column of the array] [Gen 20 electrical interconnects' is based on the needs of the system being implemented (connection contacts 4 6 and 7). In this example, the line passes through seven adjacent contacts; in this example, two contact positions indicated by the numbers 1 2 2 are not located in the area of the line 120 having a hexagon. The conductive interconnects 120 of the layout shown are offset from the solder bumps on the wafer 10, i.e., 'their separation', define a hexagonal opening between the two sides. A solder mask put down before the wafer is filled fills the hexagonal opening and forms a depression in this position on the top surface of the solder mask. The depressions enclose the solder balls on the cover and isolate them from the surrounding connectors, so that when the Ma Liu process is heated, any conductive material that is turned into a molten state is limited. At Zachzhong, the solder ball 30 on the bottom of the wafer 10 will change shape and lower the wafer 10. The dielectric material between the solder balls 30 and the contact pads 110 prevents the formation of electrical paths. Therefore, the connection below IC10 disturbs, but the unused connection does not affect the substrate connection (for example, by not shorting) or the operation of the chip (by changing the capacitance value). Referring to the side view of Fig. 2, the face taken through the inner connecting line 120 is not shown in section, that is, it is 11 () when the line passes through the pad 丨 丨, and when it passes through the hexagon 122 Marked 122. In the figure, two areas 1 3 5 are shown on each side of the bump, _ 钖 mask on the interconnect 1 2 2. In the top column of Fig. 1, the box 124 defines a contact area which seals back a guide 1-3 > position formed by a solder mask material. Use, the function is the position; the bonding operation mold 125 i piece 10 and the solder bonding operation are slightly reduced. This pad prevents a path from being formed between the contact 110 at that location and the wafer contact at that location. This configuration is used when a contact is on the wafer, which is not used in this particular system, and the contact in the substrate is not connected or may be shorted to another extension on or in the substrate. Therefore, the present invention can use larger grade wafers and / or substrates because a stacked material with a contact 1 10 connected to other wiring in the substrate can still be used, and the substrate will be added to the wafer. Capacitive load on the circuit (if there is contact). Likewise, the interconnects in the substrate of a wafer contact K and L shorted in a system version may be closed, so that systems without the short circuit can still use the same substrate. Those skilled in the art know that there is no need for a closed hexagon and one-sided structure to preserve the continuity of the line 120. The line 1 2 0 is not necessarily a straight line and it may have a right angle or other shape. A diamond, rectangle, parallelogram, or other shape (preferably a closed curve) can be used instead of a hexagon. Preferably, the thickness of the solder mask is sufficiently thick to prevent electrical contact, and at the same time, it is thin enough so that other solder bumps do not come into contact with the adhered pad 110. Because the solder bump will be reflowed in the bonding process, it can also allow some tolerances. The present invention has been described for the flip-chip bonding process opened by IB M, but other techniques can also be used. Its 1C bottom group The contacts are bonded to an array on top of the substrate. Although the present invention has been described in terms of a single embodiment, it can be learned from the present technology that the present invention can also be obtained in a connected base without departing from the following application. The spirit and scope of the scope are implemented in various versions. [Brief Description of the Drawings] 'Figure 1 is a top view of a structure according to the present invention. , ~ Figure 2 is a sectional view of Figure 1. -Figure 3 is a sectional view corresponding to the prior art of Figure 2. [Simple description of component representative symbols] φ 10 chip 30 solder bump 110 contact pad 120 thick line 122 contact position 124 box 125 solder mask layer 130 solder mask 135 top surface

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Claims (1)

200406050 拾、申請專利範圍： 1. 一種用以連接積體電路的基材，其至少包含：一基材頂 面，具有至少一標準圖案陣列之接觸形成於其上，以及， 一圖案介電層，安排於該頂面上，該有圖案介電層被作 出圖案，以包圍並彼此隔離開一次組標準圖案陣列之接 觸，其中，一導電接觸内連線件係安排在該頂面上並電 氣連接至少部份之該陣列接觸，該接觸内連線件係由該 至少一陣列中之接觸位置的至少一選定位置位移，及該 有圖案介電層覆蓋該至少一選擇位置，其中在頂面之選 定位置之積體電路接觸係與位在選定位置之接觸陣列之 接觸隔離開。 2. 如申請專利範圍第1項所述之基材，其中上述之接觸内 連線件係由包圍該至少一選定位置之閉合曲線中之至少 一選定位置位移開，其中，該介電層在該閉合曲線内之 該至少一選定位置處有一下凹。 3 .如申請專利範圍第1項所述之基材，其中安排在頂面及 電氣連接至一次組接觸之該導電内連線件延伸通過至少 一其所未連接之未連接接觸。 4.如申請專利範圍 '第3項所述之基材，其中上述之導電内 連線件形成一閉合曲線，包圍住該至少一未連接接觸。 9 1¾¾ 200406050 5 ·如申請專利範圍第4項所述之基材，其中上述之導電内 連線件形成一六角形，包圍住該至少一未連接接觸。 6 ·如申請專利範圍第4項所述之基材，其中上述之導電内 連線件形成一四邊形，包圍住該至少一未連接接觸。 7.—種用以連接積體電路的基材，其具有一基材頂面，具 有至少一標準圖案陣列之接觸形成於其上及一圖案化介 電層安排於該頂面上，該圖案化介電層係作出圖案以包 圍並隔離開——次組之標準圖案陣列之接觸，其中該圖案 化之介電層覆蓋該至少一選定位置，其中一在該頂面之 選定位置的積體電路接觸係與位在該選定位置之陣列接 觸之一接觸隔絕。 8 .如申請專利範圍第7項所述之基材，其中上述之圖案化 介電質係為一形成一閉合曲線之導電内連線件所閉合， 該曲線包圍該至少一未連接接觸。 9.如申請專利範圍第8項所述之基材，其中上述之導電内 連線件形成一六角形，包圍住該至少一未連接接觸。 1 0.如申請專利範圍第9項所述之基材，其中上述之導電 内連線件形成一四邊形，包圍住該至少一未連接接觸。 10 200406050 11. 一種製造一基材的方法，該基材用以連接具有一基材 頂面之積體電路，具有至少一標準圖案陣列之接觸形成 於其上及一圖案介電層安排於該頂面上，該方法至少包 含步驟： 提供一組内連線給一基材，該内連線連接至少部份之 標準圖案陣列之接觸，形成一導電接觸内連線件安排於 該頂面上並電氣連揍該至少陣列接觸之部份，該接觸内 連線件係由在該至少一陣列中之接觸位置的至少一選定 位置位移開； 對一介電層作出圖案，以包圍並與該標準圖案陣列之 接觸的一次組分隔，並覆蓋該玉少一選定位置，其中在 一 1C之底面上之一積體電路接觸在該頂面之選定位置 處係與位在該選定位置之陣列接觸之接觸隔離。 1 2.如申請專利範圍第 9項所述之方法，其中上述之接觸 内連線件係位移開在一包圍住該至少一選定位置之閉合 曲線中的該至少一選定位置。 1 3 .如申請專利範圍第9項所述之方法，其中上述之介電 層在該至少一選定位置之閉合曲線内具有一下凹。 11200406050 Patent application scope: 1. A substrate for connecting an integrated circuit, which at least includes: a substrate top surface, at least one contact having a standard pattern array formed thereon, and a patterned dielectric layer Arranged on the top surface, the patterned dielectric layer is patterned to surround and isolate one another from a set of standard pattern array contacts, wherein a conductive contact interconnect is arranged on the top surface and electrically At least a portion of the array contacts are connected, the contact interconnects are displaced by at least one selected position of the contact positions in the at least one array, and the patterned dielectric layer covers the at least one selected position, with a top surface The integrated circuit contact at the selected position is isolated from the contact of the contact array at the selected position. 2. The substrate according to item 1 of the scope of patent application, wherein the above-mentioned contact interconnects are displaced from at least one selected position in a closed curve surrounding the at least one selected position, wherein the dielectric layer is at There is a depression at the at least one selected position in the closed curve. 3. The substrate according to item 1 of the scope of patent application, wherein the conductive interconnector arranged on the top surface and electrically connected to the primary contact extends through at least one unconnected contact to which it is not connected. 4. The substrate according to item 3 of the scope of the patent application, wherein the above-mentioned conductive interconnector forms a closed curve surrounding the at least one unconnected contact. 9 1¾¾ 200406050 5 · The substrate according to item 4 of the scope of patent application, wherein the above-mentioned conductive interconnects form a hexagon to surround the at least one unconnected contact. 6. The substrate according to item 4 of the scope of patent application, wherein the above-mentioned conductive interconnector forms a quadrangle to surround the at least one unconnected contact. 7. A substrate for connecting an integrated circuit, which has a substrate top surface, contacts having at least one standard pattern array formed thereon, and a patterned dielectric layer arranged on the top surface, the pattern The patterned dielectric layer is patterned to surround and isolate the contacts of a sub-group of standard pattern arrays, wherein the patterned dielectric layer covers the at least one selected position, one of which is a product at the selected position on the top surface The circuit contact is isolated from one of the array contacts at the selected location. 8. The substrate according to item 7 of the scope of the patent application, wherein the patterned dielectric is closed by a conductive interconnect member forming a closed curve, the curve surrounding the at least one unconnected contact. 9. The substrate according to item 8 of the scope of the patent application, wherein the above-mentioned conductive interconnector forms a hexagonal shape to surround the at least one unconnected contact. 10. The substrate according to item 9 of the scope of the patent application, wherein the above-mentioned conductive interconnects form a quadrangle to surround the at least one unconnected contact. 10 200406050 11. A method for manufacturing a substrate for connecting an integrated circuit having a top surface of the substrate, a contact having at least one standard pattern array formed thereon, and a pattern dielectric layer arranged thereon On the top surface, the method includes at least the steps of: providing a set of interconnects to a substrate, the interconnects connecting at least part of the contacts of the standard pattern array to form a conductive contact interconnecting member arranged on the top surface And electrically connecting the portion of the at least array contact, the contact interconnects being displaced from at least one selected position of the contact position in the at least one array; patterning a dielectric layer to surround and communicate with the The group of contacts of the standard pattern array is separated once and covers the selected position of the jade. One of the integrated circuit contacts on a 1C bottom surface is in contact with the array at the selected position at the selected position on the top surface. The contact is isolated. 1 2. The method according to item 9 of the scope of patent application, wherein the above-mentioned contact interconnects are displaced at the at least one selected position in a closed curve surrounding the at least one selected position. 13. The method according to item 9 of the scope of patent application, wherein the above-mentioned dielectric layer has a depression in the closed curve of the at least one selected position. 11
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