CN100423250C - Double layer lead wire package structure and its producing method - Google Patents
Double layer lead wire package structure and its producing method Download PDFInfo
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- CN100423250C CN100423250C CNB200610096808XA CN200610096808A CN100423250C CN 100423250 C CN100423250 C CN 100423250C CN B200610096808X A CNB200610096808X A CN B200610096808XA CN 200610096808 A CN200610096808 A CN 200610096808A CN 100423250 C CN100423250 C CN 100423250C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
Abstract
This invention provides a double layer lead package structure and its manufacturing method, in which, a compatible weld pad is covered on the glass forming a cavity, the glass is adhered with a semiconductor, element on the chip is in the cavity, the insulation material at the back of the chip combines the second layer of glass with the chip, and the glass is coated with insulation material and a metal layer is deposited on it and isolated by open-ends, a welded mask is covered on the metal layer and opened with an open-end, part of the metal layer is exposed , the second metal layer is deposited on the open-end and the welded-mask of a V-shape channel and covered with the mask attached with welded humps, the compatible weld pad is connected with the first and the second metal layers.
Description
Technical field
The present invention relates to a kind of wafer level chip scale package structure, relate in particular to the method for a kind of double layer lead wire package structure and this encapsulating structure of manufacturing.
Background technology
Along with the raising of electronic device microminiaturization and circuit integration density in the semi-conductor industry, chip size packages technology (CSP) has obtained developing rapidly, and its package dimension is similar to die size.Traditional encapsulation technology such as wire bonding, automatic band carry a combined techniques (TAB), flip-chip, all have shortcoming separately.Carry in the combined techniques at wire bonding and automatic band, the size of semiconductor packages will be much larger than the original size of chip.Flip-Chip Using faces down electronic component by the conductive solder projection of chip, make circuit side down, be installed in direct electric connection on substrate/supporting body, Flip-Chip Using can cause breaking of soldered ball junction owing to big thermal expansion mismatch between wafer and the substrate.Chip size packages can directly encapsulate on single chip; Also can be after encapsulating on the full wafer wafer, the chip that the wafer cutting that encapsulated has been obtained encapsulating again.This is crystal wafer chip dimension encapsulation (WLCSP) a kind of title in back.Crystal wafer chip dimension encapsulation normally is scattered in a large amount of metal soldered balls that the face battle array is arranged to the compatible pad of peripheral arrangement on the semiconductor chip by distributed process again, is called as solder-bump sometimes.Weldering film projection on the WLCSP surface is bigger on diameter, and spacing is farther between the projection, so the assembling of the printed circuit board (PCB) of WLCSP is correspondingly more solid.The WLCSP technology is compared with other encapsulated types, has more superior electrical property and lower manufacturing cost.
ShellOP, the ShellOC of Israel Shellcase company exploitation and the advanced WLCSP technology of ShellUT are mainly used to encapsulating optical and imageing sensor, for example are integrated in charge-coupled device (CCD) or cmos imager on the silicon wafer.At present, CCD and cmos image sensor are widely applied in electronic product.Different with other method for packing, the packaging technology of Shellcase company does not need lead frame or wire bond.In brief, the ShellOP processing procedure adopts the sandwich structure of glass/silicon/glass, obtains the image sensing ability, and the protection imageing sensor is avoided the pollution of external environment condition.The ShellOC processing procedure adopts identical sandwich structure, but on first glassy layer, made up extra cavity, be used to hold above-mentioned imageing sensor and the lenticule on it, image quality can further improve like this, so ShellOC is the technical scheme that a kind of encapsulation has lenticular imageing sensor.In ShellUT encapsulation, cavity still is retained, but second glassy layer is removed, so that relevant packaging height reduces.
The cross-sectional view of ShellOC packaged chip as shown in fig. 1 can be observed, and the top glass 5 that has cavity wall covers the silicon 20 that has compatible pad 15 with protection, and epoxy resin 25 makes second glass 30 combine with chip 20.Before this combination, used photoetching technique and plasma etching technology, the compatible pad 15 on the chip 20 is partly exposed like this.After solder mask is applied on the glass 30, carries out the hemisection fluting subsequently, thereby, make reverse lead-in wire 40 with the "T"-shaped compatible pad 15 that is electrically communicated to by deposition.The 40 coated protectiveness that have that go between are welded film masks 45, and solder mask 45 is dielectric materials, can stop lead-in wire 40 to contact with outside, makes its electric insulation, and protection wire surface opposing erosion.Solder-bump 50 is pasted in lead-in wire 40 bottoms, is suitable for well-known method and carries out the assembling of printed circuit board (PCB); Solder-bump 50 can be with known method, and for example screen painting forms.
In the WLCSP technology, only used the individual layer lead-in wire.Because the space of solder-bump face is limited, the quantity of compatible pad also is restricted.
Summary of the invention
The purpose of this invention is to provide a kind of crystal wafer chip dimension double layer lead wire package structure and manufacture method thereof, thereby can save more space at the solder-bump face of packaged chip and be used to the layout that goes between, allowing the application of more compatible pads on the unit are, and can significantly improve the reliability of electrical connection.
Purpose of the present invention is achieved through the following technical solutions:
Double layer lead wire package structure comprises: which is provided with the crystal substrates of chip, chip periphery is gathered and is arranged compatible pad; Be located at the first glass packaging layer in chip and substrate front; Be located at the insulation material layer of substrate back; It is characterized in that: at described insulation material layer backside deposition the first metal layer is arranged, described the first metal layer middle position is provided with perforate; Be coated with first solder mask layer having on the first metal layer back side of perforate, described first solder mask layer is provided with at least one perforate, makes the first metal layer have part surface to be exposed by the perforate on described first solder mask layer; The side of described encapsulating structure and the backside deposition of the solder mask layer of perforate second metal level is arranged; Bottom at second metal level is provided with solder-bump, thereby makes described compatible pad by described second metal level and described the first metal layer and described solder-bump electric connection.
Further, above-mentioned double layer lead wire package structure, electric connection between described second metal level and the described compatible pad is "T"-shaped connection, electric connection between described the first metal layer and described second metal level is " L-U " shape and connects, and described compatible pad is " T-L-U " shape to the electric connection between the described solder-bump and connects.
Further, above-mentioned double layer lead wire package structure, electric connection between described second metal level and the described compatible pad is "T"-shaped connection, electric connection between described the first metal layer and described second metal level is " T-2U " shape and connects, and described compatible pad is " 2T-2U " shape to the electric connection between the described solder-bump and connects.
Further, above-mentioned double layer lead wire package structure is provided with cavity wall between described crystal substrates and the described first glass packaging layer.
Further, above-mentioned double layer lead wire package structure is provided with the second glass packaging layer between described insulation material layer and described the first metal layer; Between described second glass packaging layer and described the first metal layer, be provided with second solder mask layer, playing the stress buffer effect, and strengthen the adhesive ability of the first metal layer.
Further, above-mentioned double layer lead wire package structure is provided with cavity wall between described crystal substrates and the described first glass packaging layer; Between described insulation material layer and described the first metal layer, be provided with the second glass packaging layer; Between described second glass packaging layer and described the first metal layer, be provided with second solder mask layer, playing the stress buffer effect, and strengthen the adhesive ability of the first metal layer.
Again further, the manufacture method of above-mentioned double layer lead wire package structure is characterized in that: a wafer is provided, and described wafer comprises a plurality of crystal substrates which is provided with chip, and each described on-chip chip periphery is provided with a plurality of compatible pads; Chip on described wafer and substrate front are provided with the first glass packaging layer; Substrate back at described wafer is provided with insulation material layer; At described insulation material layer backside deposition the first metal layer, and perforate is set at described the first metal layer middle position; Having covering first solder mask layer on the first metal layer back side of perforate, on described first solder mask layer, at least one perforate is set, make the first metal layer have part surface to be exposed by the perforate on described first solder mask layer; At the side of the lamination of forming by compatible pad, insulation material layer, the first metal layer and first solder mask layer and backside deposition second metal level of the solder mask layer of perforate; Bottom at second metal level is provided with solder-bump, thereby makes described compatible pad by described second metal level and described the first metal layer and described solder-bump electric connection; Cut described wafer, form single wafer level packaging structure.
Again further, the manufacture method of above-mentioned double layer lead wire package structure is characterized in that: a wafer is provided, and described wafer comprises a plurality of crystal substrates which is provided with chip, and each described on-chip chip periphery is provided with a plurality of compatible pads; Chip on described wafer and substrate front are provided with the first glass packaging layer; On the described first glass packaging layer, form cavity wall, thereby between described crystal substrates and the described first glass packaging layer, form the cavity that holds on-chip chip; Substrate back at described wafer is provided with insulation material layer; At described insulation material layer backside deposition the first metal layer, and perforate is set at described the first metal layer middle position; Having covering first solder mask layer on the first metal layer back side of perforate, on described first solder mask layer, at least one perforate is set, make the first metal layer have part surface to be exposed by the perforate on described first solder mask layer; At the side of the lamination of forming by compatible pad, insulation material layer, the first metal layer and first solder mask layer and backside deposition second metal level of the solder mask layer of perforate; Bottom at second metal level is provided with solder-bump, thereby makes described compatible pad by described second metal level and described the first metal layer and described solder-bump electric connection; Cut described wafer, form single wafer level packaging structure.
Again further, the manufacture method of above-mentioned double layer lead wire package structure is characterized in that: a wafer is provided, and described wafer comprises a plurality of crystal substrates which is provided with chip, and each described on-chip chip periphery is gathered and arranged compatible pad; Chip on described wafer and substrate front are provided with the first glass packaging layer; Substrate back at described wafer is provided with insulation material layer; At the described insulation material layer back side the second glass packaging layer is set; At the described second glass packaging layer back side second solder mask layer is set, then at the described second solder mask layer backside deposition the first metal layer; And perforate is set at described the first metal layer middle position; Having covering first solder mask layer on the first metal layer back side of perforate, on described first solder mask layer, at least one perforate is set, make the first metal layer have part surface to be exposed by the perforate on described first solder mask layer; At the side of described encapsulating structure and backside deposition second metal level of the solder mask layer of perforate; Bottom at second metal level is provided with solder-bump, thereby makes described compatible pad by described second metal level and described the first metal layer and described solder-bump electric connection; Cut described wafer, form single wafer level packaging structure.
Again further, the manufacture method of above-mentioned double layer lead wire package structure is characterized in that: a wafer is provided, and described wafer comprises a plurality of crystal substrates which is provided with chip, and each described on-chip chip periphery is provided with a plurality of compatible pads; Chip on described wafer and substrate front are provided with the first glass packaging layer; On the described first glass packaging layer, form cavity wall, thereby between described crystal substrates and the described first glass packaging layer, form the cavity that holds on-chip chip; Substrate back at described wafer is provided with insulation material layer; At the described insulation material layer back side the second glass packaging layer is set; At the described second glass packaging layer back side second solder mask layer is set, then at the described second solder mask layer backside deposition the first metal layer; And perforate is set at described the first metal layer middle position; Having covering first solder mask layer on the first metal layer back side of perforate, on described first solder mask layer, at least one perforate is set, make the first metal layer have part surface to be exposed by the perforate on described first solder mask layer; At the side of described packaging system and backside deposition second metal level of the solder mask layer of perforate; Bottom at second metal level is provided with solder-bump, thereby makes described compatible pad by described second metal level and described the first metal layer and described solder-bump electric connection; Cut described wafer, form single wafer level packaging structure.
Again further, the manufacture method of above-mentioned double layer lead wire package structure, electric connection between described second metal level and the described compatible pad is "T"-shaped connection, electric connection between described the first metal layer and described second metal level is " L-U " shape and connects, and described compatible pad is " T-L-U " shape to the electric connection between the described solder-bump and connects.
Again further, the manufacture method of above-mentioned double layer lead wire package structure, electric connection between described second metal level and the described compatible pad is "T"-shaped connection, electric connection between described the first metal layer and described second metal level is " T-2U " shape and connects, and described compatible pad is " 2T-2U " shape to the electric connection between the described solder-bump and connects.
The outstanding substantive distinguishing features and the obvious improvement of technical solution of the present invention is mainly reflected in:
1. realize the application of the sizable unit are quantity of compatible pad, be used for lead design can save more space at the Lead-on-Chip face;
2. produce more reliable electrical connection, significantly improve the reliability of electrical connection.
Description of drawings
Below in conjunction with accompanying drawing technical solution of the present invention is described further:
Fig. 1: background technology has the schematic cross-section of the ShellOC packaged chip of one deck pin configuration and "T"-shaped combination thereof;
Fig. 2～13: the packaging technology flow chart of the ShellOC double layer lead wire package structure of " T-L-U " shape combination;
Figure 14～17: the schematic diagram of the ShellOC packaged chip of the double layer lead wire package structure of " 2T-2U " shape combination;
Figure 18: the schematic perspective view of the ShellOC double layer lead wire package structure of " 2T-2U " shape combination;
Figure 19: the schematic cross-section of the ShellUT packaged chip of the double layer lead wire package structure of " 2T-2U " shape combination.
The implication of each Reference numeral sees the following form among the figure:
| Reference numeral | Implication | Reference numeral | Implication | Reference | Implication | |
| 1 | |
5 | First |
10 | |
|
| 15 | |
20 | |
25 | Insulation material layer |
| Reference numeral | Implication | Reference numeral | Implication | | Implication | |
| 30 | Second |
35 | First |
36 | Second |
|
| 40 | The |
41 | |
45 | The protectiveness |
|
| 50 | Solder- |
60 | "T"- |
65 | " L " |
|
| 70 | " U " shape tie point |
Embodiment
The invention provides a kind of double-deck lead structure and manufacture method thereof, be used for substituting the existing individual layer outside lead of Shellcase wafer-level chip scale package technology structure.Wherein have the double-deck lead structure of combination of T-L-U shape and the combination of 2T-2U shape, be described as first-selected embodiment of the present invention; Have such double-deck lead structure, can realize the application of the sizable unit are quantity of compatible pad, be used for lead design, produce more reliable electrical connection simultaneously, significantly improve the reliability of electrical connection to save more space at the packaged chip lower surface.
Embodiment 1:
The ShellOC double layer lead wire package structure of " T-L-U " shape combination, as shown in figure 13, at the densely covered compatible pad 15 of arranging of chip periphery, first glassy layer 5 is bonding with chip 20, optics on the chip/image sensor element 1 is contained in the cavity, the insulation material layer 25 of chip back combines second layer glassy layer 30 with chip 20, form " glass-silicon-glass " sandwich structure; On second glassy layer 30, apply second solder mask layer 36, playing the stress buffer effect, and strengthen the adhesive ability of the first metal layer; Deposit the first metal layer 40 on second solder mask 36 and separated by perforate, form on the metal level 40 of perforate and be covered with first solder mask layer 35, solder mask layer 35 is also by perforate, and the part surface of the first metal layer 40 exposes; The side of compatible pad 15 is exposed and is formed the V-arrangement raceway groove; Second metal level 41 is deposited on the solder mask of perforate and V-arrangement raceway groove, is coated with protectiveness solder mask layer 45 on second metal level 41, adheres to solder-bump 50; The exposed side of compatible pad is electrically connected to second metal level 41, is "T"-shaped tie point; Compatible pad 15 and the first metal layer 40 and second metal level, 41 electric connections.
It should be noted that the first metal layer 40 is " L-U " shape with the electric connection of second metal level 41 and is connected, form the double layer lead wire package structure of " T-L-U " shape combination, as shown in figure 13.Wherein, glassy layer 5 is to optical transparency, but second glassy layer 30 is not had these requirements, and the thermal coefficient of expansion of two glass is close with semiconductor chip material as far as possible, and solder mask all is resistant to elevated temperatures, and metal level generally is Al, but is not limited to Al.
A preferred embodiment of the present invention is based on the SchellOC technology, and its packaging technology flow process is shown in Fig. 2～13.That is:
At first, on first glassy layer 5, form cavity wall 10, as Fig. 2;
After this, the back side of chip 20 adopts photoetching and plasma technology to be selectively etched, and the part surface of compatible pad 15 passes and is formed on groove therebetween and is exposed, as Fig. 4;
Insulating material 25 abundant filling grooves also cover the silicon chip inclined-plane and the expose portion of compatible pad 15, and then, second layer glass 30 combines with silicon 20, as Fig. 5;
So the ShellOC technology produces " glass-silicon-glass " sandwich structure.Be applied to glass 30 as the mechanical damping layer solder mask 36 that is used for follow-up fluting, as Fig. 6;
Next, carry out metal deposition 40, replace the fluting in the standard technology flow process, as Fig. 7;
After this layer metal deposition, on the first metal layer 40, build perforate by photoetching technique, as Fig. 8;
Afterwards, the solder mask 35 of a Photoimageable is placed on the metal level 40 that forms perforate, and metal level 40 is filled with the perforate of solder mask separately isolates, as Fig. 9;
On second metal level 41, coat protectiveness solder mask 45, as Figure 12;
Adhere to solder-bump 50, as Figure 13;
After above-mentioned encapsulation process technology is finished, by the method for section packaged chip is separated from entire wafer, so far, encapsulating structure makes up and finishes again.
Description by above technical scheme as seen, the present invention is by change route and the electric connection lead channels that reconfigures in the double-decker, compatible pad 15 along gap edge directly with second metal level, 41 electric connections, simultaneously, compatible pad 15 also with the first metal layer 40 electric connections." T ", " L " and " U " shape binding sequence realization of the latter's electric connection by shown in the figure circles mark, be called have " T ", the double-deck lead structure of " L " and " U " shape combination.Encapsulation step afterwards; the same with standard Shellcase type encapsulation process; on second metal level 41, coat protectiveness solder mask 45 successively, adhere to solder-bump 50; electric connection between second metal level 41 and the compatible pad 15 is "T"-shaped connection; electric connection between the first metal layer 40 and second metal level 41 is " L-U " shape and connects, and compatible pad 15 is " T-L-U " shape to the electric connection between the solder-bump 50 and connects.Clearly, the electric connection stability of this structure is better than structure shown in Figure 1.
Embodiment 2:
For further improving the electric connection reliability, electric connection between second metal level 41 and the compatible pad 15 is "T"-shaped connection, electric connection between the first metal layer 40 and second metal level 41 is " T-2U " shape and connects, and compatible pad 15 is " 2T-2U " shape to the electric connection between the solder-bump 50 and connects; Form the double layer lead wire package structure of " 2T-2U " shape combination.
Carry out and identical process shown in Fig. 2～9 with respect to the foregoing description, but after technology, on solder mask 35, construct the perforate (2 " U " shape) different, as Figure 14 with perforate shown in Figure 10 (1 " U " shape); Second metal level 41 is deposited on the solder mask of perforate and V-arrangement raceway groove then, so that compatible pad 15 and ground floor metal 40 and second metal level, 41 electric connections, as Figure 15; On second metal level 41, coat protectiveness solder mask 45, as Figure 16; Adhere to solder-bump 50, as Figure 17.So just, formed the double-deck lead structure with 2 " T " and 2 " U " electric connection mode, its stereogram as shown in figure 18.This encapsulating structure electrical connection properties is very reliable, even the T shape of bottom margin is in conjunction with breakage, electric connection still can remain intact.
Embodiment 3:
It should be noted that, double-deck lead structure with " T ", " L " and " U " shape and 2 " T ", 2 " L " and the combination of 2 " U " shape can be applicable to ShellUT and ShellOP encapsulation, Figure 19 is the schematic cross-section of the ShellUT packaged chip of " 2T-2U " form combination, its encapsulation process is similar to embodiment 1, so no longer be repeated in this description.
The present invention not only is confined to the foregoing description, and the example that provides only is preferred illustrative example.Allly comprise technical concept of the present invention, adopt equivalents or equivalence to replace and the technical scheme that forms, all drop within the rights protection scope of the present invention.
Claims (12)
1. double layer lead wire package structure comprises: which is provided with the crystal substrates of chip, the densely covered compatible pad [15] of arranging of chip periphery; Be located at the first glass packaging layer [5] in chip and substrate front; Be located at the insulation material layer [25] of substrate back; It is characterized in that: at described insulation material layer backside deposition the first metal layer [40] is arranged, described the first metal layer middle position is provided with perforate; Be coated with first solder mask layer [35] on the first metal layer back side of perforate having, described first solder mask layer [35] is provided with at least one perforate, makes the first metal layer have part surface to be exposed by the perforate on described first solder mask layer [35]; The side of described encapsulating structure and the backside deposition of the solder mask layer of perforate second metal level [41] is arranged; Be provided with solder-bump [50] in the bottom of second metal level, thereby make described compatible pad [15] by described second metal level [41] and described the first metal layer [40] and described solder-bump [50] electric connection.
2. double layer lead wire package structure according to claim 1, be characterised in that: the electric connection between described second metal level [41] and the described compatible pad [15] is "T"-shaped connection, electric connection between described the first metal layer [40] and described second metal level [41] is " L-U " shape and connects, and described compatible pad [15] is " T-L-U " shape to the electric connection between the described solder-bump [50] and connects.
3. double layer lead wire package structure according to claim 1, be characterised in that: the electric connection between described second metal level [41] and the described compatible pad [15] is "T"-shaped connection, electric connection between described the first metal layer [40] and described second metal level [41] is " T-2U " shape and connects, and described compatible pad [15] is " 2T-2U " shape to the electric connection between the described solder-bump and connects.
4. double layer lead wire package structure according to claim 1 is characterised in that: be provided with cavity wall [10] between described crystal substrates and the described first glass packaging layer.
5. double layer lead wire package structure according to claim 1 is characterised in that: be provided with the second glass packaging layer [30] between described insulation material layer [25] and described the first metal layer [40]; Between described second glass packaging layer [30] and described the first metal layer [40], be provided with second solder mask layer [36].
6. double layer lead wire package structure according to claim 1 is characterised in that: be provided with cavity wall [10] between described crystal substrates and the described first glass packaging layer; Between described insulation material layer [25] and described the first metal layer [40], be provided with the second glass packaging layer [30]; Between described second glass packaging layer [30] and described the first metal layer [40], be provided with second solder mask layer [36].
7. the manufacture method of double layer lead wire package structure, it is characterized in that: a wafer is provided, and described wafer comprises a plurality of crystal substrates which is provided with chip, each described on-chip chip periphery is gathered and is arranged compatible pad [15]; Chip on described wafer and substrate front are provided with the first glass packaging layer [5]; Substrate back at described wafer is provided with insulation material layer [25]; At described insulation material layer [25] backside deposition the first metal layer [40], and perforate is set at described the first metal layer middle position; Having covering first solder mask layer [35] on the first metal layer back side of perforate, on described first solder mask layer [35], at least one perforate is set, makes the first metal layer have part surface to be exposed by the perforate on described first solder mask layer [35]; At the side of the lamination of being formed by compatible pad [15], insulation material layer [25], the first metal layer [40] and first solder mask layer [35] and backside deposition second metal level [41] of the solder mask layer of perforate; Be provided with solder-bump [50] in the bottom of second metal level, thereby make described compatible pad [25] by described second metal level [41] and described the first metal layer [40] and described solder-bump [50] electric connection; Cut described wafer, form single wafer level packaging structure.
8. the manufacture method of double layer lead wire package structure according to claim 7, it is characterized in that: on the described first glass packaging layer, form cavity wall [10], make and form the cavity that holds on-chip chip between crystal substrates and the described first glass packaging layer [5].
9. the manufacture method of double layer lead wire package structure according to claim 7, it is characterized in that: the second glass packaging layer [30] is set at described insulation material layer [25] back side, and second solder mask layer [36] is set, and then in second solder mask layer [36] backside deposition the first metal layer [40] at second glass packaging layer [30] back side.
10. the manufacture method of double layer lead wire package structure according to claim 7, it is characterized in that: on the described first glass packaging layer, form cavity wall [10], make to form between crystal substrates and the described first glass packaging layer [5] and hold the cavity that is arranged on on-chip chip; Simultaneously, the second glass packaging layer [30] is set, and second solder mask layer [36] is set at second glass packaging layer [30] back side at described insulation material layer [25] back side, and then in second solder mask layer [36] backside deposition the first metal layer [40].
11. manufacture method according to described any one double layer lead wire package structure of claim 7～10, it is characterized in that: the electric connection between described second metal level [41] and the described compatible pad [15] is "T"-shaped connection, electric connection between described the first metal layer [40] and described second metal level [41] is " L-U " shape and connects, and described compatible pad [15] is " T-L-U " shape to the electric connection between the described solder-bump [50] and connects.
12. manufacture method according to described any one double layer lead wire package structure of claim 7～10, it is characterized in that: the electric connection between described second metal level [41] and the described compatible pad [15] is "T"-shaped connection, electric connection between described the first metal layer [40] and described second metal level [41] is " T-2U " shape and connects, and described compatible pad [15] is " 2T-2U " shape to the electric connection between the described solder-bump [50] and connects.
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| CN1945818A (en) | 2007-04-11 |
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