TW200737380A - Multilayer interconnection substrate, semiconductor device, and solder resist - Google Patents

Multilayer interconnection substrate, semiconductor device, and solder resist

Info

Publication number
TW200737380A
TW200737380A TW095125998A TW95125998A TW200737380A TW 200737380 A TW200737380 A TW 200737380A TW 095125998 A TW095125998 A TW 095125998A TW 95125998 A TW95125998 A TW 95125998A TW 200737380 A TW200737380 A TW 200737380A
Authority
TW
Taiwan
Prior art keywords
solder resist
semiconductor device
multilayer interconnection
interconnection substrate
layers
Prior art date
Application number
TW095125998A
Other languages
English (en)
Other versions
TWI310969B (en
Inventor
Mamoru Kurashina
Daisuke Mizutani
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of TW200737380A publication Critical patent/TW200737380A/zh
Application granted granted Critical
Publication of TWI310969B publication Critical patent/TWI310969B/zh

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/281—Applying non-metallic protective coatings by means of a preformed insulating foil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H01L23/4922—Bases or plates or solder therefor having a heterogeneous or anisotropic structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0275—Fibers and reinforcement materials
    • H05K2201/029—Woven fibrous reinforcement or textile
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
TW095125998A 2006-03-27 2006-07-17 Multilayer interconnection substrate, semiconductor device, and solder resist TWI310969B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006086562A JP4929784B2 (ja) 2006-03-27 2006-03-27 多層配線基板、半導体装置およびソルダレジスト

Publications (2)

Publication Number Publication Date
TW200737380A true TW200737380A (en) 2007-10-01
TWI310969B TWI310969B (en) 2009-06-11

Family

ID=38532147

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095125998A TWI310969B (en) 2006-03-27 2006-07-17 Multilayer interconnection substrate, semiconductor device, and solder resist

Country Status (5)

Country Link
US (1) US20070221400A1 (zh)
JP (1) JP4929784B2 (zh)
KR (1) KR100769637B1 (zh)
CN (1) CN101047159B (zh)
TW (1) TWI310969B (zh)

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JP5335364B2 (ja) * 2007-10-31 2013-11-06 三洋電機株式会社 素子搭載用基板、半導体モジュール及び携帯機器
TWI382502B (zh) * 2007-12-02 2013-01-11 Univ Lunghwa Sci & Technology 晶片封裝之結構改良
KR100908986B1 (ko) 2007-12-27 2009-07-22 대덕전자 주식회사 코어리스 패키지 기판 및 제조 방법
JP2009218545A (ja) * 2008-03-12 2009-09-24 Ibiden Co Ltd 多層プリント配線板及びその製造方法
JP5295596B2 (ja) 2008-03-19 2013-09-18 新光電気工業株式会社 多層配線基板およびその製造方法
KR100923883B1 (ko) 2008-04-25 2009-10-28 대덕전자 주식회사 강도가 부가된 코어 리스 인쇄회로기판 제조 방법
KR100956688B1 (ko) 2008-05-13 2010-05-10 삼성전기주식회사 인쇄회로기판 및 그 제조방법
US20100073894A1 (en) * 2008-09-22 2010-03-25 Russell Mortensen Coreless substrate, method of manufacturing same, and package for microelectronic device incorporating same
US8389870B2 (en) 2010-03-09 2013-03-05 International Business Machines Corporation Coreless multi-layer circuit substrate with minimized pad capacitance
KR101122140B1 (ko) 2010-05-11 2012-03-16 엘지이노텍 주식회사 단일층 인쇄회로기판 및 그 제조방법
US8742603B2 (en) * 2010-05-20 2014-06-03 Qualcomm Incorporated Process for improving package warpage and connection reliability through use of a backside mold configuration (BSMC)
JP5444136B2 (ja) * 2010-06-18 2014-03-19 新光電気工業株式会社 配線基板
JP5578962B2 (ja) * 2010-06-24 2014-08-27 新光電気工業株式会社 配線基板
US8461676B2 (en) 2011-09-09 2013-06-11 Qualcomm Incorporated Soldering relief method and semiconductor device employing same
TWI541957B (zh) * 2012-05-11 2016-07-11 矽品精密工業股份有限公司 半導體封裝件及其封裝基板
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JP6161380B2 (ja) * 2013-04-17 2017-07-12 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
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JP6761224B2 (ja) * 2014-02-19 2020-09-23 味の素株式会社 プリント配線板、半導体装置及び樹脂シートセット
US20160254220A1 (en) * 2015-02-26 2016-09-01 Bridge Semiconductor Corporation Low warping coreless substrate and semiconductor assembly using the same
JP6832630B2 (ja) * 2016-03-28 2021-02-24 富士通インターコネクトテクノロジーズ株式会社 配線基板の製造方法
KR102185706B1 (ko) * 2017-11-08 2020-12-02 삼성전자주식회사 팬-아웃 반도체 패키지
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Also Published As

Publication number Publication date
CN101047159A (zh) 2007-10-03
CN101047159B (zh) 2012-02-08
KR20070096741A (ko) 2007-10-02
US20070221400A1 (en) 2007-09-27
JP4929784B2 (ja) 2012-05-09
TWI310969B (en) 2009-06-11
JP2007266136A (ja) 2007-10-11
KR100769637B1 (ko) 2007-10-23

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