TW200705621A - Interposer and semiconductor device - Google Patents

Interposer and semiconductor device

Info

Publication number
TW200705621A
TW200705621A TW095120063A TW95120063A TW200705621A TW 200705621 A TW200705621 A TW 200705621A TW 095120063 A TW095120063 A TW 095120063A TW 95120063 A TW95120063 A TW 95120063A TW 200705621 A TW200705621 A TW 200705621A
Authority
TW
Taiwan
Prior art keywords
interposer
plane
insulating substrate
semiconductor device
island
Prior art date
Application number
TW095120063A
Other languages
English (en)
Inventor
Yasumasa Kasuya
Sadamasa Fujii
Motoharu Haga
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2005165801A external-priority patent/JP4828164B2/ja
Priority claimed from JP2005240286A external-priority patent/JP5285204B2/ja
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Publication of TW200705621A publication Critical patent/TW200705621A/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3677Wire-like or pin-like cooling fins or heat sinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/10378Interposers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10734Ball grid array [BGA]; Bump grid array
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
TW095120063A 2005-06-06 2006-06-06 Interposer and semiconductor device TW200705621A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005165801A JP4828164B2 (ja) 2005-06-06 2005-06-06 インタポーザおよび半導体装置
JP2005240286A JP5285204B2 (ja) 2005-08-22 2005-08-22 半導体装置及び半導体装置製造用基板

Publications (1)

Publication Number Publication Date
TW200705621A true TW200705621A (en) 2007-02-01

Family

ID=37498351

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095120063A TW200705621A (en) 2005-06-06 2006-06-06 Interposer and semiconductor device

Country Status (4)

Country Link
US (2) US8022532B2 (zh)
KR (1) KR20080014004A (zh)
TW (1) TW200705621A (zh)
WO (1) WO2006132151A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI604541B (zh) * 2016-09-19 2017-11-01 南亞科技股份有限公司 半導體封裝體及其製造方法

Families Citing this family (66)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG111935A1 (en) 2002-03-04 2005-06-29 Micron Technology Inc Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods
SG121707A1 (en) 2002-03-04 2006-05-26 Micron Technology Inc Method and apparatus for flip-chip packaging providing testing capability
WO2006134220A1 (en) * 2005-06-16 2006-12-21 Imbera Electronics Oy Method for manufacturing a circuit board structure, and a circuit board structure
JP4962228B2 (ja) * 2006-12-26 2012-06-27 株式会社ジェイテクト 多層回路基板およびモータ駆動回路基板
CN101296570A (zh) * 2007-04-25 2008-10-29 富葵精密组件(深圳)有限公司 电路板及其制作方法
JP5081578B2 (ja) 2007-10-25 2012-11-28 ローム株式会社 樹脂封止型半導体装置
US8129001B2 (en) * 2008-03-17 2012-03-06 The Research Foundation Of State University Of New York Composite thermal interface material system and method using nano-scale components
TWI365517B (en) * 2008-05-23 2012-06-01 Unimicron Technology Corp Circuit structure and manufactring method thereof
US8188379B2 (en) * 2008-07-04 2012-05-29 Unimicron Technology Corp. Package substrate structure
US8115292B2 (en) * 2008-10-23 2012-02-14 United Test And Assembly Center Ltd. Interposer for semiconductor package
TWI414048B (zh) * 2008-11-07 2013-11-01 Advanpack Solutions Pte Ltd 半導體封裝件與其製造方法
TW201029230A (en) * 2009-01-23 2010-08-01 Everlight Electronics Co Ltd Light emitting diode package
US8897046B2 (en) 2009-12-25 2014-11-25 Rohm Co., Ltd. DC voltage conversion module, semiconductor module, and method of making semiconductor module
CN102822962B (zh) 2010-03-31 2015-12-09 京瓷株式会社 内插件及使用了该内插件的电子装置
KR101142336B1 (ko) * 2010-05-07 2012-05-17 에스케이하이닉스 주식회사 반도체 칩 및 이를 이용한 스택 패키지
DE102010025966B4 (de) * 2010-07-02 2012-03-08 Schott Ag Interposer und Verfahren zum Herstellen von Löchern in einem Interposer
JP5769058B2 (ja) * 2011-03-29 2015-08-26 大日本印刷株式会社 半導体装置および半導体装置の製造方法
US9263374B2 (en) 2010-09-28 2016-02-16 Dai Nippon Printing Co., Ltd. Semiconductor device and manufacturing method therefor
US9029991B2 (en) * 2010-11-16 2015-05-12 Conexant Systems, Inc. Semiconductor packages with reduced solder voiding
KR20120082190A (ko) * 2011-01-13 2012-07-23 삼성엘이디 주식회사 발광소자 패키지
KR101289186B1 (ko) * 2011-04-15 2013-07-26 삼성전기주식회사 인쇄회로기판 및 그 제조방법
KR20130010359A (ko) * 2011-07-18 2013-01-28 삼성전자주식회사 반도체 장치용 기판 및 그를 포함한 반도체 장치
US9406738B2 (en) 2011-07-20 2016-08-02 Xilinx, Inc. Inductive structure formed using through silicon vias
US20130025839A1 (en) * 2011-07-25 2013-01-31 Endicott Interconnect Technologies, Inc. Thermal substrate
US9330823B1 (en) * 2011-12-19 2016-05-03 Xilinx, Inc. Integrated circuit structure with inductor in silicon interposer
US9337138B1 (en) 2012-03-09 2016-05-10 Xilinx, Inc. Capacitors within an interposer coupled to supply and ground planes of a substrate
US8664768B2 (en) * 2012-05-03 2014-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Interposer having a defined through via pattern
JP6008582B2 (ja) * 2012-05-28 2016-10-19 新光電気工業株式会社 半導体パッケージ、放熱板及びその製造方法
US8866024B1 (en) * 2012-06-22 2014-10-21 Altera Corporation Transceiver power distribution network
US9293338B2 (en) 2012-11-08 2016-03-22 Nantong Fujitsu Microelectronics Co., Ltd. Semiconductor packaging structure and method
US9474166B2 (en) * 2012-12-21 2016-10-18 Canon Kabushiki Kaisha Printed wiring board, printed circuit board, and method for manufacturing printed circuit board
US9554453B2 (en) * 2013-02-26 2017-01-24 Mediatek Inc. Printed circuit board structure with heat dissipation function
US8723052B1 (en) 2013-02-27 2014-05-13 Boulder Wind Power, Inc. Methods and apparatus for optimizing electrical interconnects on laminated composite assemblies
US8785784B1 (en) 2013-03-13 2014-07-22 Boulder Wind Power, Inc. Methods and apparatus for optimizing structural layout of multi-circuit laminated composite assembly
US9793775B2 (en) 2013-12-31 2017-10-17 Boulder Wind Power, Inc. Methods and apparatus for reducing machine winding circulating current losses
JP2015211204A (ja) * 2014-04-30 2015-11-24 イビデン株式会社 回路基板及びその製造方法
JP6504762B2 (ja) * 2014-08-05 2019-04-24 キヤノン株式会社 モジュールの製造方法
US9490226B2 (en) * 2014-08-18 2016-11-08 Qualcomm Incorporated Integrated device comprising a heat-dissipation layer providing an electrical path for a ground signal
JP2016171119A (ja) * 2015-03-11 2016-09-23 イビデン株式会社 回路基板及びその製造方法
US9585257B2 (en) 2015-03-25 2017-02-28 Globalfoundries Inc. Method of forming a glass interposer with thermal vias
JP6392163B2 (ja) * 2015-04-17 2018-09-19 新光電気工業株式会社 配線基板及びその製造方法、半導体装置
FR3036917B1 (fr) * 2015-05-28 2018-11-02 IFP Energies Nouvelles Dispositif electronique comprenant une carte de circuit imprime avec un refroidissement ameliore.
KR102486558B1 (ko) * 2015-06-24 2023-01-10 삼성전자주식회사 회로 기판 및 이를 구비한 반도체 패키지
KR101923659B1 (ko) * 2015-08-31 2019-02-22 삼성전자주식회사 반도체 패키지 구조체, 및 그 제조 방법
WO2017039275A1 (ko) 2015-08-31 2017-03-09 한양대학교 산학협력단 반도체 패키지 구조체, 및 그 제조 방법
US10418302B2 (en) 2015-11-30 2019-09-17 Nsk Ltd. Control unit and electric power steering device
US10083894B2 (en) * 2015-12-17 2018-09-25 International Business Machines Corporation Integrated die paddle structures for bottom terminated components
JP6487315B2 (ja) * 2015-12-21 2019-03-20 日立オートモティブシステムズ株式会社 電子制御装置
CN109844945A (zh) * 2016-09-30 2019-06-04 英特尔公司 具有高密度互连的半导体封装
US10811334B2 (en) 2016-11-26 2020-10-20 Texas Instruments Incorporated Integrated circuit nanoparticle thermal routing structure in interconnect region
US11004680B2 (en) 2016-11-26 2021-05-11 Texas Instruments Incorporated Semiconductor device package thermal conduit
US10529641B2 (en) 2016-11-26 2020-01-07 Texas Instruments Incorporated Integrated circuit nanoparticle thermal routing structure over interconnect region
US10256188B2 (en) 2016-11-26 2019-04-09 Texas Instruments Incorporated Interconnect via with grown graphitic material
US11676880B2 (en) 2016-11-26 2023-06-13 Texas Instruments Incorporated High thermal conductivity vias by additive processing
US10861763B2 (en) 2016-11-26 2020-12-08 Texas Instruments Incorporated Thermal routing trench by additive processing
US11742270B2 (en) 2016-12-15 2023-08-29 Intel Corporation Landing pad apparatus for through-silicon-vias
US10229864B1 (en) * 2017-09-14 2019-03-12 Northrop Grumman Systems Corporation Cryogenic integrated circuit having a heat sink coupled to separate ground planes through differently sized thermal vias
DE102017218273B4 (de) 2017-10-12 2022-05-12 Vitesco Technologies GmbH Halbleiterbaugruppe
JP6462926B2 (ja) * 2018-03-05 2019-01-30 東芝メモリ株式会社 ストレージ装置、及び電子機器
JP7269756B2 (ja) * 2018-05-01 2023-05-09 ローム株式会社 半導体装置および半導体装置の製造方法
EP3621104A1 (en) * 2018-09-05 2020-03-11 Infineon Technologies Austria AG Semiconductor package and method of manufacturing a semiconductor package
JP2020126921A (ja) * 2019-02-04 2020-08-20 株式会社村田製作所 高周波モジュールおよび通信装置
GB2581149B (en) * 2019-02-05 2021-11-10 Pragmatic Printing Ltd Flexible interposer
US10770399B2 (en) * 2019-02-13 2020-09-08 Infineon Technologies Ag Semiconductor package having a filled conductive cavity
KR20220000294A (ko) * 2020-06-25 2022-01-03 삼성전자주식회사 반도체 패키지
CN117747560B (zh) * 2024-02-19 2024-05-14 成都汉芯国科集成技术有限公司 一种基于砷化镓、氮化镓和金刚石3d封装芯片及封装方法

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08139226A (ja) 1994-11-04 1996-05-31 Sony Corp 半導体回路装置及びその回路実装方法
JP3123638B2 (ja) * 1995-09-25 2001-01-15 株式会社三井ハイテック 半導体装置
US6117705A (en) * 1997-04-18 2000-09-12 Amkor Technology, Inc. Method of making integrated circuit package having adhesive bead supporting planar lid above planar substrate
KR100244965B1 (ko) * 1997-08-12 2000-02-15 윤종용 인쇄회로기판과 볼 그리드 어레이 패키지의 제조 방법
JPH11121643A (ja) 1997-10-09 1999-04-30 Hitachi Ltd 半導体装置
JPH11154717A (ja) * 1997-11-20 1999-06-08 Citizen Watch Co Ltd 半導体装置
TW413874B (en) * 1999-04-12 2000-12-01 Siliconware Precision Industries Co Ltd BGA semiconductor package having exposed heat dissipation layer and its manufacturing method
JP4618464B2 (ja) 1999-12-28 2011-01-26 日立化成工業株式会社 接着剤組成物、これを用いた接着フィルム、半導体チップ搭載用基板及び半導体装置
US6372540B1 (en) * 2000-04-27 2002-04-16 Amkor Technology, Inc. Moisture-resistant integrated circuit chip package and method
CN1265451C (zh) 2000-09-06 2006-07-19 三洋电机株式会社 半导体装置及其制造方法
JP2002158315A (ja) 2000-09-06 2002-05-31 Sanyo Electric Co Ltd 半導体装置およびその製造方法
US6909178B2 (en) 2000-09-06 2005-06-21 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing the same
TW462121B (en) * 2000-09-19 2001-11-01 Siliconware Precision Industries Co Ltd Heat sink type ball grid array package
TW490820B (en) * 2000-10-04 2002-06-11 Advanced Semiconductor Eng Heat dissipation enhanced ball grid array package
US20020079572A1 (en) * 2000-12-22 2002-06-27 Khan Reza-Ur Rahman Enhanced die-up ball grid array and method for making the same
JP2003008186A (ja) 2001-06-21 2003-01-10 Sony Corp 半導体装置
US6657296B2 (en) * 2001-09-25 2003-12-02 Siliconware Precision Industries Co., Ltd. Semicondctor package
JP2003297966A (ja) * 2002-03-29 2003-10-17 Mitsubishi Electric Corp 半導体装置
US7109573B2 (en) * 2003-06-10 2006-09-19 Nokia Corporation Thermally enhanced component substrate
JP2005101365A (ja) 2003-09-25 2005-04-14 Kyocera Corp 電子装置
JP4255842B2 (ja) * 2004-01-09 2009-04-15 パナソニック株式会社 半導体装置
JP4828164B2 (ja) * 2005-06-06 2011-11-30 ローム株式会社 インタポーザおよび半導体装置
US7696594B2 (en) * 2005-12-22 2010-04-13 International Business Machines Corporation Attachment of a QFN to a PCB
JP2008091714A (ja) * 2006-10-03 2008-04-17 Rohm Co Ltd 半導体装置
JP4906496B2 (ja) * 2006-12-25 2012-03-28 新光電気工業株式会社 半導体パッケージ

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI604541B (zh) * 2016-09-19 2017-11-01 南亞科技股份有限公司 半導體封裝體及其製造方法
US9922920B1 (en) 2016-09-19 2018-03-20 Nanya Technology Corporation Semiconductor package and method for fabricating the same
US10037937B2 (en) 2016-09-19 2018-07-31 Nanya Technology Corporation Method for forming semiconductor package

Also Published As

Publication number Publication date
KR20080014004A (ko) 2008-02-13
US8022532B2 (en) 2011-09-20
WO2006132151A1 (ja) 2006-12-14
US20090115050A1 (en) 2009-05-07
US20110156226A1 (en) 2011-06-30

Similar Documents

Publication Publication Date Title
TW200705621A (en) Interposer and semiconductor device
WO2008099554A1 (ja) 半導体パッケージの実装構造
WO2007136941A3 (en) Flip chip mlp with folded heat sink
WO2006089033A3 (en) Led light module assembly
TW200712850A (en) Heatsink assembly
TW200737443A (en) Novel chip packaging structure for improving reliability
TW200709766A (en) Flexible circuit board with heat sink
WO2008076635A3 (en) Stacked flip-assembled semiconductor chips embedded in thin hybrid substrate
SG170099A1 (en) Integrated circuit package system with warp-free chip
TW200616169A (en) Wiring board and semiconductor device
TW200642055A (en) Area mount type semiconductor device, and die bonding resin composition and encapsulating resin composition used for the same
TW200607127A (en) Thermoelectric module
SG147390A1 (en) Semiconductor device package to improve functions of heat sink and ground shield
TW200739841A (en) Semiconductor device with a heat sink and method for fabricating the same
TW200703523A (en) Semiconductor device with low CTE substrates
EP2743979A3 (en) Chip thermal dissipation structure
ATE519229T1 (de) Einrichtung mit einem sensormodul
TW200635013A (en) Stacked semiconductor package
SG148987A1 (en) Inter-connecting structure for semiconductor device package and method of the same
SG154406A1 (en) Mcm packages
EP2135281A4 (en) THERMAL SPREADING IN CHIPSUBSTRATES
JP2008091719A5 (zh)
SG148973A1 (en) Semiconductor device package having pseudo chips
JP2010251625A5 (ja) 半導体装置
TW200629501A (en) Chip scale packaging with improved heat dissipation capability