CN109844945A - 具有高密度互连的半导体封装 - Google Patents

具有高密度互连的半导体封装 Download PDF

Info

Publication number
CN109844945A
CN109844945A CN201680088848.1A CN201680088848A CN109844945A CN 109844945 A CN109844945 A CN 109844945A CN 201680088848 A CN201680088848 A CN 201680088848A CN 109844945 A CN109844945 A CN 109844945A
Authority
CN
China
Prior art keywords
interconnection
electronic component
active electronic
semiconductor packages
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201680088848.1A
Other languages
English (en)
Inventor
A·A·埃尔谢尔比尼
J·M·斯旺
S·M·利夫
H·布劳尼施
K·巴拉斯
J·索托冈萨雷斯
J·A·法尔孔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taihao Research Co ltd
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN109844945A publication Critical patent/CN109844945A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73209—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0652—Bump or bump-like direct electrical connections from substrate to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)

Abstract

所公开的各种实施例涉及半导体封装。本半导体封装包括衬底。衬底由交替的导电层和电介质层形成。第一有源电子部件设置于衬底的外表面上，并且第二有源电子部件至少部分地嵌入在衬底内。第一互连区域由第一有源电子部件和第二有源电子部件之间的多个互连形成。在第一有源电子部件和衬底之间，由多个互连形成第二互连区域。此外，第三互连区域由第二有源电子部件和衬底之间的多个互连形成。

Description

具有高密度互连的半导体封装
背景技术
半导体封装中的挑战是以相对低的成本在不同管芯之间提供非常高的互连密度。一种可能的方案是在不同管芯之间使用硅内插器。另一种方案可以是使用非常高密度的有机内插器或封装。
附图说明
在附图中，在所有几幅图中以类似的附图标记描述基本类似的部件，附图未必是按比例绘制的。具有不同字母下标的类似附图标记代表基本类似部件的不同实例。附图通过举例而非限制的方式总体上例示了本文中论述的各种实施例。
图1A是根据各种实施例的半导体封装的示意性截面图。
图1B是根据各种实施例的另一半导体封装的示意性截面图。
图1C是根据各种实施例的又一半导体封装的示意性截面图。
图2A-图2E是根据各种实施例的总体上示出了形成半导体封装的方法的示意图。
图3A-图3G是根据各种实施例的总体上示出了形成另一半导体封装的方法的示意图。
具体实施方式
现在将详细地参考所公开主题的某些实施例，在附图中部分地示出了这些实施例的示例。尽管将结合所枚举的权利要求描述所公开的主题，但将要理解，举例说明的主题并非要将权利要求限制到所公开的主题。
在本文通篇中，以范围格式表达的值应当以灵活的方式解释，以不仅包括明确列举为范围的极限的数值，而且还包括该范围内涵盖的所有个体数值或子范围，如同明确列举了每个数值和子范围一样。例如，“大约0.1％到大约5％”或“大约0.1％到5％”的范围应当被理解为不仅包括大约0.1％到大约5％，而且还包括所指示例围内的个体值(例如，1％、2％、3％和4％)和子范围(例如，0.1％到0.5％、1.1％到2.2％、3.3％到4.4％)。表述“大约X到Y”与“大约X到大约Y”具有相同含义，除非另外指示。同样，表述“大约X、Y或大约Z”与“大约X、大约Y或大约Z”具有相同含义，除非另外指示。
在本文中，使用术语“一”或“所述”以包括一个或超过一个，除非上下文以其它方式明确规定。使用术语“或”指代非排他性“或”，除非另外指示。表述“A和B中的至少一个”与“A、B或A和B”具有相同含义。此外，应当理解，本文采用的未经另行定义的措辞或术语仅用于描述的目的而非进行限制。对章节标题的任何使用旨在辅助阅读本文，并且不应被理解为限制；与章节标题相关的信息可以出现于该特定章节内或外部。
在本文描述的方法中，可以按照任何次序执行动作而不脱离本公开的原理，除非在明确列举了时间或操作序列时。此外，可以同时执行指定的动作，除非明确的权利要求语言叙述了这些动作要被独立执行。例如，可以在单一操作内同时进行所要求保护的做X的动作和所要求保护的做Y的动作，并且所得的过程将落在所要求保护的过程的字面范围内。
如本文所用的，术语“大约”能够允许值或范围中的一定程度的变化，例如，所规定的值或范围的所规定的极限的10％内、5％内或1％内，并且包括精确规定的值或范围。
如本文所用的术语“基本上”是指大多数、或大部分，至少大约50％、60％、70％、80％、90％、95％、96％、97％、98％、99％、99.5％、99.9％、99.99％，或至少大约99.999％或更多，或者100％。
图1A是半导体封装10A的示意性截面图。如图1A中所示，半导体封装10A包括衬底12。衬底12由交替的导电层14和电介质层16形成。每个导电层14由诸如铜的导电材料形成。导电层14允许通过衬底12传送信号以及输送功率。每个导电层14通过衬底过孔18连接到其它层，所述其它层典型地由与每个导电层14相同的导电材料形成。每个导电层14可以具有不同的功能。例如，导电层14中的一些可能适合作为信号层，其通过衬底12发送信号。其它导电层14可能适合作为电源层或接地层。
电介质层16与导电层14穿插并由电介质材料形成。电介质材料的适当示例包括累积膜、聚酰亚胺、双马来酰亚胺三嗪(BT)树脂、环氧树脂、聚氨酯、苯并环丁烯(BCB)或高密度聚乙烯(HDPE)。至少一些电介质材料可以包括强化玻璃纤维。通过电介质层16形成衬底过孔18并连接导电层14。
半导体封装10A还包括至少两个有源电子部件。有源电子部件可以是硅管芯。例如，第一有源电子部件20可以是第一硅管芯，其可以是中央处理单元、现场可编程门阵列、片上系统或图形处理单元。第二有源电子部件22可以是第二硅管芯，其可以是高带宽存储器、封装嵌入式存储器、闪存存储器、嵌入式非易失性存储器、III-V管芯、加速器、或低功率双数据速率存储器。第一有源电子部件20和第二有源电子部件22两者具有除了在部件之间传送信号之外的有源功能。
第一有源电子部件20被设置在衬底12的外表面上。外表面可以是导电层或电介质层，其间形成有衬底过孔18。第二有源电子部件22至少部分地嵌入在衬底12内。具体而言，第二有源电子部件22嵌入在衬底12的凹陷24内。第一有源电子部件20和第二有源电子部件22中的每者具有设置于其上的若干互连。具体而言，第一互连区域26由第一有源电子部件20和第二有源电子部件22之间的多个互连28形成。
第二互连区域30由第一有源电子部件20和衬底12之间的多个互连28形成。此外，第三互连区域32由第二有源电子部件22和衬底12之间的多个互连28形成。可以通过若干不同的方式形成第三互连区域32。例如，如图1A所示，第三互连区域32部分由内插器34形成。内插器34由顶表面36和底表面38形成。第四互连区域33包括多个互连28并且被限定在内插器34和衬底12之间。底表面38的第一部分40连接到第三互连区域32的互连28，并且底表面38的第二部分42连接到第四互连区域33的互连28。互连28由焊球形成，其连接到内插器34的底表面38和衬底12的导电层14。如所示，第一互连区域26和第三互连区域32位于第二有源电子部件22的同一表面上。
内插器34通常由与电介质层16的电介质材料类似的电介质材料形成。多个热过孔44从底表面38延伸穿过电介质材料到达顶表面36。热过孔44由诸如金属的导热材料形成。例如，热过孔44可以由铜形成。热过孔44被定位在第二有源电子部件22之上。这允许通过热过孔44有效地带走在第二有源电子部件22的操作期间所产生的热量。
如图1A所示，第三互连区域32的互连28由焊球形成。焊球连接到内插器34的底表面38和第二有源电子部件22的顶表面48。此外，第一互连区域26的互连28包括焊球，其连接到第一有源电子部件20的底表面51和第二有源电子部件22的顶表面48。第二互连区域30的互连28包括连接到衬底12的导电层14并连接到第一有源电子部件20的底表面51的焊球。
相应的互连区域可以在其功能和其中的互连28的密度方面彼此不同。例如，第一互连区域26具有的互连28的密度比第二互连区域30的互连28和第三互连区域32的互连28中的至少一者的密度高。该较高密度可以允许在第一有源电子部件20和第二有源电子部件22之间传输高带宽信号。不过，第二互连区域30和第三互连区域32的较低密度足以允许从衬底12分别向第一有源电子部件20和第二有源电子部件22传输功率。
每个互连区域的密度可以被测量为个体互连28之间的间距或间隔的函数。例如，第一互连区域26的互连28的间距可以具有处于从大约20微米到大约80微米的范围内、或大约40微米到大约65微米的范围内、或小于大约、等于大约或大于大约25微米、30微米、35微米、40微米、45微米、50微米、55微米、60微米、65微米、70微米或75微米的值。在第二互连区域30密度小于第一互连区域26的示例中，第二互连区域30的互连28的间距可以处于从大约85微米到大约350微米的范围内、或从大约100微米到大约500微米的范围内、或小于大约、等于大约或大于大约110微米、120微米、130微米、140微米、150微米、160微米、170微米、180微米、190微米、200微米、210微米、220微米、230微米、240微米、250微米、260微米、270微米、280微米、290微米、300微米、310微米、320微米、330微米、340微米、350微米、360微米、370微米、380微米、390微米、400微米、410微米、420微米、430微米、440微米、450微米、460微米、470微米、480微米或490微米的范围内。类似地，在第三互连区域32密度小于第一互连区域26的示例中，第三互连区域32的互连28的间距可以处于从大约85微米到大约500微米的范围内、或从大约100微米到大约300微米的范围内、或小于大约、等于大约或大于大约120微米、130微米、140微米、150微米、160微米、170微米、180微米、190微米、200微米、210微米、220微米、230微米、240微米、250微米、260微米、270微米、280微米、290微米、300微米、310微米、320微米、330微米、340微米、350微米、360微米、370微米、380微米、390微米、400微米、410微米、420微米、430微米、440微米、450微米、460微米、470微米、480微米或490微米的范围内。第二互连区域30和第三互连区域32的密度可以相同或不同。
每个互连区域占用第一有源电子部件20或第二有源电子部件22的表面积的不同百分比。例如，第一互连区域26可以处于从第一有源电子部件20的表面积的大约2％到大约15％的范围内，或处于从第一有源电子部件20的表面积的大约2％到大约10％的范围内，或处于小于大约、等于大约或大于大约第一有源电子部件20的表面积的2％、3％、4％、5％、6％、7％、8％、9％、10％、11％、12％、13％或14％的范围内。表面积越小，则信号在第一有源电子部件20和第二有源电子部件22之间必须行进的距离越小。如图1A所示，第二互连区域30可以处于从第一有源电子部件20的表面积的大约85％到大约95％的范围内，或处于从第一有源电子部件20的表面积的大约90％到大约98％的范围内，或处于小于大约、等于大约或大于大约第一有源电子部件20的表面积的86％、87％、88％、89％、90％、91％、92％、93％、94％、95％、96％或97％的范围内。类似地，第三互连区域32可以处于从第二有源电子部件22的表面积的大约85％到大约95％的范围内，或处于从第二有源电子部件22的表面积的大约90％到大约98％的范围内，或处于小于大约、等于大约或大于大约第二有源电子部件22的表面积的86％、87％、88％、89％、90％、91％、92％、93％、94％、95％、96％或97％的范围内。
图1B是示出半导体封装10B的示意性截面图。图1B示出了很多与图1A相同的部件。不过，半导体封装10A和半导体封装10B之间的不同之处在于，如内插器34的位置处所示，在半导体封装10B中，第三互连区域32由衬底12的导电层14的部分形成。衬底12的形成第三互连区域32的该部分覆盖第二有源电子部件22的一部分。第三互连区域32的互连28包括从衬底12到第二有源电子部件22的过孔18。第三互连区域32的过孔18最初是第二有源电子部件22的部分，其通过在过孔18之上镀敷铜层而附接到衬底12。第二有源电子部件22包括与第一有源电子部件20的焊球连接以形成第一互连区域26的另一组过孔18。
半导体封装10B还包括热过孔44。热过孔44设置于第二有源电子部件22上、在第一互连区域26和第三互连区域32之间。热过孔44的表面积可以变化。例如，热过孔44可以设置于第二有源电子部件22的表面积之上，处于从第二有源电子部件22的表面积的大约25％到50％的范围内，或处于从第二有源电子部件22的表面积的大约25％到35％的范围内，或处于小于大约、等于大约或大于大约第二有源电子部件22的表面积的30％、35％、40％或45％的范围内。热过孔44也可以存在于第二有源电子部件22下方的衬底12中。
图1C是示出半导体封装10C的示意性截面图。图1C示出了很多与图1A和图1B相同的部件。不过，半导体封装10C与半导体封装10A和半导体封装10B二者之间的不同之处在于，替代内插器34，在半导体封装10C中，第三互连区域32由衬底12和第二有源电子部件22之间的导线连接50形成。
图2A-图2E是总体上示出了形成半导体封装10A的方法的示意图。图2A示出了由交替的导电层14和电介质层16形成的衬底12。为了组装半导体封装10A，在衬底12中创建凹陷24。这在图2B中示出。可以通过包括研磨、湿法或干法蚀刻或机械研磨的很多不同方式创建凹陷24。此外，能够通过在最顶部的铜和阻焊剂区域中空出某一区域来创建凹陷24。在其它示例中，可以形成衬底12以像成品那样包括凹陷24。如图2C所示，第二有源电子部件22附接到凹陷24。这可以使用管芯附接膜(DAF)来实现。使用当前的制造工具来附接第二有源电子部件22允许好于6μm的放置精确度。如果需要，这样又可以允许互连28的间距为55μm或甚至更小间距，例如40μm。为了解决封装厚度变化，可以使用较软的DAF和稍大的凹陷24。然后向下按压第一有源电子部件20。可以利用诸如环氧树脂的包封材料填充围绕第一有源电子部件20的任何空气隙。如图2D所示，使用热压接合(TCB)附接第一有源电子部件20。这样允许根据需要实现非常精细的对准和塌缩控制。在其它示例中，可以首先面对面地附接第一有源电子部件20和第二有源电子部件22，并且此后将它们附接到衬底12。
如图2E所示，将内插器34附接到衬底12和第二有源电子部件22。这可以使用热压接合技术(TCB)或焊料回流来完成。可以使用标准封装制造工艺来制造内插器34。与铜的大约400W/mK相比，硅具有的热导率为大致149W/mK。取决于需要耗散的功率量和内插器34封装的厚度，可以增大过孔18的密度以减小热电阻。替代地，可以通过在内插器34中使用光刻过孔来改善热导率。
在附接内插器34之后，可以向第一有源电子部件20的顶侧和内插器34的顶侧施加热界面材料(TIM)。然后附接集成散热器(IHS)。在其它示例中，可以施加多种类型的TIM以解决高度容差衬底12部件。此外，可以根据IHS的适当设计的需要和理解，在顶侧封装的顶部放置集成电路和/或分立部件，例如电压调节器、电容器或电感器。
图3A-图3G是总体上示出了形成半导体封装10B的方法的示意图。如图3A所示，在衬底12中创建凹陷24。如图3B所示，然后在凹陷24中嵌入第二有源电子部件22。第二有源电子部件22包括其上形成的若干过孔18。每个过孔18可以较高。例如，过孔18可以是从大约10μm到大约20μm高。如图3C所示，在第二有源电子部件22之上层压电介质累积膜。如图3D所示，(例如，使用机械研磨或抛光)研磨衬底12以显露第二有源电子部件22上的过孔28。如图3E所示，然后在衬底12和第二有源电子部件22上沉积种层，并且施加光致抗蚀剂层，并对其进行曝光和显影。这在过孔18之上创建了开口，如果曝光不可控，也可以使用激光钻孔来创建开口。如图3F所示，然后在衬底12和第二有源电子部件22之上镀敷金属导电层，并剥离光致抗蚀剂。如图3G所示，将阻焊层施加到衬底12和第二有源电子部件22。接下来对阻焊层进行曝光和显影。然后以类似于结合图2C所述的方式附接第一有源电子部件20。此外，可以向第一有源电子部件20的顶侧和第二有源电子部件22的顶侧施加热界面材料。然后附接IHS。在其它示例中，可以施加多种类型的TIM以解决MCP部件之间的高度容差。此外，可以根据IHS的适当设计的需要和理解，在顶侧封装的顶部放置集成电路和/或分立部件，例如电压调节器、电容器或电感器。
尽管已经描述了仅使用第一有源电子部件20和第二有源电子部件22的本公开的示例，但半导体封装10的其它示例可以包括附加的有源电子部件。例如，两个或更多有源电子部件可以位于凹陷24中。此外，可以将两个或更多有源电子部件附接到第二有源电子部件22。
有很多原因使用半导体封装10A-10C，包括以下非限制性原因。例如，由于第一有源电子部件20和第二有源电子部件22之间的电容显著减小，与常规封装相比，半导体封装10可以提供高达60％的功率节省。由于部件之间的直接连接而使部件之间的距离减小，从而导致电容减小。此外，在一些示例中，由于急剧减小的电阻和减小的电容，所提出的半导体封装10可以允许互连28在与当前互连相同的功率下以高得多的带宽进行操作。此外，在一些实施例中，因为互连极短(例如，50-100μm)，所以与很多当前方式相比，极细间距下的极高数据速率/频率(例如，对于通往用于产生/放大的III-V管芯的毫米波互连)是可能的，而且损耗极低。
附加实施例
提供了以下示例性实施例，其编号不应被理解为指定重要性水平：
实施例1提供了一种半导体封装，包括：
衬底，包括：
交替的导电层和电介质层；
设置于衬底的外表面上的第一硅管芯；
至少部分地嵌入在衬底内的第二有源电子部件；
由第一有源电子部件和第二有源电子部件之间的多个互连形成的第一互连区域；
由第一有源电子部件和衬底之间的多个互连形成的第二互连区域；
由第二有源电子部件和衬底之间的多个互连形成的第三互连区域。
实施例2提供了实施例1所述的半导体封装，其中，导电层包括：
导电材料。
实施例3提供了实施例1-2中任一个所述的半导体封装，其中，导电材料是铜。
实施例4提供了实施例1-3中任一个所述的半导体封装，其中，电介质层包括：
电介质材料。
实施例5提供了实施例1-4中任一个所述的半导体封装，其中，电介质材料是从聚酰亚胺、双马来酰亚胺-三嗪(BT)树脂、环氧树脂、聚氨酯、苯并环丁烯(BCB)、高密度聚乙烯(HDPE)、编织玻璃纤维强化树脂或其组合组成的组中选择的。
实施例6提供了实施例1-5中任一个所述的半导体封装，其中，第一互连区域具有的互连密度比第二互连区域和第三互连区域中的至少一个的互连密度高。
实施例7提供了实施例1-6中任一个所述的半导体封装，其中，第一互连区域的互连包括：
连接到第一有源电子部件的底表面和第二有源电子部件的顶表面的焊球。
实施例8提供了实施例1-7中任一个所述的半导体封装，其中，第一互连区域的互连包括：
连接到第一有源电子部件的底表面的焊球；以及
连接到第二有源电子部件的顶表面的过孔，
其中，焊球和过孔彼此连接。
实施例9提供了实施例1-8中任一个所述的半导体封装，其中，第二互连区域的互连包括：
连接到衬底的导电层和第一有源电子部件的焊球。
实施例10提供了实施例1-9中任一个所述的半导体封装，其中，第一互连区域的互连具有处于从大约20微米到大约80微米的范围内的间距。
实施例11提供了实施例1-10中任一个所述的半导体封装，其中，第一互连区域的互连具有处于从大约40微米到大约65微米的范围内的间距。
实施例12提供了实施例1-11中任一个所述的半导体封装，其中，第二互连区域的互连具有处于从大约微米μm到大约500微米的范围内的间距。
实施例13提供了实施例1-12中任一个所述的半导体封装，其中，第二互连区域的互连具有处于从大约100微米到大约300微米的范围内的间距。
实施例14提供了实施例1-13中任一个所述的半导体封装，其中，第三互连区域的互连具有处于从大约微米μm到大约500微米的范围内的间距。
实施例15提供了实施例1-14中任一个所述的半导体封装，其中，第三互连区域的互连具有处于从大约100微米到大约300微米的范围内的间距。
实施例16提供了实施例1-15中任一个所述的半导体封装，其中，第二互连区域的密度和第三互连区域的密度相同。
实施例17提供了实施例1-16中任一个所述的半导体封装，其中，第二互连区域的密度和第三互连区域的密度不同。
实施例18提供了实施例1-17中任一个所述的半导体封装，其中，第一互连区域包括第一有源电子部件的表面积的大约2％到大约15％。
实施例19提供了实施例1-18中任一个所述的半导体封装，其中，第一互连区域包括第一有源电子部件的表面积的大约2％到大约10％。
实施例20提供了实施例1-19中任一个所述的半导体封装，其中，第一互连区域包括第二有源电子部件的表面积的大约2％到大约15％。
实施例21提供了实施例1-20中任一个所述的半导体封装，其中，第一互连区域包括第二有源电子部件的表面积的大约2％到大约10％。
实施例22提供了实施例1-21中任一个所述的半导体封装，其中，第二互连区域包括第一有源电子部件的表面积的大约85％到大约95％。
实施例23提供了实施例1-22中任一个所述的半导体封装，其中，第二互连区域包括第一有源电子部件的表面积的大约90％到大约98％。
实施例24提供了实施例1-23中任一个所述的半导体封装，其中，第三互连区域包括第二有源电子部件的表面积的大约85％到大约95％。
实施例25提供了实施例1-24中任一个所述的半导体封装，其中，第三互连区域包括第二有源电子部件的表面积的大约90％到大约98％。
实施例26提供了实施例1-25中任一个所述的半导体封装，其中，第三互连区域由内插器形成，内插器包括：
顶表面；
底表面；以及
处于内插器和衬底之间的第四互连区域，
其中，底表面的第一部分连接到第三互连区域的互连；并且底表面的第二部分连接到第四互连区域的互连。
实施例27提供了实施例1-26中任一个所述的半导体封装，其中，内插器还包括：
从内插器的底表面延伸到内插器的顶表面的多个热过孔。
实施例28提供了实施例1-27中任一个所述的半导体封装，其中，第三互连区域的互连包括：
连接到内插器的底表面和第二有源电子部件的顶表面的焊球。
实施例29提供了实施例1-28中任一个所述的半导体封装，其中，第四互连区域包括多个互连。
实施例30提供了实施例1-29中任一个所述的半导体封装，其中，第四互连区域的互连包括：
连接到内插器的底表面和衬底的导电层的焊球。
实施例31提供了实施例1-30中任一个所述的半导体封装，其中，热过孔被定位在第二有源电子部件之上。
实施例32提供了实施例1-31中任一个所述的半导体封装，其中，热过孔由导热材料形成。
实施例33提供了实施例1-32中任一个所述的半导体封装，其中，导热材料是铜。
实施例34提供了实施例1-33中任一个所述的半导体封装，其中，第三互连区域由衬底的导电层的一部分形成。
实施例35提供了实施例1-34中任一个所述的半导体封装，其中，第三互连区域覆盖第二有源电子部件的一部分。
实施例36提供了实施例1-35中任一个所述的半导体封装，并且还包括：
设置在第二有源电子部件上并在第一互连区域和第三互连区域之间的热过孔。
实施例37提供了实施例1-36中任一个所述的半导体封装，其中，热过孔设置于第二有源电子部件的表面积之上、处于从第二有源电子部件的表面积的大约25％到50％的范围内。
实施例38提供了实施例1-37中任一个所述的半导体封装，其中，热过孔设置于第二有源电子部件的表面积之上、处于从第二有源电子部件的表面积的大约25％到35％的范围内。
实施例39提供了实施例1-38中任一个所述的半导体封装，其中，第一互连区域和第三互连区域位于第二有源电子部件的同一表面上。
实施例40提供了实施例1-39中任一个所述的半导体封装，其中，第三互连区域由衬底和第二有源电子部件之间的导线形成。
实施例41提供了实施例1-40中任一个所述的半导体封装，其中，第一有源电子部件是第一硅管芯。
实施例42提供了实施例1-41中任一个所述的半导体封装，其中，第一硅管芯选自由中央处理单元、现场可编程门阵列、片上系统或图形处理单元或其组合组成的组。
实施例43提供了实施例1-42中任一个所述的半导体封装，其中，第二有源电子部件是第二硅管芯。
实施例44提供了实施例1-43中任一个所述的半导体封装，其中，第二硅管芯选自由高带宽存储器、封装嵌入式存储器、闪存存储器、嵌入式非易失性存储器、III-V管芯、加速器和低功率双数据速率存储器组成的组。
实施例45提供了一种半导体封装，包括：
衬底，衬底包括：
交替的导电层和电介质层；
设置于衬底的外表面上的第一有源电子部件；
至少部分地嵌入衬底内的第二有源电子部件；
由第一有源电子部件和第二有源电子部件之间的多个互连形成的第一互连区域；
由第一有源电子部件和衬底之间的多个互连形成的第二互连区域；
由第二有源电子部件和衬底之间的多个互连形成的第三互连区域，
其中，第一互连区域的互连的密度大于第二互连区域和第三互连区域中的至少一个的互连的密度。
实施例46提供了实施例45所述的半导体封装，其中，导电层包括：
导电材料。
实施例47提供了实施例45-46中任一个所述的半导体封装，其中，导电材料是铜。
实施例48提供了实施例45-47中任一个所述的半导体封装，其中，电介质层包括：
电介质材料。
实施例49提供了实施例45-48中任一个所述的半导体封装，其中，第一互连区域的互连包括：
连接到第一有源电子部件的底表面和第二有源电子部件的顶表面的焊球。
实施例50提供了实施例45-49中任一个所述的半导体封装，其中，第一互连区域的互连包括：
连接到第一有源电子部件的底表面的焊球；以及
连接到第二有源电子部件的顶表面的过孔，
其中，焊球和过孔彼此连接。
实施例51提供了实施例45-50中任一个所述的半导体封装，其中，第二互连区域的互连包括：
连接到衬底的导电层和第一有源电子部件的焊球。
实施例52提供了实施例45-51中任一个所述的半导体封装，其中，第一互连区域的互连具有处于从大约20微米到大约80微米的范围内的间距。
实施例53提供了实施例45-52中任一个所述的半导体封装，其中，第一互连区域的互连具有处于从大约40微米到大约65微米的范围内的间距。
实施例54提供了实施例45-53中任一个所述的半导体封装，其中，第二互连区域的互连具有处于从大约85微米到大约500微米的范围内的间距。
实施例55提供了实施例45-54中任一个所述的半导体封装，其中，第二互连区域的互连具有处于从大约100微米到大约300微米的范围内的间距。
实施例56提供了实施例45-55中任一个所述的半导体封装，其中，第三互连区域的互连具有处于从大约85微米到大约500微米的范围内的间距。
实施例57提供了实施例45-56中任一个所述的半导体封装，其中，第三互连区域的互连具有处于从大约100微米到大约300微米的范围内的间距。
实施例58提供了实施例45-57中任一个所述的半导体封装，其中，第二互连区域的互连的密度和第三互连区域的互连的密度相同。
实施例59提供了实施例45-58中任一个所述的半导体封装，其中，第二互连区域的互连的密度和第三互连区域的互连的密度不同。
实施例60提供了实施例45-59中任一个所述的半导体封装，其中，第一互连区域包括第一有源电子部件的表面积的大约2％到大约15％。
实施例61提供了实施例45-60中任一个所述的半导体封装，其中，第一互连区域包括第一有源电子部件的表面积的大约2％到大约10％。
实施例62提供了实施例45-61中任一个所述的半导体封装，其中，第一互连区域包括第二有源电子部件的表面积的大约2％到大约15％。
实施例63提供了实施例45-62中任一个所述的半导体封装，其中，第一互连区域包括第二有源电子部件的表面积的大约2％到大约10％。
实施例64提供了实施例45-63中任一个所述的半导体封装，其中，第二互连区域包括第一有源电子部件的表面积的大约85％到大约95％。
实施例65提供了实施例45-64中任一个所述的半导体封装，其中，第二互连区域包括第一有源电子部件的表面积的大约90％到大约98％。
实施例66提供了实施例45-65中任一个所述的半导体封装，其中，第三互连区域包括第二有源电子部件的表面积的大约85％到大约95％。
实施例67提供了实施例45-66中任一个所述的半导体封装，其中，第三互连区域包括第二有源电子部件的表面积的大约90％到大约98％。
实施例68提供了实施例45-67中任一个所述的半导体封装，其中，第三互连区域由内插器形成，内插器包括：
顶表面；
底表面；以及
处于内插器和衬底之间的第四互连区域，
其中，底表面的第一部分连接到第三互连区域的互连；并且底表面的第二部分连接到第四互连区域的互连。
实施例69提供了实施例45-68中任一个所述的半导体封装，其中，内插器还包括：
从内插器的底表面延伸到内插器的顶表面的多个热过孔。
实施例70提供了实施例45-69中任一个所述的半导体封装，其中，第三互连区域的互连包括：
连接到内插器的底表面和第二有源电子部件的顶表面的焊球。
实施例71提供了实施例45-70中任一个所述的半导体封装，其中，第四互连区域包括多个互连。
实施例72提供了实施例45-71中任一个所述的半导体封装，其中，第四互连区域的互连包括：
连接到内插器的底表面和衬底的导电层的焊球。
实施例73提供了实施例45-72中任一个所述的半导体封装，其中，热过孔被定位在第二有源电子部件之上。
实施例74提供了实施例45-73中任一个所述的半导体封装，其中，热过孔由导热材料形成。
实施例75提供了实施例45-74中任一个所述的半导体封装，其中，导热材料是铜。
实施例76提供了实施例45-75中任一个所述的半导体封装，其中，第三互连区域由衬底的导电层的一部分形成。
实施例77提供了实施例45-76中任一个所述的半导体封装，其中，第三互连区域覆盖第二有源电子部件的一部分。
实施例78提供了实施例45-77中任一个所述的半导体封装，并且还包括：
设置在第二有源电子部件上并且在第一互连区域和第三互连区域之间的热过孔。
实施例79提供了实施例45-78中任一个所述的半导体封装，其中，热过孔设置于第二有源电子部件的表面积之上、处于从第二有源电子部件的表面积的大约25％到50％的范围内。
实施例80提供了实施例45-79中任一个所述的半导体封装，其中，热过孔设置于第二有源电子部件的表面积之上、处于从第二有源电子部件的表面积的大约25％到35％的范围内。
实施例81提供了实施例45-80中任一个所述的半导体封装，其中，第一互连区域和第三互连区域位于第二有源电子部件的同一表面上。
实施例82提供了实施例45-81中任一个所述的半导体封装，其中，第三互连区域由衬底和第二有源电子部件之间的导线形成。
实施例83提供了实施例45-82中任一个所述的半导体封装，其中，第一有源电子部件是第一硅管芯。
实施例84提供了实施例45-83中任一个所述的半导体封装，其中，第一硅管芯选自由中央处理单元、现场可编程门阵列、片上系统或图形处理单元或其组合组成的组。
实施例85提供了实施例45-84中任一个所述的半导体封装，其中，第二有源电子部件是第二硅管芯。
实施例86提供了实施例45-85中任一个所述的半导体封装，其中，第二硅管芯部件选自由高带宽存储器、封装嵌入式存储器、闪存存储器、嵌入式非易失性存储器、III-V管芯、加速器和低功率双数据速率存储器组成的组。
实施例87提供了实施例45-86中任一个所述的半导体封装，其中，电介质材料选自由累积膜、聚酰亚胺、双马来酰亚胺-三嗪(BT)树脂、环氧树脂、聚氨酯、苯并环丁烯(BCB)、高密度聚乙烯(HDPE)、或其组合组成的组。
实施例88提供了一种形成半导体封装的方法，包括：
在衬底上放置第一有源电子部件；
在衬底的凹陷中放置第二有源电子部件；
在第一有源电子部件和第二有源电子部件之间形成第一互连；
在第一有源电子部件和衬底之间形成第二互连；以及
在第二有源电子部件和衬底之间形成第三互连。
实施例89提供了实施例88的方法，并且还包括：
在衬底中形成凹陷。
实施例90提供了实施例88-89中任一个所述的方法，其中，凹陷是通过激光碾磨、湿法蚀刻、干法蚀刻或机械碾磨而形成在衬底中的。
实施例91提供了实施例88-90中任一个所述的方法，并且还包括：
将管芯附接膜分配到第二有源电子部件；以及
使管芯附接膜接触到衬底的凹陷。
实施例92提供了实施例88-91中任一个所述的方法，其中，形成第一互连包括：
将第一有源电子部件的第一组焊球与第二有源电子部件的第二组焊球对准；
使第一组焊球与第二组焊球接触；
对第一组焊球和第二组焊球进行加热；以及
使第一组焊球和第二组焊球冷却。
实施例93提供了实施例88-92中任一个所述的方法，其中，形成第二互连包括：
将第一有源电子部件的第三组焊球与衬底的导电层对准；
使第三组焊球与导电层接触；
对第三组焊球和导电层进行加热；以及
使第三组焊球和导电层冷却。
实施例94提供了实施例88-93中任一个所述的方法，其中，形成第三互连包括：
将内插器附接到第二有源电子部件。
实施例95提供了实施例88-94中任一个所述的方法，其中，将内插器附接到第二有源电子部件包括：
将内插器的第四组焊球与第二有源电子部件对准；
对第四组焊球进行加热；以及
使第四组焊球冷却。
实施例96提供了实施例88-95中任一个所述的方法，其中，第二有源电子部件包括：
第一多个过孔；
第二多个过孔；以及
热过孔。
实施例97提供了实施例88-96中任一个所述的方法，其中，第一多个过孔具有比第二多个过孔高的密度。
实施例98提供了实施例88-97中任一个所述的方法，其中，第一多个过孔具有处于从大约20微米到大约80微米的范围内的间距。
实施例99提供了实施例88-98中任一个所述的方法，其中，第一多个过孔具有处于从大约40微米到大约65微米的范围内的间距。
实施例100提供了实施例88-99中任一个所述的方法，其中，第二多个过孔具有处于从大约85微米到大约350微米的范围内的间距。
实施例101提供了实施例88-100中任一个所述的方法，其中，第二多个过孔具有处于从大约100微米到大约350微米的范围内的间距。
实施例102提供了实施例88-101中任一个所述的方法，并且还包括：
在电介质材料中涂覆第二有源电子部件。
实施例103提供了实施例88-102中任一个所述的方法，并且还包括：
对涂覆第二有源电子部件的电介质材料进行蚀刻以暴露第一多个过孔、第二多个过孔和热过孔。
实施例104提供了实施例88-103中任一个所述的方法，并且还包括：
在第二多个过孔和衬底之上镀敷导电材料层。
实施例105提供了实施例88-104中任一个所述的方法，其中，在第二有源电子部件和衬底之间形成第三互连包括：
利用导线将第二有源电子部件的一组互连连接到衬底的导电层。
实施例106提供了实施例88-105中任一个所述的方法，其中，第一有源电子部件是第一硅管芯。
实施例107提供了实施例88-106中任一个所述的方法，其中，第一硅管芯选自由中央处理单元、现场可编程门阵列或其组合组成的组。
实施例108提供了实施例88-107中任一个所述的方法，其中，第二有源电子部件是第二硅管芯。
实施例109提供了实施例88-108中任一个所述的方法，其中，第二硅管芯电子部件选自由高带宽存储器、封装嵌入式存储器、闪存存储器、嵌入式非易失性存储器、图形卡、III-V管芯、加速器和低功率双数据速率存储器组成的组。

Claims (25)

1.一种半导体封装，包括：
衬底，其包括：
多个导电层和电介质层；
设置于所述衬底的外表面上的第一有源硅管芯；
至少部分地嵌入在所述衬底内的第二有源硅管芯；
由所述第一有源电子部件和所述第二有源电子部件之间的多个互连形成的第一互连区域；
由所述第一有源电子部件和所述衬底之间的多个互连形成的第二互连区域；以及
由所述第二有源电子部件和所述衬底之间的多个互连形成的第三互连区域，
其中，所述第一互连区域的互连的密度大于所述第二互连区域和所述第三互连区域中的至少一个的互连的密度。
2.根据权利要求1所述的半导体封装，其中，所述导电层包括：
导电材料。
3.根据权利要求2所述的半导体封装，其中，所述导电材料是铜。
4.根据权利要求1所述的半导体封装，其中，所述电介质层包括：
电介质材料。
5.根据权利要求4所述的半导体封装，其中，所述电介质材料选自由聚酰亚胺、双马来酰亚胺-三嗪(BT)树脂、环氧树脂、聚氨酯、苯并环丁烯(BCB)、高密度聚乙烯(HDPE)、或其组合组成的组。
6.根据权利要求1所述的半导体封装，其中，所述第一互连区域具有的互连密度比所述第二互连区域和所述第三互连区域中的至少一个的互连密度高。
7.根据权利要求6所述的半导体封装，其中，所述第一互连区域的互连具有从大约20微米到大约80微米的范围内的间距。
8.根据权利要求6所述的半导体封装，其中，所述第二互连区域的互连具有从大约85微米到大约350微米的范围内的间距。
9.根据权利要求6所述的半导体封装，其中，所述第三互连区域的互连具有从大约85微米到大约350微米的范围内的间距。
10.根据权利要求6所述的半导体封装，其中，所述第二互连区域的密度和所述第三互连区域的密度相同。
11.根据权利要求6所述的半导体封装，其中，所述第二互连区域的密度和所述第三互连区域的密度不同。
12.根据权利要求1所述的半导体封装，其中，所述第三互连区域由内插器形成，所述内插器包括：
顶表面；
底表面；以及
由所述内插器和所述衬底之间的多个互连形成的第四互连区域，
其中，所述底表面的第一部分连接到所述第三互连区域的互连；并且所述底表面的第二部分连接到所述第四互连区域的互连。
13.一种半导体封装，包括：
衬底，其包括：
多个导电层和电介质层；
设置于所述衬底的外表面上的第一有源电子部件；
至少部分地嵌入在所述衬底内的第二有源电子部件；
由所述第一有源电子部件和所述第二有源电子部件之间的多个互连形成的第一互连区域；
由所述第一有源电子部件和所述衬底之间的多个互连形成的第二互连区域；以及
由所述第二有源电子部件和所述衬底之间的多个互连形成的第三互连区域，
其中，所述第一互连区域的互连的密度大于所述第二互连区域和所述第三互连区域中的至少一个的互连的密度。
14.根据权利要求13所述的半导体封装，其中，所述第一互连区域的互连包括：
连接到所述第一有源电子部件的底表面的焊球；以及
连接到所述第二有源电子部件的顶表面的过孔，
其中，所述焊球和所述过孔彼此连接。
15.根据权利要求13所述的半导体封装，其中，所述第二互连区域的互连包括：
连接到所述衬底的导电层和所述第一有源电子部件的焊球。
16.根据权利要求13所述的半导体封装，其中，所述第一有源电子部件和所述第二有源电子部件是第一硅管芯和第二硅管芯。
17.根据权利要求13所述的半导体封装，并且是中央处理单元、现场可编程门阵列、片上系统或图形处理单元或其组合。
18.根据权利要求13所述的半导体封装，所述第二硅管芯部件选自由高带宽存储器、封装嵌入式存储器、闪存存储器、嵌入式非易失性存储器、III-V管芯、加速器和低功率双数据速率存储器组成的组。
19.根据权利要求13所述的半导体封装，其中，所述第三互连区域由内插器形成，所述内插器包括：
顶表面；
底表面；以及
由所述内插器和所述衬底之间的多个互连形成的第四互连区域，
其中，所述底表面的第一部分连接到所述第三互连区域的互连；并且所述底表面的第二部分连接到所述第四互连区域的互连。
20.根据权利要求19所述的半导体封装，其中，所述内插器还包括：
从所述内插器的底表面延伸到所述内插器的顶表面的多个热过孔。
21.根据权利要求13所述的半导体封装，其中，所述第三互连区域由所述衬底的导电层的一部分形成。
22.根据权利要求21所述的半导体封装，其中，所述第三互连区域覆盖所述第二有源电子部件的一部分。
23.一种形成半导体封装的方法，包括：
在衬底上放置第一有源电子部件；
在所述衬底的凹陷中放置第二有源电子部件；
在所述第一有源电子部件和所述第二有源电子部件之间形成第一互连；
在所述第一有源电子部件和所述衬底件之间形成第二互连；以及
在所述第二有源电子部件和所述衬底之间形成第三互连。
24.根据权利要求23所述的方法，其中，形成所述第三互连包括：
将内插器附接到所述第二有源电子部件。
25.根据权利要求24所述的方法，其中，将所述内插器附接到所述第二有源电子部件包括：
将所述内插器的一组焊球与所述第二有源电子部件对准；
对所述一组焊球进行加热；以及
使所述一组焊球冷却。
CN201680088848.1A 2016-09-30 2016-09-30 具有高密度互连的半导体封装 Pending CN109844945A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2016/054856 WO2018063351A1 (en) 2016-09-30 2016-09-30 Semiconductor packaging with high density interconnects

Publications (1)

Publication Number Publication Date
CN109844945A true CN109844945A (zh) 2019-06-04

Family

ID=61760035

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201680088848.1A Pending CN109844945A (zh) 2016-09-30 2016-09-30 具有高密度互连的半导体封装

Country Status (5)

Country Link
US (2) US10971453B2 (zh)
KR (1) KR102621950B1 (zh)
CN (1) CN109844945A (zh)
DE (1) DE112016007306T5 (zh)
WO (1) WO2018063351A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102621950B1 (ko) 2016-09-30 2024-01-05 타호 리서치 리미티드 고밀도 상호접속을 갖는 반도체 패키징
US11735548B2 (en) * 2018-08-08 2023-08-22 Kuprion Inc. Electronics assemblies employing copper in multiple locations
KR20210019308A (ko) 2019-08-12 2021-02-22 삼성전자주식회사 반도체 패키지
US20230245947A1 (en) * 2022-01-31 2023-08-03 Taiwan Semiconductor Manufacturing Co.,Ltd. Integrated circuit package and method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100327424A1 (en) * 2009-06-24 2010-12-30 Henning Braunisch Multi-chip package and method of providing die-to-die interconnects in same
US20130181354A1 (en) * 2012-01-12 2013-07-18 Broadcom Corporation Semiconductor Interposer Having a Cavity for Intra-Interposer Die
CN103258806A (zh) * 2013-05-08 2013-08-21 日月光半导体制造股份有限公司 具桥接结构的半导体封装构造及其制造方法
KR20140095182A (ko) * 2013-01-24 2014-08-01 삼성전자주식회사 적층된 다이 패키지, 이를 포함하는 시스템 및 이의 제조 방법

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06291216A (ja) * 1993-04-05 1994-10-18 Sony Corp 基板及びセラミックパッケージ
JP4581768B2 (ja) * 2005-03-16 2010-11-17 ソニー株式会社 半導体装置の製造方法
KR20080014004A (ko) * 2005-06-06 2008-02-13 로무 가부시키가이샤 인터포저 및 반도체 장치
US7994619B2 (en) * 2005-11-01 2011-08-09 Stats Chippac Ltd. Bridge stack integrated circuit package system
US10475759B2 (en) * 2011-10-11 2019-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure having dies with connectors of different sizes
KR101298280B1 (ko) 2011-10-25 2013-08-26 삼성전기주식회사 임베디드 인쇄회로기판 및 이의 제조 방법
US9490196B2 (en) * 2011-10-31 2016-11-08 Intel Corporation Multi die package having a die and a spacer layer in a recess
CN104335342A (zh) * 2012-03-13 2015-02-04 英特尔公司 反向微电子封装上的微电子器件附着
US8736076B2 (en) 2012-08-10 2014-05-27 Lsi Corporation Multi-chip stacking of integrated circuit devices using partial device overlap
KR20140086416A (ko) * 2012-12-28 2014-07-08 삼성전기주식회사 반도체 패키지 및 그 제조방법
KR102154039B1 (ko) * 2013-12-23 2020-09-09 에스케이하이닉스 주식회사 접속 조인트부의 크랙이 억제된 칩 내장형 패키지
US9666559B2 (en) * 2014-09-05 2017-05-30 Invensas Corporation Multichip modules and methods of fabrication
KR102621950B1 (ko) 2016-09-30 2024-01-05 타호 리서치 리미티드 고밀도 상호접속을 갖는 반도체 패키징

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100327424A1 (en) * 2009-06-24 2010-12-30 Henning Braunisch Multi-chip package and method of providing die-to-die interconnects in same
US20130181354A1 (en) * 2012-01-12 2013-07-18 Broadcom Corporation Semiconductor Interposer Having a Cavity for Intra-Interposer Die
KR20140095182A (ko) * 2013-01-24 2014-08-01 삼성전자주식회사 적층된 다이 패키지, 이를 포함하는 시스템 및 이의 제조 방법
CN103258806A (zh) * 2013-05-08 2013-08-21 日月光半导体制造股份有限公司 具桥接结构的半导体封装构造及其制造方法

Also Published As

Publication number Publication date
US10971453B2 (en) 2021-04-06
US11881457B2 (en) 2024-01-23
KR102621950B1 (ko) 2024-01-05
DE112016007306T5 (de) 2019-06-19
US20190259705A1 (en) 2019-08-22
WO2018063351A1 (en) 2018-04-05
KR20190049713A (ko) 2019-05-09
US20210193583A1 (en) 2021-06-24

Similar Documents

Publication Publication Date Title
KR101834389B1 (ko) 웨이퍼 레벨의 적층형 다이 패키지
CN100511676C (zh) 微电子封装方法和装置
CN1322566C (zh) 半导体装置
CN101944518B (zh) 半导体结构体及其制造方法、半导体器件及其制造方法
US6701614B2 (en) Method for making a build-up package of a semiconductor
US6836025B2 (en) Semiconductor device configured to be surface mountable
CN110518000A (zh) 半导体器件和制造方法
CN109844945A (zh) 具有高密度互连的半导体封装
CN105144416B (zh) 具有光电子器件的照明设备
US7462508B2 (en) Stack type semiconductor package module utilizing solder coated stacking protrusions and method for manufacturing the same
CN107644860A (zh) 集成扇出型封装
US10109618B2 (en) Bonding structure between semiconductor device package
CN105304613A (zh) 半导体器件和方法
US9247631B2 (en) Method for fabricating heat dissipation substrate
US10777482B2 (en) Multipart lid for a semiconductor package with multiple components
CN110858576B (zh) 覆晶封装基板及其制法
CN110459521A (zh) 覆晶封装基板和电子封装件
CN110268520A (zh) 用于集成功率芯片以及形成散热器的汇流条的方法
US20030146520A1 (en) Flip-chip package with a heat spreader
CN101533818B (zh) 集成电路元件的封装结构及其制造方法
JP2006525660A (ja) ケース型熱管理素子およびその製造方法
CN113097201B (zh) 半导体封装结构、方法、器件和电子产品
US20210202345A1 (en) Packages with separate communication and heat dissipation paths
EP1369919A1 (en) Flip chip package
CN113078149B (zh) 半导体封装结构、方法、器件和电子产品

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20221026

Address after: Irish Dublin

Applicant after: Taihao Research Co.,Ltd.

Address before: California, USA

Applicant before: INTEL Corp.