JP6392163B2 - 配線基板及びその製造方法、半導体装置 - Google Patents
配線基板及びその製造方法、半導体装置 Download PDFInfo
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- JP6392163B2 JP6392163B2 JP2015085102A JP2015085102A JP6392163B2 JP 6392163 B2 JP6392163 B2 JP 6392163B2 JP 2015085102 A JP2015085102 A JP 2015085102A JP 2015085102 A JP2015085102 A JP 2015085102A JP 6392163 B2 JP6392163 B2 JP 6392163B2
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Description
[第1の実施の形態に係る配線基板の構造]
まず、第1の実施の形態に係る配線基板の構造について説明する。図1は、第1の実施の形態に係る配線基板を例示する図であり、図1(b)は平面図、図1(a)は図1(b)のA−A線に沿う断面図である。
次に、第1の実施の形態に係る配線基板の製造方法について説明する。図2〜図9は、第1の実施の形態に係る配線基板の製造工程を例示する図である。なお、第1の実施の形態に係る配線基板の製造工程の説明で用いる断面図は、全て図1(a)に対応する断面図である。
第1の実施の形態の変形例1では、第1開口部10y及び第2開口20yを充填する接着層と、配線部Zを放熱板80上に固定する接着層とを個別に設ける例を示す。なお、第1の実施の形態の変形例1において、既に説明した実施の形態と同一構成部品についての説明は省略する。
第1の実施の形態の変形例2では、第1の実施の形態とは貫通配線を形成する領域が異なる配線基板の例を示す。なお、第1の実施の形態の変形例2において、既に説明した実施の形態と同一構成部品についての説明は省略する。
第1の実施の形態の変形例3では、第1の実施の形態とは貫通配線を形成する配線の平面形状が異なる配線基板の例を示す。なお、第1の実施の形態の変形例3において、既に説明した実施の形態と同一構成部品についての説明は省略する。
第2の実施の形態では、第1の実施の形態で示した配線基板に半導体素子(発光素子)を搭載した半導体装置の例を示す。なお、第2の実施の形態において、既に説明した実施の形態と同一構成部品についての説明は省略する。
第2の実施の形態の変形例1では、第1の実施の形態で示した配線基板に半導体素子(発光素子)を搭載した半導体装置の他の例を示す。なお、第2の実施の形態の変形例1において、既に説明した実施の形態と同一構成部品についての説明は省略する。
第2の実施の形態の変形例2では、第1の実施の形態で示した配線基板に半導体素子(発光素子)を搭載した半導体装置の他の例を示す。なお、第2の実施の形態の変形例2において、既に説明した実施の形態と同一構成部品についての説明は省略する。
10 基板
10x 貫通孔
10y 第1開口部
20、70、70A、70B、190 接着層
20a 接着層の外縁部
20y 第2開口部
30A 金属層
31〜33 配線
41〜45 めっき膜
50 貫通配線
60 絶縁層
60x、60y 開口部
80 放熱板
100、100A、100B 半導体装置
110 電子部品
120 半導体素子
130 電気接続用端子
135 熱拡散用端子
139 はんだ
140 封止樹脂
150 基板
160 配線
170 リフレクタ
180 ボンディングワイヤ
T スペース
Z 配線部
Claims (10)
- 半導体素子又は電子部品が搭載される配線基板であって、
放熱板と、
一方の面及び他方の面を備え、前記他方の面が第1接着層を介して前記放熱板に接着された基板と、
前記基板の一方の面に第2接着層を介して設けられた、前記半導体素子とは電気的に接続されない熱拡散用配線と、
前記基板及び前記第2接着層を厚さ方向に貫通して設けられ、前記熱拡散用配線の前記第2接着層側の面と接合された複数の貫通配線と、を有し、
前記基板には、夫々の前記貫通配線の周囲側面を露出する第1開口部が設けられ、
前記第2接着層には、前記第1開口部と連通し、夫々の前記貫通配線の周囲側面及び前記熱拡散用配線の前記第2接着層側の面を露出する第2開口部が設けられ、
前記第2開口部は、前記第1開口部よりも幅広に形成され、
前記第1接着層は、前記基板の他方の面、前記基板の前記第1開口部内に露出する側面に接しており、前記第1開口部及び前記第2開口部を充填していることを特徴とする配線基板。 - 前記基板上の熱拡散用配線と同一平面に設けられた、前記半導体素子と電気的に接続される電気接続用配線と、
前記基板上に設けられ、前記熱拡散用配線を露出する開口部を備えた絶縁層と、を有し、
平面視において、前記熱拡散用配線の形成領域は、前記絶縁層の前記熱拡散用配線を露出する開口部の領域よりも外側に延在し、前記電気接続用配線の形成領域よりも大きく設けられていることを特徴とする請求項1記載の配線基板。 - 前記半導体素子は発光素子であり、
前記絶縁層は、前記発光素子の照射する光を反射する反射膜であることを特徴とする請求項2記載の配線基板。 - 前記電気接続用配線は平面上のみに形成され、前記電気接続用配線と平面視で重複する領域には前記貫通配線は存在しないことを特徴とする請求項2又は3記載の配線基板。
- 前記複数の貫通配線は、平面視において、前記貫通配線の外形の一部が、搭載される前記半導体素子の外形の一部と重複する範囲に配置されていることを特徴とする請求項1乃至4の何れか一項記載の配線基板。
- 前記基板はポリイミド系樹脂であることを特徴とする請求項1乃至5の何れか一項記載の配線基板。
- 前記第1接着層はフィラーを含有することを特徴とする請求項1乃至6の何れか一項記載の配線基板。
- 請求項1乃至7の何れか一項記載の配線基板と、
前記熱拡散用配線上に搭載された前記半導体素子又は前記電子部品と、を有する半導体装置。 - 半導体素子又は電子部品が搭載される配線基板の製造方法であって、
基板の一方の面に第2接着層を介して、前記半導体素子とは電気的に接続されない熱拡散用配線を形成する工程と、
前記基板及び前記第2接着層を厚さ方向に貫通し、前記熱拡散用配線の前記第2接着層側の面と接合する複数の貫通配線を形成する工程と、
前記基板及び前記第2接着層をエッチングし、前記基板に夫々の前記貫通配線の周囲側面を露出する第1開口部を形成すると共に、前記第2接着層に前記第1開口部と連通し、夫々の前記貫通配線の周囲側面及び前記熱拡散用配線の前記第2接着層側の面を露出する第2開口部を形成する工程と、
前記基板の他方の面を第1接着層を介して放熱板に接着する工程と、を有し、
前記第1開口部及び前記第2開口部を形成する工程では、前記第2開口部は前記第1開口部よりも幅広に形成され、
前記接着する工程では、前記第1接着層は、前記基板の他方の面に接し、前記第1開口部及び前記第2開口部に充填されることを特徴とする配線基板の製造方法。 - 前記貫通配線を形成する工程では、前記貫通配線の他端が前記基板の他方の面よりも凹んだ位置に形成されることを特徴とする請求項9記載の配線基板の製造方法。
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