TW200614255A - Semiconductor memory device with on die termination circuit - Google Patents

Semiconductor memory device with on die termination circuit

Info

Publication number
TW200614255A
TW200614255A TW093141293A TW93141293A TW200614255A TW 200614255 A TW200614255 A TW 200614255A TW 093141293 A TW093141293 A TW 093141293A TW 93141293 A TW93141293 A TW 93141293A TW 200614255 A TW200614255 A TW 200614255A
Authority
TW
Taiwan
Prior art keywords
die termination
memory device
semiconductor memory
termination circuit
data input
Prior art date
Application number
TW093141293A
Other languages
English (en)
Other versions
TWI303436B (en
Inventor
Hee-Bok Kang
Jin-Hong Ahn
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200614255A publication Critical patent/TW200614255A/zh
Application granted granted Critical
Publication of TWI303436B publication Critical patent/TWI303436B/zh

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048Data bus control circuits, e.g. precharging, presetting, equalising
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264Arrangements for coupling to transmission lines
    • H04L25/028Arrangements specific to the transmitter end
    • H04L25/0284Arrangements to ensure DC-balance
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10Aspects relating to interfaces of memory device to external buses
    • G11C2207/105Aspects related to pads, pins or terminals

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)
  • Memory System (AREA)
TW093141293A 2004-10-30 2004-12-30 Semiconductor memory device with on die termination circuit TWI303436B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020040087725A KR100670702B1 (ko) 2004-10-30 2004-10-30 온다이 터미네이션 회로를 구비한 반도체 메모리 장치

Publications (2)

Publication Number Publication Date
TW200614255A true TW200614255A (en) 2006-05-01
TWI303436B TWI303436B (en) 2008-11-21

Family

ID=36261081

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093141293A TWI303436B (en) 2004-10-30 2004-12-30 Semiconductor memory device with on die termination circuit

Country Status (5)

Country Link
US (1) US7161378B2 (zh)
JP (1) JP4403462B2 (zh)
KR (1) KR100670702B1 (zh)
CN (1) CN100508067C (zh)
TW (1) TWI303436B (zh)

Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6282145B1 (en) 1999-01-14 2001-08-28 Silicon Storage Technology, Inc. Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system
US7345512B2 (en) 2004-05-04 2008-03-18 Silicon Storage Technology, Inc. Sense amplifier for low voltage high speed sensing
US7439760B2 (en) 2005-12-19 2008-10-21 Rambus Inc. Configurable on-die termination
KR100681879B1 (ko) 2006-01-16 2007-02-15 주식회사 하이닉스반도체 온-다이 터미네이션 제어 장치
KR100744130B1 (ko) * 2006-02-20 2007-08-01 삼성전자주식회사 터미네이션 회로 및 이를 구비하는 반도체 메모리 장치
KR100681881B1 (ko) 2006-04-06 2007-02-15 주식회사 하이닉스반도체 반도체 메모리의 온 다이 터미네이션 장치 및 방법
KR100718049B1 (ko) 2006-06-08 2007-05-14 주식회사 하이닉스반도체 반도체 메모리의 온 다이 터미네이션 장치 및 그 제어방법
KR100780646B1 (ko) 2006-10-31 2007-11-30 주식회사 하이닉스반도체 온 다이 터미네이션 장치 및 이를 포함하는 반도체장치.
TWI314326B (en) * 2006-11-23 2009-09-01 Realtek Semiconductor Corp Output driving circuit
US8599631B2 (en) 2006-12-21 2013-12-03 Rambus Inc. On-die termination of address and command signals
KR100857854B1 (ko) 2007-01-10 2008-09-10 주식회사 하이닉스반도체 효과적으로 온다이 터미네이션 동작 타이밍 조절이 가능한반도체 메모리 장치
KR100909251B1 (ko) 2007-01-31 2009-07-23 주식회사 하이닉스반도체 아날로그-디지털 변환기 및 이를 포함하는 온도정보출력장치
KR100821585B1 (ko) 2007-03-12 2008-04-15 주식회사 하이닉스반도체 반도체 메모리 장치의 온 다이 터미네이션 회로
KR100857438B1 (ko) 2007-03-13 2008-09-10 주식회사 하이닉스반도체 전압 생성 회로 및 이를 이용한 반도체 메모리 장치의 기준전압 생성 회로
KR100897253B1 (ko) 2007-04-11 2009-05-14 주식회사 하이닉스반도체 반도체 집적 회로 및 그의 제어 방법
KR100897255B1 (ko) 2007-04-12 2009-05-14 주식회사 하이닉스반도체 반도체 메모리 장치의 온 다이 터미네이션 회로 및 방법
KR100875673B1 (ko) 2007-05-14 2008-12-24 주식회사 하이닉스반도체 온 다이 터미네이션 장치 및 이의 캘리브래이션 방법
KR100902104B1 (ko) 2007-06-08 2009-06-09 주식회사 하이닉스반도체 반도체 메모리장치
KR100845807B1 (ko) 2007-06-13 2008-07-14 주식회사 하이닉스반도체 온 다이 터미네이션 제어신호 생성회로
KR100879783B1 (ko) 2007-06-26 2009-01-22 주식회사 하이닉스반도체 온 다이 터미네이션 장치 및 이를 포함하는 반도체메모리장치
KR100879782B1 (ko) 2007-06-26 2009-01-22 주식회사 하이닉스반도체 온 다이 터미네이션 장치 및 이를 포함하는 반도체메모리장치
KR100886644B1 (ko) 2007-08-29 2009-03-04 주식회사 하이닉스반도체 온 다이 터미네이션 장치의 캘리브래이션 회로
KR100845811B1 (ko) 2007-09-05 2008-07-14 주식회사 하이닉스반도체 디지털/아날로그 변환회로 및 이를 이용한 온 다이터미네이션 조정 장치
US7876123B2 (en) * 2007-10-09 2011-01-25 Lsi Corporation High speed multiple memory interface I/O cell
JP5145879B2 (ja) * 2007-11-07 2013-02-20 セイコーエプソン株式会社 Odt制御機能を備えたddrメモリシステム
TW200921595A (en) * 2007-11-14 2009-05-16 Darfon Electronics Corp Multi-lamp backlight apparatus
JP2009252322A (ja) * 2008-04-09 2009-10-29 Nec Electronics Corp 半導体メモリ装置
JP5430880B2 (ja) * 2008-06-04 2014-03-05 ピーエスフォー ルクスコ エスエイアールエル メモリモジュール及びその使用方法、並びにメモリシステム
DE102008045707A1 (de) * 2008-09-04 2010-03-11 Micronas Gmbh Leiterplatine mit Terminierung einer T-förmigen Signalleitung
US7915912B2 (en) * 2008-09-24 2011-03-29 Rambus Inc. Signal lines with internal and external termination
US7741867B2 (en) * 2008-10-30 2010-06-22 Hewlett-Packard Development Company, L.P. Differential on-line termination
KR101626468B1 (ko) 2009-02-10 2016-06-02 삼성전자주식회사 누설 전류 차단기능을 갖는 데이터 처리장치의 메모리 모듈
EP2693641A1 (en) * 2009-02-12 2014-02-05 Mosaid Technologies Incorporated Termination circuit for on-die termination
KR101053530B1 (ko) 2009-07-31 2011-08-03 주식회사 하이닉스반도체 반도체 메모리 장치의 온도 측정 범위 보정 회로
KR101027689B1 (ko) 2009-09-30 2011-04-12 주식회사 하이닉스반도체 데이터 드라이빙 임피던스 자동 조정 회로 및 이를 이용한 반도체 집적회로
KR101789077B1 (ko) * 2010-02-23 2017-11-20 삼성전자주식회사 온-다이 터미네이션 회로, 데이터 출력 버퍼, 반도체 메모리 장치, 메모리 모듈, 온-다이 터미네이션 회로의 구동 방법, 데이터 출력 버퍼의 구동 방법 및 온-다이 터미네이션 트레이닝 방법
CN102915756B (zh) * 2012-10-09 2015-05-20 无锡江南计算技术研究所 Ddr3信号端接结构
US9088445B2 (en) 2013-03-07 2015-07-21 Qualcomm Incorporated Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed
US9218859B2 (en) 2013-03-20 2015-12-22 Kabushiki Kaisha Toshiba Semiconductor memory device
US10083728B2 (en) 2013-09-06 2018-09-25 Mediatek Inc. Memory controller, memory module and memory system
KR101620292B1 (ko) 2014-08-08 2016-05-12 주식회사 창공 세라믹도장의 전처리개선방법
US9571098B2 (en) * 2014-08-11 2017-02-14 Samsung Electronics Co., Ltd. Signal receiving circuits including termination resistance having adjustable resistance value, operating methods thereof, and storage devices therewith
KR102219451B1 (ko) * 2014-09-22 2021-02-24 삼성전자주식회사 스토리지 컨트롤러, 이의 동작 방법 및 이를 포함하는 솔리드 스테이트 디스크
US9910482B2 (en) * 2015-09-24 2018-03-06 Qualcomm Incorporated Memory interface with adjustable voltage and termination and methods of use
CN105575419B (zh) * 2015-12-17 2018-04-27 上海斐讯数据通信技术有限公司 同步动态随机存储器
US9917589B2 (en) * 2016-02-02 2018-03-13 Samsung Electronics Co., Ltd. Transmitter circuit and receiver circuit for operating under low voltage
US20170243628A1 (en) * 2016-02-22 2017-08-24 Mediatek Inc. Termination topology of memory system and associated memory module and control method
US10468073B2 (en) * 2017-12-29 2019-11-05 Sandisk Technologies Llc Transmission line optimization for multi-die systems
US10270450B1 (en) * 2018-08-23 2019-04-23 Xilinx, Inc. Unified low power bidirectional port
US11302645B2 (en) 2020-06-30 2022-04-12 Western Digital Technologies, Inc. Printed circuit board compensation structure for high bandwidth and high die-count memory stacks
US11456022B2 (en) 2020-06-30 2022-09-27 Western Digital Technologies, Inc. Distributed grouped terminations for multiple memory integrated circuit systems
US11750190B2 (en) 2020-12-14 2023-09-05 Intel Corporation Encoded on-die termination for efficient multipackage termination
CN117198370A (zh) * 2022-05-30 2023-12-08 长鑫存储技术有限公司 一种终结阻抗参数的产生方法和测试系统

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6026456A (en) 1995-12-15 2000-02-15 Intel Corporation System utilizing distributed on-chip termination
JPH1020974A (ja) 1996-07-03 1998-01-23 Fujitsu Ltd バス構造及び入出力バッファ
US6560290B2 (en) 1998-01-20 2003-05-06 Silicon Image, Inc. CMOS driver and on-chip termination for gigabaud speed data communication
US6414512B1 (en) 2000-04-04 2002-07-02 Pixelworks, Inc. On-chip termination circuit
US6411122B1 (en) 2000-10-27 2002-06-25 Intel Corporation Apparatus and method for dynamic on-die termination in an open-drain bus architecture system
US6424170B1 (en) * 2001-05-18 2002-07-23 Intel Corporation Apparatus and method for linear on-die termination in an open drain bus architecture system
KR100389928B1 (ko) * 2001-07-20 2003-07-04 삼성전자주식회사 액티브 터미네이션 제어를 위한 반도체 메모리 시스템
US6724082B2 (en) 2001-07-23 2004-04-20 Intel Corporation Systems having modules with selectable on die terminations
US6754129B2 (en) * 2002-01-24 2004-06-22 Micron Technology, Inc. Memory module with integrated bus termination
KR100468728B1 (ko) * 2002-04-19 2005-01-29 삼성전자주식회사 반도체 집적회로의 온-칩 터미네이터, 그 제어 회로 및 그제어 방법
US6807650B2 (en) 2002-06-03 2004-10-19 International Business Machines Corporation DDR-II driver impedance adjustment control algorithm and interface circuits
KR100502408B1 (ko) * 2002-06-21 2005-07-19 삼성전자주식회사 액티브 터미네이션을 내장한 메모리 장치의 파워-업시퀀스를 제어하는 메모리 시스템과 그 파워-업 및 초기화방법
DE10246741B4 (de) 2002-10-07 2007-04-19 Infineon Technologies Ag Verfahren und Halbleitereinrichtung zum Abgleich von Schnittstelleneinrichtungen
US6885959B2 (en) * 2002-10-29 2005-04-26 Intel Corporation Circuit and method for calibrating DRAM pullup Ron to pulldown Ron
KR100464437B1 (ko) * 2002-11-20 2004-12-31 삼성전자주식회사 온칩 dc 전류 소모를 최소화할 수 있는 odt 회로와odt 방법 및 이를 구비하는 메모리장치를 채용하는메모리 시스템
KR100532426B1 (ko) 2003-03-25 2005-11-30 삼성전자주식회사 온-칩 터미네이션 저항의 미스매치를 보상할 수 있는반도체 장치
KR100502664B1 (ko) 2003-04-29 2005-07-20 주식회사 하이닉스반도체 온 다이 터미네이션 모드 전환 회로 및 그방법
KR100532431B1 (ko) 2003-04-29 2005-11-30 삼성전자주식회사 부정합되는 온-다이 터미네이션 회로 및 터미네이션 방법
US6980020B2 (en) * 2003-12-19 2005-12-27 Rambus Inc. Calibration methods and circuits for optimized on-die termination
US7173450B2 (en) * 2004-06-01 2007-02-06 Hewlett-Packard Development Company, L.P. Bus controller

Also Published As

Publication number Publication date
CN1770323A (zh) 2006-05-10
US7161378B2 (en) 2007-01-09
CN100508067C (zh) 2009-07-01
JP2006129423A (ja) 2006-05-18
KR20060038629A (ko) 2006-05-04
KR100670702B1 (ko) 2007-01-17
JP4403462B2 (ja) 2010-01-27
US20060091900A1 (en) 2006-05-04
TWI303436B (en) 2008-11-21

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