DE602004011809D1 - Tstelle - Google Patents
TstelleInfo
- Publication number
- DE602004011809D1 DE602004011809D1 DE602004011809T DE602004011809T DE602004011809D1 DE 602004011809 D1 DE602004011809 D1 DE 602004011809D1 DE 602004011809 T DE602004011809 T DE 602004011809T DE 602004011809 T DE602004011809 T DE 602004011809T DE 602004011809 D1 DE602004011809 D1 DE 602004011809D1
- Authority
- DE
- Germany
- Prior art keywords
- pull
- voltage reference
- reference node
- calibration terminal
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2254—Calibration
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dram (AREA)
- Logic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Bipolar Transistors (AREA)
- Magnetic Heads (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Tests Of Electronic Circuits (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/714,075 US7095245B2 (en) | 2003-11-14 | 2003-11-14 | Internal voltage reference for memory interface |
US714075 | 2003-11-14 | ||
PCT/US2004/036825 WO2005050656A1 (en) | 2003-11-14 | 2004-11-05 | Internal voltage reference for memory interface |
Publications (2)
Publication Number | Publication Date |
---|---|
DE602004011809D1 true DE602004011809D1 (de) | 2008-03-27 |
DE602004011809T2 DE602004011809T2 (de) | 2009-02-05 |
Family
ID=34573880
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602004011809T Active DE602004011809T2 (de) | 2003-11-14 | 2004-11-05 | Interne spannungsdifferenz für eine speicherschnittstelle |
Country Status (8)
Country | Link |
---|---|
US (1) | US7095245B2 (de) |
EP (1) | EP1683156B1 (de) |
JP (1) | JP4422153B2 (de) |
CN (1) | CN1906696B (de) |
AT (1) | ATE386326T1 (de) |
DE (1) | DE602004011809T2 (de) |
TW (1) | TWI294217B (de) |
WO (1) | WO2005050656A1 (de) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4944793B2 (ja) * | 2005-12-15 | 2012-06-06 | 株式会社アドバンテスト | 試験装置、及びピンエレクトロニクスカード |
US7729168B2 (en) | 2007-06-28 | 2010-06-01 | Intel Corporation | Reduced signal level support for memory devices |
US20090009212A1 (en) * | 2007-07-02 | 2009-01-08 | Martin Brox | Calibration system and method |
US7936812B2 (en) * | 2007-07-02 | 2011-05-03 | Micron Technology, Inc. | Fractional-rate decision feedback equalization useful in a data transmission system |
KR101001635B1 (ko) * | 2008-06-30 | 2010-12-17 | 주식회사 하이닉스반도체 | 반도체 패키지, 이를 갖는 적층 반도체 패키지 및 적층반도체 패키지의 하나의 반도체 칩 선택 방법 |
US7830285B2 (en) * | 2008-07-10 | 2010-11-09 | Lantiq Deutschland Gmbh | Circuit with calibration circuit portion |
US7859298B1 (en) * | 2009-06-30 | 2010-12-28 | Intel Corporation | Method and system to facilitate configurable input/output (I/O) termination voltage reference |
DE112011106018B4 (de) * | 2011-12-23 | 2017-08-03 | Intel Corporation | Leistungsdrosselung des dynamischen Speichers |
US8797084B2 (en) | 2012-08-31 | 2014-08-05 | International Business Machines Corporation | Calibration schemes for charge-recycling stacked voltage domains |
US9715467B2 (en) | 2012-11-26 | 2017-07-25 | Rambus Inc. | Calibration protocol for command and address bus voltage reference in low-swing single-ended signaling |
CN104076896B (zh) * | 2014-06-24 | 2016-09-21 | 北京空间机电研究所 | 一种高等级ddr供电电路 |
CN105304110B (zh) * | 2015-11-26 | 2019-02-12 | 上海兆芯集成电路有限公司 | 数据接收芯片的控制方法 |
CN105489235B (zh) * | 2015-11-26 | 2019-04-09 | 上海兆芯集成电路有限公司 | 数据接收芯片 |
CN105321577B (zh) * | 2015-11-26 | 2018-09-14 | 上海兆芯集成电路有限公司 | 数据接收芯片 |
CN105469817B (zh) * | 2015-11-26 | 2018-06-12 | 上海兆芯集成电路有限公司 | 数据接收芯片 |
US9911469B1 (en) * | 2016-11-10 | 2018-03-06 | Micron Technology, Inc. | Apparatuses and methods for power efficient driver circuits |
CN107315442B (zh) * | 2017-06-30 | 2019-04-30 | 上海兆芯集成电路有限公司 | 控制器与参考电压产生方法 |
KR20190099933A (ko) * | 2018-02-20 | 2019-08-28 | 삼성전자주식회사 | 외부의 전압을 기반으로 동작 모드를 결정하는 메모리 장치 및 그 동작방법 |
CN110597529A (zh) * | 2019-09-29 | 2019-12-20 | 上海菱沃铂智能技术有限公司 | 一种用于微控制器参数校准的烧录器及烧录方法 |
JP7369597B2 (ja) | 2019-11-11 | 2023-10-26 | ニデックインスツルメンツ株式会社 | エンコーダ |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5206140A (en) * | 1988-06-24 | 1993-04-27 | Research Corporation Technologies, Inc. | Assay for soluble crosslinked fibrin polymers |
DE69309196T2 (de) * | 1992-08-31 | 1997-08-07 | Sgs Thomson Microelectronics | Ausgangstreiber einer integrierten Schaltung |
US6137720A (en) * | 1997-11-26 | 2000-10-24 | Cypress Semiconductor Corporation | Semiconductor reference voltage generator having a non-volatile memory structure |
US6309888B1 (en) * | 1998-09-04 | 2001-10-30 | Leuven Research & Development Vzw | Detection and determination of the stages of coronary artery disease |
US6226205B1 (en) | 1999-02-22 | 2001-05-01 | Stmicroelectronics, Inc. | Reference voltage generator for an integrated circuit such as a dynamic random access memory (DRAM) |
US6246258B1 (en) * | 1999-06-21 | 2001-06-12 | Xilinx, Inc. | Realizing analog-to-digital converter on a digital programmable integrated circuit |
US6316980B1 (en) * | 2000-06-30 | 2001-11-13 | Intel Corporation | Calibrating data strobe signal using adjustable delays with feedback |
US6445245B1 (en) * | 2000-10-06 | 2002-09-03 | Xilinx, Inc. | Digitally controlled impedance for I/O of an integrated circuit device |
JP4128763B2 (ja) * | 2000-10-30 | 2008-07-30 | 株式会社東芝 | 電圧切り替え回路 |
US6617895B2 (en) * | 2001-03-30 | 2003-09-09 | Intel Corporation | Method and device for symmetrical slew rate calibration |
US6456544B1 (en) * | 2001-03-30 | 2002-09-24 | Intel Corporation | Selective forwarding of a strobe based on a predetermined delay following a memory read command |
US6629225B2 (en) * | 2001-05-31 | 2003-09-30 | Intel Corporation | Method and apparatus for control calibration of multiple memory modules within a memory channel |
US6581017B2 (en) * | 2001-06-28 | 2003-06-17 | Intel Corporation | System and method for minimizing delay variation in double data rate strobes |
US6918048B2 (en) * | 2001-06-28 | 2005-07-12 | Intel Corporation | System and method for delaying a strobe signal based on a slave delay base and a master delay adjustment |
US6636821B2 (en) * | 2001-07-03 | 2003-10-21 | International Business Machines Corporation | Output driver impedance calibration circuit |
US6461828B1 (en) * | 2001-09-04 | 2002-10-08 | Syn X Pharma | Conjunctive analysis of biological marker expression for diagnosing organ failure |
US6965529B2 (en) * | 2002-06-21 | 2005-11-15 | Intel Coproration | Memory bus termination |
US7036053B2 (en) * | 2002-12-19 | 2006-04-25 | Intel Corporation | Two dimensional data eye centering for source synchronous data transfers |
US6922077B2 (en) * | 2003-06-27 | 2005-07-26 | Intel Corporation | Hybrid compensated buffer design |
-
2003
- 2003-11-14 US US10/714,075 patent/US7095245B2/en not_active Expired - Fee Related
-
2004
- 2004-11-05 AT AT04810345T patent/ATE386326T1/de not_active IP Right Cessation
- 2004-11-05 JP JP2006539652A patent/JP4422153B2/ja not_active Expired - Fee Related
- 2004-11-05 DE DE602004011809T patent/DE602004011809T2/de active Active
- 2004-11-05 CN CN2004800405040A patent/CN1906696B/zh not_active Expired - Fee Related
- 2004-11-05 WO PCT/US2004/036825 patent/WO2005050656A1/en active IP Right Grant
- 2004-11-05 EP EP04810345A patent/EP1683156B1/de not_active Not-in-force
- 2004-11-11 TW TW093134429A patent/TWI294217B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US7095245B2 (en) | 2006-08-22 |
CN1906696A (zh) | 2007-01-31 |
CN1906696B (zh) | 2010-05-05 |
JP2007520839A (ja) | 2007-07-26 |
WO2005050656A1 (en) | 2005-06-02 |
ATE386326T1 (de) | 2008-03-15 |
TWI294217B (en) | 2008-03-01 |
EP1683156A1 (de) | 2006-07-26 |
JP4422153B2 (ja) | 2010-02-24 |
US20050104624A1 (en) | 2005-05-19 |
EP1683156B1 (de) | 2008-02-13 |
TW200529559A (en) | 2005-09-01 |
DE602004011809T2 (de) | 2009-02-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |